From 44e4b9c5db6fdf29683720afbb142fdd92462c1f Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 2 Jul 2018 15:40:09 +0000
Subject: [PATCH] testbench should be skipped when te selected technology is
not stratixiv
---
applications/aartfaac/libraries/rsp_terminal/hdllib.cfg | 2 +-
.../rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd | 9 ++++++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
index 9ea5777692..94b0cca869 100644
--- a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
+++ b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = rsp_terminal
hdl_library_clause_name = rsp_terminal_lib
hdl_lib_uses_synth = common dp diag
-hdl_lib_uses_sim = rsp_serdes tr_nonbonded
+hdl_lib_uses_sim = rsp_serdes tr_nonbonded technology
hdl_lib_technology =
diff --git a/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd b/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd
index 1ae3778625..bcd12781af 100644
--- a/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd
+++ b/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd
@@ -20,9 +20,11 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE;
+LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.rsp_terminal_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
-- > as 3
-- > run -all --> OK, note that tb instances with g_phy_link_down_en=TRUE will cause expected 'Warning: rad_frame_rx timeout occurred!'
@@ -64,12 +66,13 @@ BEGIN
u_trnb_model_align : ENTITY work.tb_rsp_terminal GENERIC MAP (FALSE, 12, TRUE, "TRNB", 1, FALSE, c_phy_xon_delay, c_phy_propagation_delay) PORT MAP (tb_end_vec(7));
u_trnb_phy : ENTITY work.tb_rsp_terminal GENERIC MAP (FALSE, 12, FALSE, "TRNB", 0, FALSE, c_phy_xon_delay, c_phy_propagation_delay) PORT MAP (tb_end_vec(8));
- tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec OR c_tech_select_default /= c_tech_stratixiv ELSE '0';
p_tb_end : PROCESS
BEGIN
WAIT UNTIL tb_end='1';
- WAIT FOR 1 ns;
+ ASSERT (c_tech_select_default = c_tech_stratixiv) REPORT "Technology is not stratixiv, skipping testbench..." SEVERITY WARNING;
+ WAIT FOR 1 ms;
REPORT "Multi tb simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
--
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