diff --git a/libraries/base/common/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common/tb/vhdl/tb_common_complex_mult.vhd
index c81f6e8b3851b982e62aff14f543cf4008cde119..74a367becccb386f51113a143a8ce96f37299434 100644
--- a/libraries/base/common/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_complex_mult.vhd
@@ -26,9 +26,10 @@
-- > as 10
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
-LIBRARY IEEE;
+LIBRARY IEEE, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
+USE technology_lib.technology_select_pkg.ALL;
USE work.common_pkg.ALL;
USE work.common_lfsr_sequences_pkg.ALL;
USE work.tb_common_pkg.ALL;
@@ -55,6 +56,8 @@ ARCHITECTURE tb OF tb_common_complex_mult IS
CONSTANT c_max : INTEGER := 2**(g_in_dat_w-1)-1;
CONSTANT c_min : INTEGER := -2**(g_in_dat_w-1);
+ CONSTANT c_technology : NATURAL := c_tech_select_default;
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '0';
@@ -69,31 +72,16 @@ ARCHITECTURE tb OF tb_common_complex_mult IS
SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val
SIGNAL result_val_expected : STD_LOGIC;
SIGNAL result_val_rtl : STD_LOGIC;
- SIGNAL result_val_str : STD_LOGIC;
- SIGNAL result_val_str_stratix4 : STD_LOGIC;
SIGNAL result_val_stratix4 : STD_LOGIC;
- SIGNAL result_val_altera_rtl : STD_LOGIC;
- SIGNAL result_val_rtl_dsp : STD_LOGIC;
- SIGNAL dut_val_rtl_dsp : STD_LOGIC;
SIGNAL out_result_re : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- combinatorial result
SIGNAL out_result_im : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_re_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined results
SIGNAL result_re_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_str : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_str_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_re_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_altera_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_re_rtl_dsp : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_str : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_str_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_altera_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL result_im_rtl_dsp : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL dut_re_rtl_dsp : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
- SIGNAL dut_im_rtl_dsp : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
BEGIN
@@ -229,8 +217,10 @@ BEGIN
out_dat => result_val_expected
);
- u_dut_rtl : ENTITY work.common_complex_mult(rtl)
+ u_dut_rtl : ENTITY work.common_complex_mult
GENERIC MAP (
+ g_technology => c_technology,
+ g_variant => "RTL",
g_in_a_w => g_in_dat_w,
g_in_b_w => g_in_dat_w,
g_out_p_w => g_out_dat_w,
@@ -254,33 +244,10 @@ BEGIN
out_val => result_val_rtl
);
- u_dut_str : ENTITY work.common_complex_mult(str)
- GENERIC MAP (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- PORT MAP (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => result_re_str,
- out_pi => result_im_str,
- out_val => result_val_str
- );
-
- u_dut_stratix4 : ENTITY work.common_complex_mult(stratix4)
+ u_dut_stratix4 : ENTITY work.common_complex_mult
GENERIC MAP (
+ g_technology => c_technology,
+ g_variant => "IP",
g_in_a_w => g_in_dat_w,
g_in_b_w => g_in_dat_w,
g_out_p_w => g_out_dat_w,
@@ -304,94 +271,6 @@ BEGIN
out_val => result_val_stratix4
);
- u_dut_str_stratix4 : ENTITY work.common_complex_mult(str_stratix4)
- GENERIC MAP (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- PORT MAP (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => result_re_str_stratix4,
- out_pi => result_im_str_stratix4,
- out_val => result_val_str_stratix4
- );
-
- u_dut_altera_rtl : ENTITY work.common_complex_mult(altera_rtl)
- GENERIC MAP (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- PORT MAP (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => result_re_altera_rtl,
- out_pi => result_im_altera_rtl,
- out_val => result_val_altera_rtl
- );
-
- u_dut_rtl_dsp : ENTITY work.common_complex_mult(rtl_dsp)
- GENERIC MAP (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => 1,
- g_pipeline_product => 0,
- g_pipeline_adder => 0,
- g_pipeline_output => 1
- )
- PORT MAP (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => dut_re_rtl_dsp,
- out_pi => dut_im_rtl_dsp,
- out_val => dut_val_rtl_dsp
- );
-
- -- increase rtl_dsp latency to 3
- p_dut_rtl_dsp_clk : PROCESS(rst, clk)
- BEGIN
- IF rst='1' THEN
- result_re_rtl_dsp <= (OTHERS=>'0');
- result_im_rtl_dsp <= (OTHERS=>'0');
- result_val_rtl_dsp <= '0';
- ELSIF rising_edge(clk) THEN
- result_re_rtl_dsp <= dut_re_rtl_dsp;
- result_im_rtl_dsp <= dut_im_rtl_dsp;
- result_val_rtl_dsp <= dut_val_rtl_dsp;
- END IF;
- END PROCESS;
p_verify : PROCESS(rst, clk)
BEGIN
@@ -401,25 +280,10 @@ BEGIN
ASSERT result_im_rtl = result_im_expected REPORT "Error: IM wrong RTL result" SEVERITY ERROR;
ASSERT result_val_rtl = result_val_expected REPORT "Error: VAL wrong RTL result" SEVERITY ERROR;
- ASSERT result_re_str = result_re_expected REPORT "Error: RE wrong STR result" SEVERITY ERROR;
- ASSERT result_im_str = result_im_expected REPORT "Error: IM wrong STR result" SEVERITY ERROR;
- ASSERT result_val_str = result_val_expected REPORT "Error: VAL wrong STR result" SEVERITY ERROR;
-
ASSERT result_re_stratix4 = result_re_expected REPORT "Error: RE wrong stratix4 result" SEVERITY ERROR;
ASSERT result_im_stratix4 = result_im_expected REPORT "Error: IM wrong stratix4 result" SEVERITY ERROR;
ASSERT result_val_stratix4 = result_val_expected REPORT "Error: VAL wrong stratix4 result" SEVERITY ERROR;
- ASSERT result_re_str_stratix4 = result_re_expected REPORT "Error: RE wrong STR_stratix4 result" SEVERITY ERROR;
- ASSERT result_im_str_stratix4 = result_im_expected REPORT "Error: IM wrong STR_stratix4 result" SEVERITY ERROR;
- ASSERT result_val_str_stratix4 = result_val_expected REPORT "Error: VAL wrong STR_stratix4 result" SEVERITY ERROR;
-
- ASSERT result_re_altera_rtl = result_re_expected REPORT "Error: RE wrong altera_rtl result" SEVERITY ERROR;
- ASSERT result_im_altera_rtl = result_im_expected REPORT "Error: IM wrong altera_rtl result" SEVERITY ERROR;
- ASSERT result_val_altera_rtl = result_val_expected REPORT "Error: VAL wrong altera_rtl result" SEVERITY ERROR;
-
- ASSERT result_re_rtl_dsp = result_re_expected REPORT "Error: RE wrong rtl_dsp result" SEVERITY ERROR;
- ASSERT result_im_rtl_dsp = result_im_expected REPORT "Error: IM wrong rtl_dsp result" SEVERITY ERROR;
- ASSERT result_val_rtl_dsp = result_val_expected REPORT "Error: VAL wrong rtl_dsp result" SEVERITY ERROR;
END IF;
END IF;
END PROCESS;