From 4455a7907bc1058f904507fa6fd2962ffa789f27 Mon Sep 17 00:00:00 2001
From: Zanting <zanting>
Date: Mon, 8 Jun 2015 14:00:52 +0000
Subject: [PATCH] Updated to changed method names in pi_io_ddr.
---
.../designs/unb1_ddr3/tb/python/tc_unb1_ddr3.py | 12 ++++++------
.../designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3.py b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3.py
index 8b4f91da14..14da982de7 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3.py
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3.py
@@ -102,8 +102,8 @@ diag = pi_diagnostics.PiDiagnostics(tc, io, instanceName='', nof_str=c_nof_strea
if __name__ == "__main__":
## SETUP
- ddr.set_address(data=0)
- ddr.set_burstsize(data=256*32)
+ ddr.write_set_address(data=0)
+ ddr.write_access_size(data=256*32)
# Set diag mode on source and sink side to PRBS
diag.write_src_md(wrData=0)
@@ -117,14 +117,14 @@ if __name__ == "__main__":
do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
# Set DDR3 controller in write mode
- ddr.set_write()
+ ddr.write_mode_write()
# Clear source and sink of the diagnostics
diag.write_src_cnt_clr(wrData=1)
diag.write_snk_cnt_clr(wrData=1)
# Enable the DDR3 controller for writing
- ddr.burstbegin()
+ ddr.write_begin_access()
# Wait until controller is done
tc.sleep(1)
@@ -133,10 +133,10 @@ if __name__ == "__main__":
wordsWritten = diag.read_src_cnt()
# Set DDR3 controller in read mode
- ddr.set_read()
+ ddr.write_mode_read()
# Enable the DDR3 controller for reading
- ddr.burstbegin()
+ ddr.write_begin_access()
do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
index 9db3346255..53a9205a78 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
@@ -96,10 +96,10 @@ for rep in range(tc.repeat):
io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
# Set DDR controller in write mode and start writing
- ddr.set_address(data=start_address, vLevel=5)
- ddr.set_burstsize(data=nof_words, vLevel=5)
- ddr.set_write(vLevel=5)
- ddr.burstbegin(vLevel=5)
+ ddr.write_set_address(data=start_address, vLevel=5)
+ ddr.write_access_size(data=nof_words, vLevel=5)
+ ddr.write_mode_write(vLevel=5)
+ ddr.write_begin_access(vLevel=5)
# Tx sequence start
tx_seq.write_enable_cntr(vLevel=5)
@@ -116,8 +116,8 @@ for rep in range(tc.repeat):
rx_seq.write_enable_cntr(vLevel=5)
# Set DDR3 controller in read mode and start reading
- ddr.set_read(vLevel=5)
- ddr.burstbegin(vLevel=5)
+ ddr.write_mode_read(vLevel=5)
+ ddr.write_begin_access(vLevel=5)
# Rx sequence monitor
for mon in range(nof_mon):
--
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