diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 8125c67b0c4926a3fd6563035a5d88d0bd0274cf..40b52605bea043ecf8072a28934746c36c46eb4a 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -118,13 +118,13 @@ architecture str of ip_arria10_e1sg_jesd204b is
signal rx_avs_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxframe_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal f2_div1_cnt_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal rxframe_toggle_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal core_pll_locked : std_logic;
- signal mm_core_pll_locked_reg : std_logic;
- signal jesd204b_sysref_1 : std_logic;
- signal jesd204b_sysref_2 : std_logic;
- signal jesd204b_sysref_frameclk_1 : std_logic;
- signal jesd204b_sysref_frameclk_2 : std_logic;
+ signal mm_core_pll_locked : std_logic;
+ signal rxlink_sysref_1 : std_logic;
+ signal rxlink_sysref_2 : std_logic;
+ signal rxframe_sysref_1 : std_logic;
+ signal rxframe_sysref_2 : std_logic;
-- Data path
signal jesd204b_rx_link_data_arr : std_logic_vector(c_jesd204b_rx_data_w * g_nof_streams - 1 downto 0);
@@ -309,7 +309,7 @@ begin
sof => OPEN,
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
downto c_jesd204b_rx_somf_w * i),
- sysref => jesd204b_sysref_2
+ sysref => rxlink_sysref_2
);
-- One cycle rd-rdval latency, waitrequest = '0' fixed
@@ -329,7 +329,7 @@ begin
irq => open,
clk => mm_clk, -- use clk = mm_clk for av_* port
csr_reset => mm_rst,
- reset1_dsrt_qual => mm_core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
+ reset1_dsrt_qual => mm_core_pll_locked, -- core pll_locked synchronised to clk = mm_clk domain
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
@@ -395,32 +395,32 @@ begin
begin
if rising_edge(rxframe_clk) then
if rxframe_rst_n_arr(i) = '0' then
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= (others => '0');
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0');
- f2_div1_cnt_arr(i) <= '0';
+ rx_src_out_arr(i).data <= (others => '0');
+ rx_src_out_arr(i).channel <= (others => '0');
+ rxframe_toggle_arr(i) <= '0';
rx_src_out_arr(i).valid <= '0';
else
rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
if jesd204b_rx_link_valid_arr(i) = '0' then
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= (others => '0');
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0');
+ rx_src_out_arr(i).data <= (others => '0');
+ rx_src_out_arr(i).channel <= (others => '0');
else
- if f2_div1_cnt_arr(i) = '1' then
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
- jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
- c_jesd204b_rx_data_w * i);
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
- jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
- c_jesd204b_rx_somf_w * i);
+ if rxframe_toggle_arr(i) = '1' then
+ rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
+ c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
+ c_jesd204b_rx_data_w * i));
+ rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_somf_arr(
+ c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
+ c_jesd204b_rx_somf_w * i));
else
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
- jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
- c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w);
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
- jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
- c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w);
+ rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
+ c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
+ c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w));
+ rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_somf_arr(
+ c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
+ c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w));
end if;
- f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
+ rxframe_toggle_arr(i) <= not rxframe_toggle_arr(i);
end if;
end if;
end if;
@@ -432,15 +432,15 @@ begin
-- See: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
-- Figure 25, page 151
-----------------------------------------------------------------------------
- p_reclocksysref : process (rxlink_clk, core_pll_locked)
+ p_reclocksysref : process (core_pll_locked, rxlink_clk)
begin
if core_pll_locked = '0' then
- jesd204b_sysref_1 <= '0';
- jesd204b_sysref_2 <= '0';
+ rxlink_sysref_1 <= '0';
+ rxlink_sysref_2 <= '0';
jesd204b_sync_n_arr <= (others => '0');
elsif rising_edge(rxlink_clk) then
- jesd204b_sysref_1 <= jesd204b_sysref;
- jesd204b_sysref_2 <= jesd204b_sysref_1;
+ rxlink_sysref_1 <= jesd204b_sysref;
+ rxlink_sysref_2 <= rxlink_sysref_1;
jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr;
end if;
end process;
@@ -448,21 +448,19 @@ begin
-----------------------------------------------------------------------------
-- Move sysref from rxlink_clk to rxframe_clk
-----------------------------------------------------------------------------
- p_rx_sysref : process (rxframe_clk, core_pll_locked)
+ p_rx_sysref : process (core_pll_locked, rxframe_clk)
begin
if core_pll_locked = '0' then
- jesd204b_sysref_frameclk_1 <= '0';
- jesd204b_sysref_frameclk_2 <= '0';
+ rxframe_sysref_1 <= '0';
+ rxframe_sysref_2 <= '0';
rx_sysref <= '0';
- else
- if rising_edge(rxframe_clk) then
- jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2; -- sysref from rxlink_clk domain
- jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
- if jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' then
- rx_sysref <= '1';
- else
- rx_sysref <= '0';
- end if;
+ elsif rising_edge(rxframe_clk) then
+ rxframe_sysref_1 <= rxlink_sysref_2; -- sysref from rxlink_clk domain
+ rxframe_sysref_2 <= rxframe_sysref_1;
+ if rxframe_sysref_1 = '1' and rxframe_sysref_2 = '0' then
+ rx_sysref <= '1';
+ else
+ rx_sysref <= '0';
end if;
end if;
end process;
@@ -487,7 +485,7 @@ begin
port map (
in_rst => core_pll_locked,
clk => mm_clk,
- out_rst => mm_core_pll_locked_reg
+ out_rst => mm_core_pll_locked
);
-- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 1d44c476be539338716cd38fa5ca48177a7117a8..8d5a6a89609c77b6bf4b4b30d205f4aad439b44c 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -118,13 +118,13 @@ architecture str of ip_arria10_e2sg_jesd204b is
signal rx_avs_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxframe_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal f2_div1_cnt_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal rxframe_toggle_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal core_pll_locked : std_logic;
- signal mm_core_pll_locked_reg : std_logic;
- signal jesd204b_sysref_1 : std_logic;
- signal jesd204b_sysref_2 : std_logic;
- signal jesd204b_sysref_frameclk_1 : std_logic;
- signal jesd204b_sysref_frameclk_2 : std_logic;
+ signal mm_core_pll_locked : std_logic;
+ signal rxlink_sysref_1 : std_logic;
+ signal rxlink_sysref_2 : std_logic;
+ signal rxframe_sysref_1 : std_logic;
+ signal rxframe_sysref_2 : std_logic;
-- Data path
signal jesd204b_rx_link_data_arr : std_logic_vector(c_jesd204b_rx_data_w * g_nof_streams - 1 downto 0);
@@ -309,7 +309,7 @@ begin
sof => OPEN,
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
downto c_jesd204b_rx_somf_w * i),
- sysref => jesd204b_sysref_2
+ sysref => rxlink_sysref_2
);
-- One cycle rd-rdval latency, waitrequest = '0' fixed
@@ -329,7 +329,7 @@ begin
irq => open,
clk => mm_clk, -- use clk = mm_clk for av_* port
csr_reset => mm_rst,
- reset1_dsrt_qual => mm_core_pll_locked_reg, -- core pll_locked synchronised to clk = mm_clk domain
+ reset1_dsrt_qual => mm_core_pll_locked, -- core pll_locked synchronised to clk = mm_clk domain
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => mm_rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
@@ -395,32 +395,32 @@ begin
begin
if rising_edge(rxframe_clk) then
if rxframe_rst_n_arr(i) = '0' then
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= (others => '0');
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0');
- f2_div1_cnt_arr(i) <= '0';
+ rx_src_out_arr(i).data <= (others => '0');
+ rx_src_out_arr(i).channel <= (others => '0');
+ rxframe_toggle_arr(i) <= '0';
rx_src_out_arr(i).valid <= '0';
else
rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
if jesd204b_rx_link_valid_arr(i) = '0' then
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <= (others => '0');
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <= (others => '0');
+ rx_src_out_arr(i).data <= (others => '0');
+ rx_src_out_arr(i).channel <= (others => '0');
else
- if f2_div1_cnt_arr(i) = '1' then
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
- jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
- c_jesd204b_rx_data_w * i);
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
- jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
- c_jesd204b_rx_somf_w * i);
+ if rxframe_toggle_arr(i) = '1' then
+ rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
+ c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
+ c_jesd204b_rx_data_w * i));
+ rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_somf_arr(
+ c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
+ c_jesd204b_rx_somf_w * i));
else
- rx_src_out_arr(i).data(c_jesd204b_rx_framer_data_w - 1 downto 0) <=
- jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
- c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w);
- rx_src_out_arr(i).channel(c_jesd204b_rx_framer_somf_w - 1 downto 0) <=
- jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
- c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w);
+ rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
+ c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
+ c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w));
+ rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_somf_arr(
+ c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
+ c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w));
end if;
- f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
+ rxframe_toggle_arr(i) <= not rxframe_toggle_arr(i);
end if;
end if;
end if;
@@ -432,15 +432,15 @@ begin
-- See: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
-- Figure 25, page 151
-----------------------------------------------------------------------------
- p_reclocksysref : process (rxlink_clk, core_pll_locked)
+ p_reclocksysref : process (core_pll_locked, rxlink_clk)
begin
if core_pll_locked = '0' then
- jesd204b_sysref_1 <= '0';
- jesd204b_sysref_2 <= '0';
+ rxlink_sysref_1 <= '0';
+ rxlink_sysref_2 <= '0';
jesd204b_sync_n_arr <= (others => '0');
elsif rising_edge(rxlink_clk) then
- jesd204b_sysref_1 <= jesd204b_sysref;
- jesd204b_sysref_2 <= jesd204b_sysref_1;
+ rxlink_sysref_1 <= jesd204b_sysref;
+ rxlink_sysref_2 <= rxlink_sysref_1;
jesd204b_sync_n_arr <= jesd204b_sync_n_combined_arr;
end if;
end process;
@@ -448,21 +448,19 @@ begin
-----------------------------------------------------------------------------
-- Move sysref from rxlink_clk to rxframe_clk
-----------------------------------------------------------------------------
- p_rx_sysref : process (rxframe_clk, core_pll_locked)
+ p_rx_sysref : process (core_pll_locked, rxframe_clk)
begin
if core_pll_locked = '0' then
- jesd204b_sysref_frameclk_1 <= '0';
- jesd204b_sysref_frameclk_2 <= '0';
+ rxframe_sysref_1 <= '0';
+ rxframe_sysref_2 <= '0';
rx_sysref <= '0';
- else
- if rising_edge(rxframe_clk) then
- jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2; -- sysref from rxlink_clk domain
- jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
- if jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' then
- rx_sysref <= '1';
- else
- rx_sysref <= '0';
- end if;
+ elsif rising_edge(rxframe_clk) then
+ rxframe_sysref_1 <= rxlink_sysref_2; -- sysref from rxlink_clk domain
+ rxframe_sysref_2 <= rxframe_sysref_1;
+ if rxframe_sysref_1 = '1' and rxframe_sysref_2 = '0' then
+ rx_sysref <= '1';
+ else
+ rx_sysref <= '0';
end if;
end if;
end process;
@@ -487,7 +485,7 @@ begin
port map (
in_rst => core_pll_locked,
clk => mm_clk,
- out_rst => mm_core_pll_locked_reg
+ out_rst => mm_core_pll_locked
);
-- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only