diff --git a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
index e2aa2378a39b58a5f575316c8ffa5c9538b0e970..4114b4c0f60d60ce4459d3595d9c20cfaf7fe291 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
@@ -22,10 +22,13 @@
--
-- Author: R. van der Walle
-- Purpose:
--- . Test bench for dp_selector_arr
+-- Test bench for dp_selector_arr
-- Description:
--- . A data stream is offered to g_nof_streams=4 inputs of the DUT.
--- A process asserts mm accesses in time to switch the streams.
+-- . Two data stream arrays are offered with g_nof_streams=4 to two DUTs. The
+-- streams are distinguished by an offset in the data fiels, defined by
+-- c_pipe_data_offset
+-- . One DUT selects one array and the other DUT selects the other array.
+-- . The output of the DUTs are compared to the expected output.
--
-- Usage:
-- > as 10
@@ -67,6 +70,8 @@ ARCHITECTURE tb OF tb_dp_selector_arr IS
CONSTANT c_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000"; -- X"0877665544332211"
CONSTANT c_err_init : NATURAL := 247;
CONSTANT c_channel_init : INTEGER := 5; -- fixed
+
+ CONSTANT c_pipe_data_offset : INTEGER := 1000;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
@@ -76,12 +81,13 @@ ARCHITECTURE tb OF tb_dp_selector_arr IS
SIGNAL stimuli_src_in : t_dp_siso;
SIGNAL stimuli_src_out : t_dp_sosi;
- SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ref_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL pipe_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL out_pipe_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL out_ref_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL mm_mosi : t_mem_mosi;
- SIGNAL mm_miso : t_mem_miso;
+ SIGNAL mm_mosi_pipe : t_mem_mosi;
+ SIGNAL mm_mosi_ref : t_mem_mosi;
BEGIN
@@ -129,29 +135,52 @@ BEGIN
-- Insert optional gap between the packets
proc_common_wait_some_cycles(clk, g_pkt_gap);
END LOOP;
+
+ -- Determine expected sosi field values after end of stimuli
+ -- . e_qual
+ v_sosi.bsn := STD_LOGIC_VECTOR( UNSIGNED(c_bsn_init) + g_nof_repeat-1);
+ v_sosi.channel := TO_DP_CHANNEL(c_channel_init + g_nof_repeat-1);
+ v_sosi.err := TO_DP_ERROR(c_err_init + g_nof_repeat-1);
+ -- . account for g_pkt_len
+ v_sosi.data := INCR_UVEC(v_sosi.data, g_pkt_len-1);
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0)); -- wrap when >= 2**g_in_dat_w
+ proc_common_wait_some_cycles(clk, 100); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+
+ FOR I IN 0 TO c_nof_streams-1 LOOP
+ ASSERT SIGNED(v_sosi.channel)=SIGNED(out_ref_sosi_arr(I).channel) REPORT "Unexpected channel from dut_ref output." SEVERITY ERROR;
+ ASSERT SIGNED(v_sosi.channel)=SIGNED(out_pipe_sosi_arr(I).channel) REPORT "Unexpected channel from dut_pipe output." SEVERITY ERROR;
+ ASSERT SIGNED(v_sosi.err)=SIGNED(out_ref_sosi_arr(I).err) REPORT "Unexpected err from dut_ref output." SEVERITY ERROR;
+ ASSERT SIGNED(v_sosi.err)=SIGNED(out_pipe_sosi_arr(I).err) REPORT "Unexpected err from dut_pipe output." SEVERITY ERROR;
+ ASSERT SIGNED(v_sosi.bsn)=SIGNED(out_ref_sosi_arr(I).bsn) REPORT "Unexpected bsn from dut_ref output." SEVERITY ERROR;
+ ASSERT SIGNED(v_sosi.bsn)=SIGNED(out_pipe_sosi_arr(I).bsn) REPORT "Unexpected bsn from dut_pipe output." SEVERITY ERROR;
+ ASSERT SIGNED(v_sosi.data)=SIGNED(out_ref_sosi_arr(I).data) REPORT "Unexpected data from dut_ref output." SEVERITY ERROR;
+ ASSERT SIGNED(v_sosi.data)+c_pipe_data_offset=SIGNED(out_pipe_sosi_arr(I).data) REPORT "Unexpected data from dut_pipe output." SEVERITY ERROR;
+ END LOOP;
+
-- Signal end of stimuli
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
WAIT;
END PROCESS;
-
+
+ stimuli_src_in <= c_dp_siso_rdy;
+
gen_connect : FOR I IN 0 TO c_nof_streams-1 generate
- in_sosi_arr(i) <= stimuli_src_out;
+ ref_sosi_arr(i) <= stimuli_src_out;
END GENERATE;
-
- stimuli_src_in <= c_dp_siso_rdy;
-
- -- Add 1000 to pipe_sosi_arr data to differentiate it from ref_sosi_arr
- p_pipe_sosi: PROCESS(in_sosi_arr)
+
+ -- Add offset to pipe_sosi_arr data to differentiate it from ref_sosi_arr
+ p_pipe_sosi: PROCESS(stimuli_src_out)
BEGIN
- pipe_sosi_arr <= in_sosi_arr;
FOR I IN 0 TO c_nof_streams-1 LOOP
- pipe_sosi_arr(I).data <= RESIZE_DP_DATA(INCR_UVEC(in_sosi_arr(I).data, 1000)(g_in_dat_w-1 DOWNTO 0));
+ pipe_sosi_arr(I) <= stimuli_src_out;
+ pipe_sosi_arr(I).data <= RESIZE_DP_DATA(INCR_UVEC(stimuli_src_out.data, c_pipe_data_offset)(g_in_dat_w-1 DOWNTO 0));
END LOOP;
END PROCESS;
- u_dut : ENTITY work.dp_selector_arr
+ -- DUT that selects pipe_sosi_arr
+ u_dut_pipe : ENTITY work.dp_selector_arr
GENERIC MAP(
g_nof_arr => c_nof_streams,
g_pipeline => 1
@@ -161,8 +190,8 @@ BEGIN
mm_rst => rst,
mm_clk => clk,
- reg_selector_mosi => mm_mosi,
- reg_selector_miso => mm_miso,
+ reg_selector_mosi => mm_mosi_pipe,
+ reg_selector_miso => OPEN,
-- Streaming clock domain
dp_rst => rst,
@@ -170,24 +199,41 @@ BEGIN
-- ST sinks
pipe_sosi_arr => pipe_sosi_arr,
- ref_sosi_arr => in_sosi_arr,
+ ref_sosi_arr => ref_sosi_arr,
-- ST source
- out_sosi_arr => out_sosi_arr
+ out_sosi_arr => out_pipe_sosi_arr
+ );
+
+ -- DUT that selects ref_sosi_arr
+ u_dut_ref : ENTITY work.dp_selector_arr
+ GENERIC MAP(
+ g_nof_arr => c_nof_streams,
+ g_pipeline => 1
+ )
+ PORT MAP(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ reg_selector_mosi => mm_mosi_ref,
+ reg_selector_miso => OPEN,
+
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- ST sinks
+ pipe_sosi_arr => pipe_sosi_arr,
+ ref_sosi_arr => ref_sosi_arr,
+ -- ST source
+ out_sosi_arr => out_ref_sosi_arr
);
p_stim: PROCESS
BEGIN
WAIT UNTIL rst='0';
- proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi);
-
- WAIT FOR 500 ns;
-
- proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi);
-
- WAIT FOR 1200 ns;
-
- proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi);
-
+ proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi_ref); -- select ref_sosi_arr on dut_ref
+ proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe); -- select pipe_sosi_arr on dut_pipe
WAIT;
END PROCESS;