diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..917b7e8ebb3b47287e6dd5b69ed4d64dca566d3d
--- /dev/null
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -0,0 +1,126 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR   "$env(RADIOHDL)/libraries/technology/ip_arria10/mac_10g/generated/sim"
+set IP_TBDIR "$env(RADIOHDL)/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim"
+
+vlib ./work/
+
+vmap ip_arria10_mac_10g_alt_em10g32_140 ./work/
+
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/alt_em10g32.v"                                                                 -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/alt_em10g32unit.v"                                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_clk_rst.v"                                                     -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_clock_crosser.v"                                               -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32.v"                                                       -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32_gf_mult32_kc.v"                                          -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_creg_map.v"                                                    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_creg_top.v"                                                    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_frm_decoder.v"                                                 -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_rs_gmii_mii_layer.v"                                        -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_pipeline_base.v"                                               -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_reset_synchronizer.v"                                          -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rr_clock_crosser.v"                                            -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rst_cnt.v"                                                     -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_fctl_filter_crcpad_rem.v"                                   -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_fctl_overflow.v"                                            -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_fctl_preamble.v"                                            -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_frm_control.v"                                              -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_pfc_flow_control.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_pfc_pause_conversion.v"                                     -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_pkt_backpressure_control.v"                                 -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_rs_gmii_mii.v"                                              -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_rs_layer.v"                                                 -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_rs_xgmii.v"                                                 -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_status_aligner.v"                                           -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_top.v"                                                      -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_stat_mem.v"                                                    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_stat_reg.v"                                                    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_data_frm_gen.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_srcaddr_inserter.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_err_aligner.v"                                              -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_flow_control.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_frm_arbiter.v"                                              -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_frm_muxer.v"                                                -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pause_beat_conversion.v"                                    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pause_frm_gen.v"                                            -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pause_req.v"                                                -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_pfc_frm_gen.v"                                              -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_preamble_inserter.v"                                        -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_rs_layer.v"                                                 -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_rs_xgmii_layer.v"                                           -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_sc_fifo.v"                                                     -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_top.v"                                                      -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_gmii_decoder_dfa.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_encoder_dfa.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_gmii_mii_decoder_if.v"                                      -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_mii_encoder_if.v"                                      -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_mm_adapter/altera_eth_avalon_mm_adapter.v"          -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/altera_eth_avalon_st_adapter.v"          -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_rx.v"        -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter_avalon_st_tx.v"        -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/avalon_st_adapter.v"                     -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_rx.v"                   -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter_tx.v"                   -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_avalon_st_adapter/sideband_adapter.v"                      -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_64_xgmii_conversion.v"    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_32_to_64_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/adapters/altera_eth_xgmii_width_adaptor/alt_em10g_64_to_32_xgmii_conversion.v" -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_altsyncram_bundle.v"                                           -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_altsyncram.v"                                                  -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_hecc.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_dc_fifo_secc.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_hecc.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avalon_sc_fifo_secc.v"                                         -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_dec_18_12.v"                                               -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_dec_39_32.v"                                               -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_enc_12_18.v"                                               -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_ecc_enc_32_39.v"                                               -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_avst_to_gmii_if.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_gmii_to_avst_if.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_gmii_tsu.v"                                                    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_lpm_mult.v"                                                    -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_ptp_aligner.v"                                              -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_ptp_detector.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_rx_ptp_top.v"                                                  -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_crc_inserter.v"                                        -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_gmii_ptp_inserter.v"                                        -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_ptp_request_controller.v"                                   -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_ptp_top.v"                                                  -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_xgmii_crc_inserter.v"                                       -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_tx_xgmii_ptp_inserter.v"                                       -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_xgmii_tsu.v"                                                   -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc328generator.v"                                             -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32ctl8.v"                                                   -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_crc32galois8.v"                                                -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/mentor/rtl/alt_em10g32_gmii_crc_inserter.v"                                           -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/altera_avalon_dc_fifo.v"                                                              -work ip_arria10_mac_10g_alt_em10g32_140
+vlog "$IP_DIR/../alt_em10g32_140/sim/altera_dcfifo_synchronizer_bundle.v"                                                  -work ip_arria10_mac_10g_alt_em10g32_140
+vcom "$IP_DIR/ip_arria10_mac_10g.vhd"                                                                                                                              
diff --git a/libraries/technology/ip_arria10/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..3ea107bec536f0059208133f931916b5692cf7e8
--- /dev/null
+++ b/libraries/technology/ip_arria10/mac_10g/generate_ip.sh
@@ -0,0 +1,56 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014                                                        
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>           
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands                             
+#                                                                           
+# This program is free software: you can redistribute it and/or modify      
+# it under the terms of the GNU General Public License as published by      
+# the Free Software Foundation, either version 3 of the License, or         
+# (at your option) any later version.                                       
+#                                                                           
+# This program is distributed in the hope that it will be useful,           
+# but WITHOUT ANY WARRANTY; without even the implied warranty of            
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
+# GNU General Public License for more details.                              
+#                                                                           
+# You should have received a copy of the GNU General Public License         
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.     
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+#   Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+#   ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_mac_10g.qsys \
+              --synthesis=VHDL \
+              --simulation=VHDL \
+              --output-directory=generated \
+              --allow-mixed-language-simulation
+              
+# Also generate the testbench IP, but that appears not useful, because:
+# - the ip_arria10_mac_10g_tb.vhd does not apply stimuli to the MM, ST and XGMII interfaces
+# - the stimuli for the clocks seem wrong, because the period is 20 us.
+#qsys-generate ip_arria10_mac_10g.qsys \
+#              --synthesis=VHDL \
+#              --simulation=VHDL \
+#              --testbench=STANDARD \
+#              --testbench-simulation=VHDL \
+#              --output-directory=generated \
+#              --allow-mixed-language-simulation \
+#              --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..db6efe4fb5375a489bad2ca538c7e521e9f27077
--- /dev/null
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_mac_10g
+hdl_library_clause_name = ip_arria10_mac_10g_lib
+hdl_lib_uses = 
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+
+synth_files =
+    
+test_bench_files = 
+    # The generated testbench is listed here to create a simulation configuration for it. However
+    # the tb is commented because it is not useful, see generate_ip.sh.
+    #$RADIOHDL/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
+
+modelsim_search_libraries =
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip
+
+quartus_qip_files =
+    generated/ip_arria10_mac_10g.qip
diff --git a/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys b/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..33694749ff6c14d1bb3cc4b1e9d90ceffa743ddd
--- /dev/null
+++ b/libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
@@ -0,0 +1,222 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element alt_em10g32_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="csr" internal="alt_em10g32_0.csr" type="avalon" dir="end">
+  <port name="csr_read" internal="csr_read" />
+  <port name="csr_write" internal="csr_write" />
+  <port name="csr_writedata" internal="csr_writedata" />
+  <port name="csr_readdata" internal="csr_readdata" />
+  <port name="csr_waitrequest" internal="csr_waitrequest" />
+  <port name="csr_address" internal="csr_address" />
+ </interface>
+ <interface
+   name="tx_312_5_clk"
+   internal="alt_em10g32_0.tx_312_5_clk"
+   type="clock"
+   dir="end">
+  <port name="tx_312_5_clk" internal="tx_312_5_clk" />
+ </interface>
+ <interface
+   name="tx_156_25_clk"
+   internal="alt_em10g32_0.tx_156_25_clk"
+   type="clock"
+   dir="end">
+  <port name="tx_156_25_clk" internal="tx_156_25_clk" />
+ </interface>
+ <interface
+   name="rx_312_5_clk"
+   internal="alt_em10g32_0.rx_312_5_clk"
+   type="clock"
+   dir="end">
+  <port name="rx_312_5_clk" internal="rx_312_5_clk" />
+ </interface>
+ <interface
+   name="rx_156_25_clk"
+   internal="alt_em10g32_0.rx_156_25_clk"
+   type="clock"
+   dir="end">
+  <port name="rx_156_25_clk" internal="rx_156_25_clk" />
+ </interface>
+ <interface
+   name="csr_clk"
+   internal="alt_em10g32_0.csr_clk"
+   type="clock"
+   dir="end">
+  <port name="csr_clk" internal="csr_clk" />
+ </interface>
+ <interface
+   name="csr_rst_n"
+   internal="alt_em10g32_0.csr_rst_n"
+   type="reset"
+   dir="end">
+  <port name="csr_rst_n" internal="csr_rst_n" />
+ </interface>
+ <interface
+   name="tx_rst_n"
+   internal="alt_em10g32_0.tx_rst_n"
+   type="reset"
+   dir="end">
+  <port name="tx_rst_n" internal="tx_rst_n" />
+ </interface>
+ <interface
+   name="rx_rst_n"
+   internal="alt_em10g32_0.rx_rst_n"
+   type="reset"
+   dir="end">
+  <port name="rx_rst_n" internal="rx_rst_n" />
+ </interface>
+ <interface
+   name="avalon_st_tx"
+   internal="alt_em10g32_0.avalon_st_tx"
+   type="avalon_streaming"
+   dir="end">
+  <port
+     name="avalon_st_tx_startofpacket"
+     internal="avalon_st_tx_startofpacket" />
+  <port name="avalon_st_tx_endofpacket" internal="avalon_st_tx_endofpacket" />
+  <port name="avalon_st_tx_valid" internal="avalon_st_tx_valid" />
+  <port name="avalon_st_tx_data" internal="avalon_st_tx_data" />
+  <port name="avalon_st_tx_empty" internal="avalon_st_tx_empty" />
+  <port name="avalon_st_tx_error" internal="avalon_st_tx_error" />
+  <port name="avalon_st_tx_ready" internal="avalon_st_tx_ready" />
+ </interface>
+ <interface
+   name="avalon_st_pause"
+   internal="alt_em10g32_0.avalon_st_pause"
+   type="avalon_streaming"
+   dir="end">
+  <port name="avalon_st_pause_data" internal="avalon_st_pause_data" />
+ </interface>
+ <interface
+   name="xgmii_tx"
+   internal="alt_em10g32_0.xgmii_tx"
+   type="avalon_streaming"
+   dir="start">
+  <port name="xgmii_tx" internal="xgmii_tx" />
+ </interface>
+ <interface
+   name="avalon_st_txstatus"
+   internal="alt_em10g32_0.avalon_st_txstatus"
+   type="avalon_streaming"
+   dir="start">
+  <port name="avalon_st_txstatus_valid" internal="avalon_st_txstatus_valid" />
+  <port name="avalon_st_txstatus_data" internal="avalon_st_txstatus_data" />
+  <port name="avalon_st_txstatus_error" internal="avalon_st_txstatus_error" />
+ </interface>
+ <interface
+   name="xgmii_rx"
+   internal="alt_em10g32_0.xgmii_rx"
+   type="avalon_streaming"
+   dir="end">
+  <port name="xgmii_rx" internal="xgmii_rx" />
+ </interface>
+ <interface
+   name="link_fault_status_xgmii_rx"
+   internal="alt_em10g32_0.link_fault_status_xgmii_rx"
+   type="avalon_streaming"
+   dir="start">
+  <port
+     name="link_fault_status_xgmii_rx_data"
+     internal="link_fault_status_xgmii_rx_data" />
+ </interface>
+ <interface
+   name="avalon_st_rx"
+   internal="alt_em10g32_0.avalon_st_rx"
+   type="avalon_streaming"
+   dir="start">
+  <port name="avalon_st_rx_data" internal="avalon_st_rx_data" />
+  <port
+     name="avalon_st_rx_startofpacket"
+     internal="avalon_st_rx_startofpacket" />
+  <port name="avalon_st_rx_valid" internal="avalon_st_rx_valid" />
+  <port name="avalon_st_rx_empty" internal="avalon_st_rx_empty" />
+  <port name="avalon_st_rx_error" internal="avalon_st_rx_error" />
+  <port name="avalon_st_rx_ready" internal="avalon_st_rx_ready" />
+  <port name="avalon_st_rx_endofpacket" internal="avalon_st_rx_endofpacket" />
+ </interface>
+ <interface
+   name="avalon_st_rxstatus"
+   internal="alt_em10g32_0.avalon_st_rxstatus"
+   type="avalon_streaming"
+   dir="start">
+  <port name="avalon_st_rxstatus_valid" internal="avalon_st_rxstatus_valid" />
+  <port name="avalon_st_rxstatus_data" internal="avalon_st_rxstatus_data" />
+  <port name="avalon_st_rxstatus_error" internal="avalon_st_rxstatus_error" />
+ </interface>
+ <interface
+   name="unidirectional"
+   internal="alt_em10g32_0.unidirectional"
+   type="conduit"
+   dir="end">
+  <port name="unidirectional_en" internal="unidirectional_en" />
+  <port
+     name="unidirectional_remote_fault_dis"
+     internal="unidirectional_remote_fault_dis" />
+ </interface>
+ <module
+   kind="alt_em10g32"
+   version="14.0"
+   enabled="1"
+   name="alt_em10g32_0"
+   autoexport="1">
+  <parameter name="DEVICE_FAMILY" value="Arria 10" />
+  <parameter name="INSERT_ST_ADAPTOR" value="0" />
+  <parameter name="INSERT_CSR_ADAPTOR" value="0" />
+  <parameter name="INSERT_XGMII_ADAPTOR" value="1" />
+  <parameter name="DATAPATH_OPTION" value="3" />
+  <parameter name="ENABLE_SUPP_ADDR" value="0" />
+  <parameter name="ENABLE_PFC" value="0" />
+  <parameter name="PFC_PRIORITY_NUMBER" value="8" />
+  <parameter name="INSTANTIATE_STATISTICS" value="0" />
+  <parameter name="REGISTER_BASED_STATISTICS" value="0" />
+  <parameter name="PREAMBLE_PASSTHROUGH" value="0" />
+  <parameter name="ENABLE_TIMESTAMPING" value="0" />
+  <parameter name="ENABLE_PTP_1STEP" value="0" />
+  <parameter name="TSTAMP_FP_WIDTH" value="4" />
+  <parameter name="ENABLE_1G10G_MAC" value="0" />
+  <parameter name="ENABLE_MEM_ECC" value="0" />
+  <parameter name="ENABLE_UNIDIRECTIONAL" value="1" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>