diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index e0f61c1fbbd0961553fdba3c4c807f740863cfb1..42c193ec90fe81b7cde66ffa4787a91185afb0a7 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -90,6 +90,16 @@ PACKAGE tb_diag_pkg IS
SIGNAL rx_mosi : OUT t_mem_mosi;
SIGNAL rd_reg : OUT t_diag_seq_mm_reg); -- read all MM reg
+ PROCEDURE proc_diag_seq_rx_write_steps(CONSTANT c_stream : IN NATURAL;
+ CONSTANT c_steps_arr : IN t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0);
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl
+ SIGNAL tx_mosi : OUT t_mem_mosi;
+ SIGNAL rx_miso : IN t_mem_miso; -- rx ctrl
+ SIGNAL rx_mosi : OUT t_mem_mosi;
+ SIGNAL rd_reg : OUT t_diag_seq_mm_reg); -- read all MM reg
+
PROCEDURE proc_diag_seq_verify(CONSTANT c_stream : IN NATURAL;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL tx_miso : IN t_mem_miso;
@@ -129,6 +139,15 @@ PACKAGE BODY tb_diag_pkg IS
proc_mem_mm_bus_rd_latency(1, mm_clk);
rd_reg.rx_ctrl <= rx_miso.rddata(c_word_w-1 DOWNTO 0);
+ ---------------------------------------------------------------------------
+ -- Readback rx_steps
+ ---------------------------------------------------------------------------
+ FOR I IN 0 TO c_diag_seq_rx_reg_nof_steps-1 LOOP
+ proc_mem_mm_bus_rd(c_rx_offset + c_diag_seq_rx_reg_nof_steps_wi + I, mm_clk, rx_miso, rx_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_reg.rx_steps(I) <= TO_SINT(rx_miso.rddata(c_word_w-1 DOWNTO 0));
+ END LOOP;
+
---------------------------------------------------------------------------
-- Read cnt and stat
---------------------------------------------------------------------------
@@ -233,6 +252,28 @@ PACKAGE BODY tb_diag_pkg IS
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
END proc_diag_seq_rx_disable;
+ PROCEDURE proc_diag_seq_rx_write_steps(CONSTANT c_stream : IN NATURAL;
+ CONSTANT c_steps_arr : IN t_integer_arr(c_diag_seq_rx_reg_nof_steps-1 DOWNTO 0);
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL tx_miso : IN t_mem_miso; -- tx ctrl
+ SIGNAL tx_mosi : OUT t_mem_mosi;
+ SIGNAL rx_miso : IN t_mem_miso; -- rx ctrl
+ SIGNAL rx_mosi : OUT t_mem_mosi;
+ SIGNAL rd_reg : OUT t_diag_seq_mm_reg) IS -- read all MM reg
+ CONSTANT c_rx_offset : NATURAL := c_stream * 2**c_diag_seq_rx_reg_adr_w;
+ CONSTANT c_en : NATURAL := 1;
+ VARIABLE v_sel : NATURAL;
+ VARIABLE v_ctlr : NATURAL;
+ BEGIN
+ -- Write rx_steps
+ FOR I IN 0 TO c_diag_seq_rx_reg_nof_steps-1 LOOP
+ proc_mem_mm_bus_wr(c_rx_offset + c_diag_seq_rx_reg_nof_steps_wi + I, c_steps_arr(I), mm_clk, rx_miso, rx_mosi);
+ END LOOP;
+ proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
+ proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
+ END proc_diag_seq_rx_write_steps;
+
PROCEDURE proc_diag_seq_verify(CONSTANT c_stream : IN NATURAL;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL tx_miso : IN t_mem_miso;