diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
index 6e60576827b6b82a8cf5868f626744dfcf28322a..5f17d869a6c41027a47f14a33c9e6694d38fbd78 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
@@ -53,6 +53,10 @@ PACKAGE tb_dp_pkg IS
-- . To run all stimuli in Modelsim do:
-- > as 10
-- > run 400 us
+ --
+ -- References:
+ -- [1] https://support.astron.nl/confluence/pages/viewpage.action?spaceKey=L2M&title=L2+STAT+Decision%3A+Timing+in+Station
+ --
------------------------------------------------------------------------------
CONSTANT clk_period : TIME := 10 ns; -- 100 MHz
@@ -489,8 +493,7 @@ PACKAGE tb_dp_pkg IS
SIGNAL sop : IN STD_LOGIC;
SIGNAL bsn : IN STD_LOGIC_VECTOR);
- PROCEDURE proc_dp_verify_sync(CONSTANT c_start_bsn : IN NATURAL;
- CONSTANT c_sync_period : IN NATURAL;
+ PROCEDURE proc_dp_verify_sync(CONSTANT c_sync_period : IN NATURAL;
CONSTANT c_block_size : IN NATURAL;
SIGNAL clk : IN STD_LOGIC;
SIGNAL verify_en : IN STD_LOGIC;
@@ -2375,13 +2378,14 @@ PACKAGE BODY tb_dp_pkg IS
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output sync
+ -- . assume PPS and BSN grid as in [1]
-- . sync is defined such that it can only be active at sop
-- . assume that the fractional sync period varies between N and N-1 blocks
+ -- . c_start_bsn = 0 is at start of PPS and BSN grid, so BSN = 0 has a PPS.
-- . the fractional sync period starts with N blocks and fits e.g.
-- dp_bsn_source_v2, dp_bsn_sync_scheduler.
------------------------------------------------------------------------------
- PROCEDURE proc_dp_verify_sync(CONSTANT c_start_bsn : IN NATURAL; -- BSN of first sync, start of fractional periods
- CONSTANT c_sync_period : IN NATURAL; -- number of sample per sync period
+ PROCEDURE proc_dp_verify_sync(CONSTANT c_sync_period : IN NATURAL; -- number of sample per sync period
CONSTANT c_block_size : IN NATURAL; -- number of sample per block
SIGNAL clk : IN STD_LOGIC;
SIGNAL verify_en : IN STD_LOGIC;
@@ -2392,11 +2396,12 @@ PACKAGE BODY tb_dp_pkg IS
SIGNAL dbg_nof_blk : OUT NATURAL;
SIGNAL dbg_accumulate : OUT NATURAL;
SIGNAL dbg_expected_bsn : OUT NATURAL) IS
+ CONSTANT c_start_bsn : NATURAL := 0; -- BSN of first sync, start of fractional periods
CONSTANT c_bsn_w : NATURAL := sel_a_b(bsn'LENGTH>31, 31, bsn'LENGTH); -- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
CONSTANT c_nof_blk_min : NATURAL := c_sync_period / c_block_size; -- minimum number of blocks in sync period
CONSTANT c_extra : NATURAL := c_sync_period MOD c_block_size; -- number of extra samples in sync period
VARIABLE v_bsn : NATURAL := TO_UINT(bsn(c_bsn_w-1 DOWNTO 0));
- VARIABLE v_expected_sync : BOOLEAN := FALSE; -- default FALSE, e.g. when bsn < c_start_bsn is in the past
+ VARIABLE v_expected_sync : BOOLEAN := FALSE;
VARIABLE v_expected_bsn : NATURAL := c_start_bsn; -- BSN that is expected to have a sync, intialize with start BSN
VARIABLE v_nof_blk : NATURAL := c_nof_blk_min + 1; -- number of blocks in period, first sync period will be 1 block longer to achieve the fraction part
VARIABLE v_accumulate : INTEGER := c_block_size - c_extra; -- number of extra samples in period, first sync period will have v_accumulate more
@@ -2405,7 +2410,7 @@ PACKAGE BODY tb_dp_pkg IS
IF c_extra = 0 THEN
-- The sync period contains an integer number of blocks (c_extra = 0)
-- Determine directly whether the input bsn is expected to have a sync
- v_expected_sync := ((v_bsn - c_start_bsn) MOD c_nof_blk_min = 0);
+ v_expected_sync := (v_bsn MOD c_nof_blk_min) = 0;
ELSE
-- The sync period contains a fractional number of blocks
-- Determine next expected BSN with sync until the input bsn is reached using a loop
@@ -2413,21 +2418,19 @@ PACKAGE BODY tb_dp_pkg IS
v_expected_bsn := v_expected_bsn + v_nof_blk; -- next expected BSN to have a sync
v_nof_blk := c_nof_blk_min;
- v_accumulate := v_accumulate - c_extra;
+ v_accumulate := v_accumulate - c_extra;
IF v_accumulate < 0 THEN
v_nof_blk := v_nof_blk + 1;
- v_accumulate := v_accumulate + c_block_size;
+ v_accumulate := v_accumulate + c_block_size;
END IF;
END LOOP;
v_expected_sync := (v_bsn = v_expected_bsn);
END IF;
- IF verify_en = '1' THEN
- -- Debug signals, for view in Wave window
- dbg_nof_blk <= v_nof_blk;
- dbg_accumulate <= v_accumulate;
- dbg_expected_bsn <= v_expected_bsn;
- END IF;
+ -- Debug signals, for view in Wave window
+ dbg_nof_blk <= v_nof_blk;
+ dbg_accumulate <= v_accumulate;
+ dbg_expected_bsn <= v_expected_bsn;
-- Report sync and v_expected_sync
proc_dp_verify_sync(clk, verify_en, sync, sop, v_bsn, v_expected_bsn, to_sl(v_expected_sync));