diff --git a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd index 372f5187091d077d31a483556dbfb94ac2b4360d..8472efc40742fd61e77675a888cf84c742b56def 100644 --- a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd +++ b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd @@ -26,7 +26,7 @@ -- mms_st_histogram couples the st_histogram component which works entirely -- in the dp clock domain through st_histogram_reg that handles the cross -- domain conversion to the MM bus. --- +-- -- -- -------------------------------------- -- | mms_st_histogram | diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd index 4177fdd6c43189ed20f8075d5abe46372fae8057..49f9da8e02a1ad45e1bdd428fa56138ce8c75cbe 100644 --- a/libraries/dsp/st/src/vhdl/st_histogram.vhd +++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd @@ -67,7 +67,7 @@ -- read/write limitation and writing takes priority in this case -- . When a sync signal appears the RAM has to be swapped 2 cycles later so -- the first 2 cycles may not be read from the old RAM block --- +-- ------------------------------------------------------------------------------- LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib; diff --git a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd b/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd index 965564ea25c13c9cf8c3ca7feaf62bd5c7b1593b..c3ff7ed4940c9e0bac5fdb559ad66a360be245bc 100644 --- a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd +++ b/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd @@ -101,6 +101,7 @@ BEGIN -- . out : bin_reader_mosi (latency: 0) -- . out : bin_reader_mosi_pp (latency: 2) -- - out : rd_cnt_allowed_pp (latency: 2) + -- . out : dp_pipeline_src_out_pp (latency: 2) ----------------------------------------------------------------------------- bin_reader_mosi.rd <= snk_in.valid; -- when 1, count allowed bin_reader_mosi.address(c_adr_w-1 DOWNTO 0) <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low); diff --git a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd index 98424485a4e1ca3439959fe4098c2b610cf9aa4e..94b5895787d93f9e24bba470440a8a18b13e70a6 100644 --- a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd +++ b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd @@ -76,7 +76,7 @@ ARCHITECTURE str OF st_histogram_reg IS -- adr_w => 1, -- dat_w => c_word_w, -- nof_dat => 1, --- init_sl => g_default_value); +-- init_sl => g_default_value); BEGIN diff --git a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd index 8c74592e65fa4a7776fe01c12e73c17808437444..fbb57a6c0ff7b8c3037c3adad36ed70083133620 100644 --- a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd +++ b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd @@ -105,7 +105,7 @@ BEGIN ---------------------------------------------------------------------------- - -- Source: counter stimuli + -- Source: counter stimuli ---------------------------------------------------------------------------- p_data : PROCESS(dp_rst, dp_clk, st_histogram_snk_in) diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd index e997850df3698990fdbd06a4a0badc7598ac386b..36a9f7a16dc67b26dc57120b94ee2327f96428ba 100644 --- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd +++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd @@ -122,7 +122,7 @@ BEGIN ---------------------------------------------------------------------------- -- Source: stimuli - -- st_histogram_snk_in.data counter or toggle stimuli + -- st_histogram_snk_in.data counter or toggle or same_rw stimuli -- .valid with or without gap's in valid stimuli -- .sync sync stimuli ----------------------------------------------------------------------------