diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
index a6d40cb2bccb38242f00825a714baacddad21be5..b1c3e7b0b880e52e3392f2de050707eeeef07574 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
@@ -105,17 +105,11 @@ ARCHITECTURE str OF node_unb1_ddr3 IS
CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_seq_dat_w : NATURAL := 16;
- -- DDR3 DP
- SIGNAL wr_siso : t_dp_siso;
- SIGNAL wr_sosi : t_dp_sosi;
-
- SIGNAL rd_siso : t_dp_siso;
- SIGNAL rd_sosi : t_dp_sosi;
-
SIGNAL en_sync : STD_LOGIC;
SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); -- Output SOSI that contains the waveform data
+ SIGNAL in_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
BEGIN
@@ -165,16 +159,16 @@ BEGIN
wr_rst => dp_rst,
wr_fifo_usedw => OPEN,
- wr_sosi => wr_sosi,
- wr_siso => wr_siso,
+ wr_sosi => out_sosi_arr(0),
+ wr_siso => out_siso_arr(0),
-- Read FIFO clock domain
rd_clk => dp_clk,
rd_rst => dp_rst,
rd_fifo_usedw => OPEN,
- rd_sosi => rd_sosi,
- rd_siso => rd_siso,
+ rd_sosi => in_sosi_arr(0),
+ rd_siso => in_siso_arr(0),
term_ctrl_out => OPEN,
term_ctrl_in => OPEN,
@@ -265,7 +259,5 @@ BEGIN
in_sosi_arr => in_sosi_arr
);
- in_sosi_arr <= out_sosi_arr;
-
END str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
index a0b9b6c9894f168ca5d47c34c13bb44d8dfff8dc..2e40ac780259eabf5df4690114e0f7a264e24f6e 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py
@@ -33,6 +33,7 @@ Usage:
# System imports
import test_case
import node_io
+import pi_ddr3
import pi_diag_block_gen
import pi_diag_tx_seq
import pi_diag_data_buffer
@@ -60,50 +61,76 @@ io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
# Create instances for the periperals
c_nof_streams = 1
+c_nof_ddr3 = 1 # possible options: 1 or 2
+
bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=c_nof_streams, ramSizePerChannel=2**14)
db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, nofStreams=c_nof_streams)
tx_seq = pi_diag_tx_seq.PiDiagTxSeq(tc, io, nof_inst=c_nof_streams)
rx_seq = pi_diag_rx_seq.PiDiagRxSeq(tc, io, nof_inst=c_nof_streams)
+ddr3 = []
+for i in range(c_nof_ddr3):
+ ddr3.append(pi_ddr3.PiDDR3(tc, io, [i]))
+
+# Create object for DDR register map
+ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
+
##################################################################################################################
# Test
-# Sequence off
-#tx_seq.write(registers=[('control', 0x0 )])
+# Wait for power up (reset release)
+io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+
+# Initialization
tx_seq.write_disable()
rx_seq.write_disable()
-print 'read RX Sequencer result before run:'
-result = rx_seq.read_result()
-print result
+# Read RX Sequencer result before run
+rx_seq.read_result()
-# Sequence restart
-tx_seq.write_init(17)
-io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+# Wait for the DDR3 to become available
+#ddr.read_io_ddr()
+do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
+
+# Set DDR3 controller in write mode and start writing
+start_address = 0
+nof_words = 100
+ddr.set_address(data=start_address)
+ddr.set_burstsize(data=nof_words)
+ddr.set_write()
+ddr.burstbegin()
+
+# Tx sequence start
tx_seq.write_enable_cntr()
+
+# Tx sequence monitor
for rep in range(tc.repeat):
io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
tx_seq.read_cnt()
+# Wait until controller write access is done
+do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
+
+# Rx sequence start
rx_seq.write_enable_cntr()
+
+# Set DDR3 controller in read mode and start reading
+ddr.set_read()
+ddr.burstbegin()
+
+# Rx sequence monitor
for rep in range(tc.repeat):
io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
rx_seq.read_cnt()
-print 'read RX Sequencer result after run:'
-result = rx_seq.read_result() # result: 3 cannot occur, 2 = no data, 1 = error, 0 = ok
-print result
-#tc.append_log(3, 'result: %d' % result[0])
+# Wait until controller read access is done
+do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)
-#tx_seq.write_enable_prbs()
+rx_seq.read_result()
io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-result = rx_seq.read_result() # result: 3 cannot occur, 2 = no data, 1 = error, 0 = ok
-#tc.append_log(3, 'result: %d' % result[0])
-
-if result[0]!=0:
- tc.set_result('FAILED')
+rx_seq.read_result()
# End