diff --git a/applications/unb1_correlator/hdllib.cfg b/applications/unb1_correlator/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4726ed8a2c0e2be3a7da3cdfaa83b44e5fedb8a3
--- /dev/null
+++ b/applications/unb1_correlator/hdllib.cfg
@@ -0,0 +1,29 @@
+hdl_lib_name = unb1_correlator
+hdl_library_clause_name = unb1_correlator_lib
+hdl_lib_uses = common mm i2c unb1_board correlator
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+quartus_copy_files =
+ quartus/qsys_unb1_correlator.qsys .
+
+synth_files =
+ $HDL_BUILD_DIR/quartus/unb1_correlator/qsys_unb1_correlator.vhd
+ src/vhdl/mmm_unb1_correlator.vhd
+ src/vhdl/unb1_correlator.vhd
+
+test_bench_files =
+ tb/vhdl/tb_unb1_correlator.vhd
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ quartus/unb1_correlator_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
diff --git a/applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys b/applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..7bc5f01a210f39750c48ccf7e8a83497d0e86480
--- /dev/null
+++ b/applications/unb1_correlator/quartus/qsys_unb1_correlator.qsys
@@ -0,0 +1,2171 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altpll_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "368";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element c0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ }
+ element altpll_0.c0
+ {
+ datum _clockDomain
+ {
+ value = "mm_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c1
+ {
+ datum _clockDomain
+ {
+ value = "epcs_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c2
+ {
+ datum _clockDomain
+ {
+ value = "tse_clk";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element reg_epcs.mem
+ {
+ datum baseAddress
+ {
+ value = "288";
+ type = "long";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "376";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element reg_mmdp_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "400";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "224";
+ type = "long";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element reg_remu.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "long";
+ }
+ }
+ element reg_dpmm_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "384";
+ type = "long";
+ }
+ }
+ element reg_dpmm_data.mem
+ {
+ datum baseAddress
+ {
+ value = "392";
+ type = "long";
+ }
+ }
+ element reg_mmdp_data.mem
+ {
+ datum baseAddress
+ {
+ value = "408";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\unb_unb1_minimal\\build\\synth\\quartus}";
+ type = "String";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element altpll_0.pll_slave
+ {
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "320";
+ type = "long";
+ }
+ }
+ element reg_dpmm_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ }
+ element reg_dpmm_data
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ }
+ element reg_epcs
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ }
+ element reg_mmdp_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ }
+ element reg_mmdp_data
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ }
+ element reg_remu
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "352";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "336";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "192";
+ type = "long";
+ }
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName">unb1_minimal_sopc.qpf</parameter>
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="1" />
+ <parameter name="timeStamp" value="1414142788570" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="avs_eth_0_ram_write"
+ internal="avs_eth_0.ram_write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_ram_write_export_from_the_avs_eth_0"
+ internal="coe_ram_write_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_reg_read"
+ internal="avs_eth_0.reg_read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reg_read_export_from_the_avs_eth_0"
+ internal="coe_reg_read_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_ctrl_readdata"
+ internal="reg_mmdp_ctrl.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_mmdp_ctrl"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface name="c0_out_clk" internal="c0.out_clk" type="clock" dir="start">
+ <port name="mm_clk" internal="out_clk" />
+ </interface>
+ <interface
+ name="pio_system_info_address"
+ internal="pio_system_info.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_pio_system_info"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="pio_pps_address"
+ internal="pio_pps.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_pio_pps"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="pio_pps_reset"
+ internal="pio_pps.reset"
+ type="conduit"
+ dir="end">
+ <port name="coe_reset_export_from_the_pio_pps" internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="reg_epcs_readdata"
+ internal="reg_epcs.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_epcs"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="pio_pps_readdata"
+ internal="pio_pps.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_pio_pps"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="pio_system_info_writedata"
+ internal="pio_system_info.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_pio_system_info"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_unb_sens_reset"
+ internal="reg_unb_sens.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_reg_unb_sens"
+ internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_tse_write"
+ internal="avs_eth_0.tse_write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_tse_write_export_from_the_avs_eth_0"
+ internal="coe_tse_write_export" />
+ </interface>
+ <interface
+ name="reg_wdi_reset"
+ internal="reg_wdi.reset"
+ type="conduit"
+ dir="end">
+ <port name="coe_reset_export_from_the_reg_wdi" internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_data_readdata"
+ internal="reg_dpmm_data.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_dpmm_data"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_ctrl_writedata"
+ internal="reg_mmdp_ctrl.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_mmdp_ctrl"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_ctrl_address"
+ internal="reg_dpmm_ctrl.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_dpmm_ctrl"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="rom_system_info_clk"
+ internal="rom_system_info.clk"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_clk_export_from_the_rom_system_info"
+ internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
+ type="conduit"
+ dir="end">
+ <port name="coe_reset_export_from_the_reg_remu" internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="reg_unb_sens_read"
+ internal="reg_unb_sens.read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_read_export_from_the_reg_unb_sens"
+ internal="coe_read_export" />
+ </interface>
+ <interface
+ name="reg_unb_sens_write"
+ internal="reg_unb_sens.write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_write_export_from_the_reg_unb_sens"
+ internal="coe_write_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_data_clk"
+ internal="reg_dpmm_data.clk"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_clk_export_from_the_reg_dpmm_data"
+ internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="reg_unb_sens_clk"
+ internal="reg_unb_sens.clk"
+ type="conduit"
+ dir="end">
+ <port name="coe_clk_export_from_the_reg_unb_sens" internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reg_writedata_export_from_the_avs_eth_0"
+ internal="coe_reg_writedata_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_ctrl_readdata"
+ internal="reg_dpmm_ctrl.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_dpmm_ctrl"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end">
+ <port name="coe_read_export_from_the_reg_wdi" internal="coe_read_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_data_reset"
+ internal="reg_mmdp_data.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_reg_mmdp_data"
+ internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_reg_write"
+ internal="avs_eth_0.reg_write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reg_write_export_from_the_avs_eth_0"
+ internal="coe_reg_write_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_data_writedata"
+ internal="reg_mmdp_data.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_mmdp_data"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_epcs_read"
+ internal="reg_epcs.read"
+ type="conduit"
+ dir="end">
+ <port name="coe_read_export_from_the_reg_epcs" internal="coe_read_export" />
+ </interface>
+ <interface
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_remu"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="reg_unb_sens_readdata"
+ internal="reg_unb_sens.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_unb_sens"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_ram_address"
+ internal="avs_eth_0.ram_address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_ram_address_export_from_the_avs_eth_0"
+ internal="coe_ram_address_export" />
+ </interface>
+ <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end">
+ <port name="coe_clk_export_from_the_pio_pps" internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="pio_system_info_readdata"
+ internal="pio_system_info.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_pio_system_info"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="rom_system_info_writedata"
+ internal="rom_system_info.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_rom_system_info"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_data_address"
+ internal="reg_dpmm_data.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_dpmm_data"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_ctrl_write"
+ internal="reg_mmdp_ctrl.write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_write_export_from_the_reg_mmdp_ctrl"
+ internal="coe_write_export" />
+ </interface>
+ <interface
+ name="reg_wdi_address"
+ internal="reg_wdi.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_wdi"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_reset"
+ internal="avs_eth_0.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_avs_eth_0"
+ internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="pio_system_info_write"
+ internal="pio_system_info.write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_write_export_from_the_pio_system_info"
+ internal="coe_write_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_tse_address"
+ internal="avs_eth_0.tse_address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_tse_address_export_from_the_avs_eth_0"
+ internal="coe_tse_address_export" />
+ </interface>
+ <interface
+ name="pio_pps_write"
+ internal="pio_pps.write"
+ type="conduit"
+ dir="end">
+ <port name="coe_write_export_from_the_pio_pps" internal="coe_write_export" />
+ </interface>
+ <interface
+ name="rom_system_info_write"
+ internal="rom_system_info.write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_write_export_from_the_rom_system_info"
+ internal="coe_write_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_irq"
+ internal="avs_eth_0.irq"
+ type="conduit"
+ dir="end">
+ <port name="coe_irq_export_to_the_avs_eth_0" internal="coe_irq_export" />
+ </interface>
+ <interface
+ name="reg_epcs_reset"
+ internal="reg_epcs.reset"
+ type="conduit"
+ dir="end">
+ <port name="coe_reset_export_from_the_reg_epcs" internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="rom_system_info_read"
+ internal="rom_system_info.read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_read_export_from_the_rom_system_info"
+ internal="coe_read_export" />
+ </interface>
+ <interface
+ name="altpll_0_phasedone_conduit"
+ internal="altpll_0.phasedone_conduit"
+ type="conduit"
+ dir="end">
+ <port name="phasedone_from_the_altpll_0" internal="phasedone" />
+ </interface>
+ <interface
+ name="clk_0_clk_in_reset"
+ internal="clk_0.clk_in_reset"
+ type="reset"
+ dir="end">
+ <port name="reset_n" internal="reset_n" />
+ </interface>
+ <interface
+ name="avs_eth_0_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_tse_writedata_export_from_the_avs_eth_0"
+ internal="coe_tse_writedata_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_ctrl_clk"
+ internal="reg_mmdp_ctrl.clk"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_clk_export_from_the_reg_mmdp_ctrl"
+ internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_tse_readdata_export_to_the_avs_eth_0"
+ internal="coe_tse_readdata_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_ram_read"
+ internal="avs_eth_0.ram_read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_ram_read_export_from_the_avs_eth_0"
+ internal="coe_ram_read_export" />
+ </interface>
+ <interface name="clk_0_clk_in" internal="clk_0.clk_in" type="clock" dir="end">
+ <port name="clk_0" internal="in_clk" />
+ </interface>
+ <interface
+ name="reg_dpmm_ctrl_read"
+ internal="reg_dpmm_ctrl.read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_read_export_from_the_reg_dpmm_ctrl"
+ internal="coe_read_export" />
+ </interface>
+ <interface
+ name="reg_remu_writedata"
+ internal="reg_remu.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_remu"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_data_write"
+ internal="reg_dpmm_data.write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_write_export_from_the_reg_dpmm_data"
+ internal="coe_write_export" />
+ </interface>
+ <interface
+ name="reg_unb_sens_writedata"
+ internal="reg_unb_sens.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_unb_sens"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface name="altpll_0_c2" internal="altpll_0.c2" type="clock" dir="start">
+ <port name="tse_clk" internal="c2" />
+ </interface>
+ <interface name="altpll_0_c1" internal="altpll_0.c1" type="clock" dir="start">
+ <port name="epcs_clk" internal="c1" />
+ </interface>
+ <interface
+ name="avs_eth_0_reg_readdata"
+ internal="avs_eth_0.reg_readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reg_readdata_export_to_the_avs_eth_0"
+ internal="coe_reg_readdata_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_ctrl_reset"
+ internal="reg_dpmm_ctrl.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_reg_dpmm_ctrl"
+ internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="pio_debug_wave_external_connection"
+ internal="pio_debug_wave.external_connection"
+ type="conduit"
+ dir="end">
+ <port name="out_port_from_the_pio_debug_wave" internal="out_port" />
+ </interface>
+ <interface
+ name="avs_eth_0_tse_read"
+ internal="avs_eth_0.tse_read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_tse_read_export_from_the_avs_eth_0"
+ internal="coe_tse_read_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_data_writedata"
+ internal="reg_dpmm_data.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_dpmm_data"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_wdi_writedata"
+ internal="reg_wdi.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_wdi"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="pio_system_info_reset"
+ internal="pio_system_info.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_pio_system_info"
+ internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="pio_system_info_read"
+ internal="pio_system_info.read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_read_export_from_the_pio_system_info"
+ internal="coe_read_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_data_clk"
+ internal="reg_mmdp_data.clk"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_clk_export_from_the_reg_mmdp_data"
+ internal="coe_clk_export" />
+ </interface>
+ <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end">
+ <port name="coe_clk_export_from_the_reg_wdi" internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_ram_readdata_export_to_the_avs_eth_0"
+ internal="coe_ram_readdata_export" />
+ </interface>
+ <interface
+ name="reg_remu_write"
+ internal="reg_remu.write"
+ type="conduit"
+ dir="end">
+ <port name="coe_write_export_from_the_reg_remu" internal="coe_write_export" />
+ </interface>
+ <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end">
+ <port name="coe_clk_export_from_the_reg_epcs" internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_data_read"
+ internal="reg_mmdp_data.read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_read_export_from_the_reg_mmdp_data"
+ internal="coe_read_export" />
+ </interface>
+ <interface
+ name="reg_epcs_writedata"
+ internal="reg_epcs.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_epcs"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="pio_wdi_external_connection"
+ internal="pio_wdi.external_connection"
+ type="conduit"
+ dir="end">
+ <port name="out_port_from_the_pio_wdi" internal="out_port" />
+ </interface>
+ <interface
+ name="reg_dpmm_data_reset"
+ internal="reg_dpmm_data.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_reg_dpmm_data"
+ internal="coe_reset_export" />
+ </interface>
+ <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end">
+ <port name="coe_clk_export_from_the_reg_remu" internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_ctrl_read"
+ internal="reg_mmdp_ctrl.read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_read_export_from_the_reg_mmdp_ctrl"
+ internal="coe_read_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_clk"
+ internal="avs_eth_0.clk"
+ type="conduit"
+ dir="end">
+ <port name="coe_clk_export_from_the_avs_eth_0" internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_ctrl_address"
+ internal="reg_mmdp_ctrl.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_mmdp_ctrl"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="reg_epcs_write"
+ internal="reg_epcs.write"
+ type="conduit"
+ dir="end">
+ <port name="coe_write_export_from_the_reg_epcs" internal="coe_write_export" />
+ </interface>
+ <interface
+ name="rom_system_info_readdata"
+ internal="rom_system_info.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_rom_system_info"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_ctrl_reset"
+ internal="reg_mmdp_ctrl.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_reg_mmdp_ctrl"
+ internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_data_readdata"
+ internal="reg_mmdp_data.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_mmdp_data"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface
+ name="reg_wdi_write"
+ internal="reg_wdi.write"
+ type="conduit"
+ dir="end">
+ <port name="coe_write_export_from_the_reg_wdi" internal="coe_write_export" />
+ </interface>
+ <interface
+ name="reg_wdi_readdata"
+ internal="reg_wdi.readdata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_readdata_export_to_the_reg_wdi"
+ internal="coe_readdata_export" />
+ </interface>
+ <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end">
+ <port name="coe_read_export_from_the_pio_pps" internal="coe_read_export" />
+ </interface>
+ <interface
+ name="pio_system_info_clk"
+ internal="pio_system_info.clk"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_clk_export_from_the_pio_system_info"
+ internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="pio_pps_writedata"
+ internal="pio_pps.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_pio_pps"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_epcs_address"
+ internal="reg_epcs.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_epcs"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_data_read"
+ internal="reg_dpmm_data.read"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_read_export_from_the_reg_dpmm_data"
+ internal="coe_read_export" />
+ </interface>
+ <interface
+ name="rom_system_info_reset"
+ internal="rom_system_info.reset"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reset_export_from_the_rom_system_info"
+ internal="coe_reset_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_tse_waitrequest_export_to_the_avs_eth_0"
+ internal="coe_tse_waitrequest_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_ctrl_writedata"
+ internal="reg_dpmm_ctrl.writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_writedata_export_from_the_reg_dpmm_ctrl"
+ internal="coe_writedata_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_data_address"
+ internal="reg_mmdp_data.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_mmdp_data"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="reg_unb_sens_address"
+ internal="reg_unb_sens.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_unb_sens"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="reg_dpmm_ctrl_clk"
+ internal="reg_dpmm_ctrl.clk"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_clk_export_from_the_reg_dpmm_ctrl"
+ internal="coe_clk_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_reg_address"
+ internal="avs_eth_0.reg_address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_reg_address_export_from_the_avs_eth_0"
+ internal="coe_reg_address_export" />
+ </interface>
+ <interface
+ name="rom_system_info_address"
+ internal="rom_system_info.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_rom_system_info"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="reg_mmdp_data_write"
+ internal="reg_mmdp_data.write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_write_export_from_the_reg_mmdp_data"
+ internal="coe_write_export" />
+ </interface>
+ <interface
+ name="reg_remu_address"
+ internal="reg_remu.address"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_address_export_from_the_reg_remu"
+ internal="coe_address_export" />
+ </interface>
+ <interface
+ name="altpll_0_areset_conduit"
+ internal="altpll_0.areset_conduit"
+ type="conduit"
+ dir="end">
+ <port name="areset_to_the_altpll_0" internal="areset" />
+ </interface>
+ <interface
+ name="altpll_0_locked_conduit"
+ internal="altpll_0.locked_conduit"
+ type="conduit"
+ dir="end">
+ <port name="locked_from_the_altpll_0" internal="locked" />
+ </interface>
+ <interface
+ name="reg_dpmm_ctrl_write"
+ internal="reg_dpmm_ctrl.write"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_write_export_from_the_reg_dpmm_ctrl"
+ internal="coe_write_export" />
+ </interface>
+ <interface
+ name="avs_eth_0_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
+ type="conduit"
+ dir="end">
+ <port
+ name="coe_ram_writedata_export_from_the_avs_eth_0"
+ internal="coe_ram_writedata_export" />
+ </interface>
+ <interface
+ name="altpll_0_c3_conduit"
+ internal="altpll_0.c3_conduit"
+ type="conduit"
+ dir="end">
+ <port name="c3_from_the_altpll_0" internal="c3" />
+ </interface>
+ <interface
+ name="reg_remu_read"
+ internal="reg_remu.read"
+ type="conduit"
+ dir="end">
+ <port name="coe_read_export_from_the_reg_remu" internal="coe_read_export" />
+ </interface>
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">sopc_unb1_minimal_onchip_memory2_0</parameter>
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="true" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
+ <parameter name="WIDTH_CLOCK" value="10" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="CLK0_MULTIPLY_BY" value="2" />
+ <parameter name="CLK1_MULTIPLY_BY" value="4" />
+ <parameter name="CLK2_MULTIPLY_BY" value="5" />
+ <parameter name="CLK3_MULTIPLY_BY" value="8" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DIVIDE_BY" value="5" />
+ <parameter name="CLK2_DIVIDE_BY" value="1" />
+ <parameter name="CLK3_DIVIDE_BY" value="5" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_PHASE_SHIFT" value="0" />
+ <parameter name="CLK2_PHASE_SHIFT" value="0" />
+ <parameter name="CLK3_PHASE_SHIFT" value="0" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK2_DUTY_CYCLE" value="50" />
+ <parameter name="CLK3_DUTY_CYCLE" value="50" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PORT_extclk0" value="" />
+ <parameter name="PORT_extclk1" value="" />
+ <parameter name="PORT_extclk2" value="" />
+ <parameter name="PORT_extclk3" value="" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_USED" />
+ <parameter name="PORT_clk3" value="PORT_UNUSED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="PORT_UNUSED" />
+ <parameter name="PORT_clk7" value="PORT_UNUSED" />
+ <parameter name="PORT_clk8" value="PORT_UNUSED" />
+ <parameter name="PORT_clk9" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_LOCKED" value="PORT_USED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 5 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 4 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 40.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 20.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 40.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 20.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="50000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_remu">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_epcs">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_ctrl">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_dpmm_data">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_ctrl">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mmdp_data">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="is_hardcopy_compatible" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuID_stored" value="0" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="setting_perfCounterWidth" value="32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="muldiv_multiplierType" value="DSPBlock" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_lineSize" value="32" />
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="dataAddrWidth" value="18" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_remu.mem' start='0x100' end='0x120' /><slave name='reg_epcs.mem' start='0x120' end='0x140' /><slave name='altpll_0.pll_slave' start='0x140' end='0x150' /><slave name='pio_debug_wave.s1' start='0x150' end='0x160' /><slave name='pio_wdi.s1' start='0x160' end='0x170' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x170' end='0x178' /><slave name='pio_pps.mem' start='0x178' end='0x180' /><slave name='reg_dpmm_ctrl.mem' start='0x180' end='0x188' /><slave name='reg_dpmm_data.mem' start='0x188' end='0x190' /><slave name='reg_mmdp_ctrl.mem' start='0x190' end='0x198' /><slave name='reg_mmdp_data.mem' start='0x198' end='0x1A0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ </module>
+ <module kind="altera_clock_bridge" version="11.1" enabled="1" name="c0">
+ <parameter name="DERIVED_CLOCK_RATE" value="50000000" />
+ <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+ <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0170" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="altpll_0.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0140" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="altpll_0.inclk_interface" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_debug_wave.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0150" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0160" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00c0" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00e0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="rom_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0178" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_remu.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_epcs.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0120" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dpmm_ctrl.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0180" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dpmm_data.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0188" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0190" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_mmdp_data.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0198" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="altpll_0.inclk_interface_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="altpll_0.inclk_interface_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_dpmm_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dpmm_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_dpmm_data.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dpmm_data.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mmdp_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_data.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mmdp_data.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="cpu_0.reset_n" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="cpu_0.reset_n" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="c0.in_clk" />
+</system>
diff --git a/applications/unb1_correlator/quartus/unb1_correlator_pins.tcl b/applications/unb1_correlator/quartus/unb1_correlator_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..14269479e73f36b1c577213c4d4438c7d8409b05
--- /dev/null
+++ b/applications/unb1_correlator/quartus/unb1_correlator_pins.tcl
@@ -0,0 +1,26 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+
diff --git a/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..62d92a26c97031d3098fe6643255d2be613789c4
--- /dev/null
+++ b/applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -0,0 +1,463 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, remu_lib, epcs_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE work.qsys_unb1_minimal_pkg.ALL;
+
+
+ENTITY mmm_unb1_minimal IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_use_qsys : BOOLEAN := FALSE
+ );
+ PORT (
+ xo_clk : IN STD_LOGIC;
+ xo_rst_n : IN STD_LOGIC;
+ xo_rst : IN STD_LOGIC;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : OUT STD_LOGIC;
+ mm_locked : OUT STD_LOGIC;
+
+ epcs_clk : OUT STD_LOGIC;
+
+ pout_wdi : OUT STD_LOGIC;
+
+ -- Manual WDI override
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso;
+
+ -- system_info
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso;
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso;
+
+ -- PPSH
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso;
+
+ -- eth1g
+ eth1g_tse_clk : OUT STD_LOGIC;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso;
+ -- EPCS read
+ reg_dpmm_data_mosi : OUT t_mem_mosi;
+ reg_dpmm_data_miso : IN t_mem_miso;
+ reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
+ reg_dpmm_ctrl_miso : IN t_mem_miso;
+
+ -- EPCS write
+ reg_mmdp_data_mosi : OUT t_mem_mosi;
+ reg_mmdp_data_miso : IN t_mem_miso;
+ reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
+ reg_mmdp_ctrl_miso : IN t_mem_miso;
+
+ -- EPCS status/control
+ reg_epcs_mosi : OUT t_mem_mosi;
+ reg_epcs_miso : IN t_mem_miso;
+
+ -- Remote Update
+ reg_remu_mosi : OUT t_mem_mosi;
+ reg_remu_miso : IN t_mem_miso
+ );
+END mmm_unb1_minimal;
+
+ARCHITECTURE str OF mmm_unb1_minimal IS
+
+ CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT c_epcs_clk_period : TIME := 50 ns; -- 20 MHz
+
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
+ CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+
+ SIGNAL i_mm_clk : STD_LOGIC := '1';
+ SIGNAL i_epcs_clk : STD_LOGIC := '1';
+
+ ----------------------------------------------------------------------------
+ -- mm_file component
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_mm_clk_period : TIME := c_mm_clk_period;
+ g_update_on_change : BOOLEAN := FALSE;
+ g_mm_rd_latency : NATURAL := 1
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+BEGIN
+
+ mm_clk <= i_mm_clk;
+ epcs_clk <= i_epcs_clk;
+
+
+ ----------------------------------------------------------------------------
+ -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ ----------------------------------------------------------------------------
+ gen_mm_file_io : IF g_sim = TRUE GENERATE
+
+ i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
+ mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
+ i_epcs_clk <= NOT i_epcs_clk AFTER c_epcs_clk_period/2;
+
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
+ u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- SOPC or QSYS for synthesis
+ ----------------------------------------------------------------------------
+ gen_sopc : IF g_sim = FALSE AND g_use_qsys = FALSE GENERATE
+ u_sopc : ENTITY work.sopc_unb1_minimal
+ PORT MAP (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+ gen_qsys : IF g_sim = FALSE AND g_use_qsys = TRUE GENERATE
+ u_qsys : qsys_unb1_minimal
+ PORT MAP (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+END str;
diff --git a/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd b/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..07f050907f5c7229352e870a56b33ddb1243ee8c
--- /dev/null
+++ b/applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
@@ -0,0 +1,288 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+
+ENTITY unb1_correlator IS
+ GENERIC (
+ g_design_name : STRING := "unb1_correlator";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC
+ );
+END unb1_correlator;
+
+
+ARCHITECTURE str OF unb1_correlator IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 1);
+ -- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 0, 0, 0, 1);
+
+ CONSTANT c_use_qsys : BOOLEAN := g_design_name="unb1_correlator_qsys";
+ CONSTANT c_use_sopc : BOOLEAN := NOT c_use_qsys;
+
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL st_rst : STD_LOGIC;
+ SIGNAL st_clk : STD_LOGIC;
+
+ SIGNAL epcs_clk : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- EPCS read
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+
+ -- EPCS write
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+
+ -- EPCS status/control
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+
+ -- Remote Update
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => epcs_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_unb1_correlator
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ epcs_clk => epcs_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso
+ );
+
+END str;
+
diff --git a/applications/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd b/applications/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e9abf603b5d8a9308c8f25c352aa07042ec2ad15
--- /dev/null
+++ b/applications/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
@@ -0,0 +1,123 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- Description:
+-- Usage:
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_unb1_correlator IS
+END tb_unb1_correlator;
+
+ARCHITECTURE tb OF tb_unb1_correlator IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 7; -- Back node 3
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ -- DUT
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_unb1_correlator : ENTITY work.unb1_correlator
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp
+ );
+
+END tb;