From 4163b5c9356ff29180e2faf3e93852c0a6516dc8 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Thu, 25 Jun 2015 15:17:28 +0000
Subject: [PATCH] Initilal commit
---
.../python/tc_apertif_unb1_cor_mesh_ref.log | 36 +++
.../tb/python/tc_apertif_unb1_cor_mesh_ref.py | 251 ++++++++++++++++
.../tb/vhdl/tb_apertif_unb1_cor_mesh_ref.vhd | 274 ++++++++++++++++++
3 files changed, 561 insertions(+)
create mode 100644 applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.log
create mode 100644 applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.py
create mode 100644 applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/vhdl/tb_apertif_unb1_cor_mesh_ref.vhd
diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.log b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.log
new file mode 100644
index 0000000000..33e1cca835
--- /dev/null
+++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.log
@@ -0,0 +1,36 @@
+[2015:06:25 16:30:06] - (3) TB - >>>
+[2015:06:25 16:30:06] - (1) TB - >>> Title : Test script for unb1_board_bg_mesh_db
+[2015:06:25 16:30:06] - (3) TB - >>>
+[2015:06:25 16:30:06] - (3) TB -
+[2015:06:25 16:30:06] - (3) TB - >>>
+[2015:06:25 16:30:06] - (3) TB - >>> Write settings to the block generator
+[2015:06:25 16:30:06] - (3) TB - >>>
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-0: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-1: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-2: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-3: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-0: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-1: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-2: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-3: write_block_gen_settings
+[2015:06:25 16:30:09] - (5) TB - BG - . samplesPerPacket = 128
+[2015:06:25 16:30:09] - (5) TB - BG - . blocksPerSync = 16
+[2015:06:25 16:30:09] - (5) TB - BG - . gapSize = 64
+[2015:06:25 16:30:09] - (5) TB - BG - . memLowAddr = 0
+[2015:06:25 16:30:09] - (5) TB - BG - . memHighAddr = 127
+[2015:06:25 16:30:09] - (5) TB - BG - . BSNInit = 42
+[2015:06:25 16:30:09] - (3) TB - >>>
+[2015:06:25 16:30:09] - (3) TB - >>> Write data to the waveform RAM of all channels
+[2015:06:25 16:30:09] - (3) TB - >>>
+[2015:06:25 16:30:09] - (3) TB - >>>
+[2015:06:25 16:30:09] - (3) TB - >>> Start the block generator
+[2015:06:25 16:30:09] - (3) TB - >>>
+[2015:06:25 16:30:09] - (3) TB -
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-0: write_enable
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-1: write_enable
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-2: write_enable
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, FN-3: write_enable
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-0: write_enable
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-1: write_enable
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-2: write_enable
+[2015:06:25 16:30:09] - (5) TB - BG - UNB-0, BN-3: write_enable
diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.py b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.py
new file mode 100644
index 0000000000..d4ac32a521
--- /dev/null
+++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/python/tc_apertif_unb1_cor_mesh_ref.py
@@ -0,0 +1,251 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2012
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for the reorder_transpose entity.
+
+ Description:
+
+
+ Usage:
+
+ > python tc_reorder_transpose.py --unb 0 --fn 0 --sim
+
+"""
+
+###############################################################################
+# System imports
+import test_case
+import node_io
+import unb_apertif as apr
+import pi_diag_block_gen
+import pi_diag_data_buffer
+import pi_bsn_monitor
+import pi_ppsh
+import pi_ss_reorder
+import dsp_test
+
+import sys, os
+import subprocess
+import time
+import pylab as pl
+import numpy as np
+import scipy as sp
+import random
+from tools import *
+from common import *
+import mem_init_file
+
+###############################################################################
+
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+
+# Constants/Generics that are shared between VHDL and Python
+# Name Value Default Description
+# START_VHDL_GENERICS
+g_nof_input_streams = 8 # 16
+
+g_blocks_per_sync = 800000 #32 # 781250
+
+if tc.sim == True:
+ g_blocks_per_sync = 16 # 781250
+
+
+# Define settings for the block generator
+c_bg_nof_streams = g_nof_input_streams
+c_bg_ram_size = 128
+c_db_nof_streams = g_nof_input_streams
+c_db_ram_size = c_bg_ram_size
+c_samples_per_packet = 128
+c_gapsize = 64
+c_mem_low_addr = 0
+c_mem_high_addr = c_samples_per_packet-1
+c_bsn_init = 42
+c_in_dat_w = 8
+
+c_write_bg_data = False
+c_write_bg_data_to_file = False
+
+tc.append_log(3, '>>>')
+tc.append_log(1, '>>> Title : Test script for unb1_board_bg_mesh_db' )
+tc.append_log(3, '>>>')
+tc.append_log(3, '')
+tc.set_result('PASSED')
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Create block generator instance
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, g_nof_input_streams, c_bg_ram_size)
+
+# Create databuffer instances
+db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = '', nofStreams=c_db_nof_streams, ramSizePerStream=c_db_ram_size)
+
+# def __init__(self, tc, io, nof_inputs = 4, nof_outputs = 8, frameSize = 128, instanceNr = 0, nodeNr = None, instanceName = 'INPUT'):
+
+reorder_input = []
+for i in tc.nodeNrs:
+ reorder_input.append(pi_ss_reorder.PiSsReorder(tc, io, nof_inputs = 8, nof_outputs = 8, frameSize = 1, nodeNr = i, instanceName = 'INPUT'))
+
+reorder_mesh = []
+for i in tc.nodeNrs:
+ reorder_mesh.append(pi_ss_reorder.PiSsReorder(tc, io, nof_inputs = 12, nof_outputs = 12, frameSize = 1, nodeNr = i, instanceName = 'MESH'))
+
+
+# Create dsp_test instance for helpful methods
+dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
+
+pps = pi_ppsh.PiPpsh(tc, io, nodeNr=tc.nodeFnNrs)
+
+#-- Output FN 0, FN 1, FN 2, FN 3, BN 0, BN 1,BN 2, BN 3,
+#-- 0 1 1 1 1 0 0 0 0
+#-- 1 0 2 4 6 1 1 7 5
+#-- 2 3 3 3 3 2 2 2 2
+#-- 3 6 0 2 4 5 3 1 7
+#-- 4 5 5 5 5 4 4 4 4
+#-- 5 4 6 0 2 7 5 3 1
+#-- 6 7 7 7 7 6 6 6 6
+#-- 7 2 4 6 0 1 7 5 3
+
+input_reorder_settings = [[[1,0,3,6,5,4,7,2]],
+ [[1,2,3,0,5,6,7,4]],
+ [[1,4,3,2,5,0,7,6]],
+ [[1,6,3,4,5,2,7,0]],
+ [[0,1,2,5,4,7,6,1]],
+ [[0,1,2,3,4,5,6,7]],
+ [[0,7,2,1,4,3,6,5]],
+ [[0,5,2,7,4,1,6,3]]]
+
+#-- Output FN 0, FN 1, FN 2, FN 3, BN 0, BN 1,BN 2, BN 3,
+#-- 0 2 11 8 5 0 0 0 0
+#-- 1 5 2 11 8 3 3 3 3
+#-- 2 8 5 2 11 6 6 6 6
+#-- 3 11 8 5 2 9 9 9 9
+#-- 4 0 0 0 0 11 2 5 8
+#-- 5 3 3 3 3 2 5 8 11
+#-- 6 6 6 6 6 5 8 11 2
+#-- 7 9 9 9 9 8 11 2 5
+#-- 8 4 7 10 1 1 4 7 10
+#-- 9 1 4 7 10 4 7 10 1
+#-- 10 10 1 4 7 7 10 1 7
+#-- 11 7 10 1 4 10 1 4 3
+
+mesh_reorder_settings = [[[ 2, 5, 8,11, 0, 3, 6, 9, 4, 1,10, 7]],
+ [[11, 2, 5, 8, 0, 3, 6, 9, 7, 4, 1,10]],
+ [[ 8,11, 2, 5, 0, 3, 6, 9,10, 7, 4, 1]],
+ [[ 5, 8,11, 2, 0, 3, 6, 9, 1,10, 7, 4]],
+ [[ 0, 3, 6, 9,11, 2, 5, 8, 1, 4, 7,10]],
+ [[ 0, 3, 6, 9, 2, 5, 8,11, 4, 7,10, 1]],
+ [[ 0, 3, 6, 9, 5, 8,11, 2, 7,10, 1, 4]],
+ [[ 0, 3, 6, 9, 8,11, 2, 5,10, 1, 7, 3]]]
+
+if __name__ == "__main__":
+
+ print tc.nodeNrs
+ for h in tc.nodeNrs:
+ print h
+
+ # Set the input reorder units.
+# for i in tc.nodeNrs:
+# setting = reorder_input[i].create_selection_buf(input_reorder_settings[i])
+# value = [int(setting[0])]
+# reorder_input[i].write_selects(value)
+#
+# # Set the mesh reorder units.
+# for i in tc.nodeNrs:
+# setting = reorder_mesh[i].create_selection_buf(mesh_reorder_settings[i])
+# value = [int(setting[0])]
+# reorder_mesh[i].write_selects(value)
+
+
+ ################################################################################
+ ##
+ ## Initialize the blockgenerators
+ ##
+ ################################################################################
+ # - Write settings to the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Write settings to the block generator')
+ tc.append_log(3, '>>>')
+
+ bg.write_block_gen_settings(c_samples_per_packet, g_blocks_per_sync, c_gapsize, c_mem_low_addr, c_mem_high_addr, c_bsn_init)
+
+ # - Create a list with the input data and write it to the RAMs of the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Write data to the waveform RAM of all channels')
+ tc.append_log(3, '>>>')
+ inputData = []
+
+ dataList=[]
+ for h in tc.nodeNrs:
+ nodeData = []
+ for i in xrange(0, g_nof_input_streams):
+ data = []
+ for j in xrange(0, c_samples_per_packet):
+ real = h & (2**c_in_dat_w-1) # Node number in real part
+ imag = i & (2**c_in_dat_w-1) # Streamnumber in imag part
+ data.append((imag << c_in_dat_w) + real)
+ nodeData.append(data)
+ dataList.append(nodeData)
+
+ inputData = []
+ for h in tc.nodeNrs:
+ for i in xrange(g_nof_input_streams):
+ if c_write_bg_data == True:
+ bg.write_waveform_ram(dataList[h][i], i, [h])
+ if c_write_bg_data_to_file == True:
+ filename = "../../src/hex/node" + str(h) + "/bg_in_data_" + str(i) + ".hex"
+ mem_init_file.list_to_hex(list_in=dataList[h][i], filename=filename, mem_width=c_nof_complex*c_in_dat_w, mem_depth=2**(ceil_log2(c_bg_ram_size)))
+ dataListComplex = bg.convert_concatenated_to_complex(dataList[h][i], c_in_dat_w)
+ inputData.append(dataListComplex)
+
+ # - Enable the block generator
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '>>> Start the block generator')
+ tc.append_log(3, '>>>')
+ tc.append_log(3, '')
+
+ bg.write_enable()
+
+ do_until_ge(db.read_nof_words, ms_retry=3000, val=c_db_ram_size, s_timeout=3600)
+
+ ###############################################################################
+ #
+ # Read data from data buffer
+ #
+ ###############################################################################
+ db_out = []
+ for i in range(c_bg_nof_streams):
+ db_out.append(flatten(db.read_data_buffer(streamNr=i, n=c_db_ram_size, radix='uns', width=c_in_dat_w, nofColumns=8)))
+
+ ###############################################################################
+ # End
+ tc.set_section_id('')
+ tc.append_log(3, '')
+ tc.append_log(3, '>>>')
+ tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+ tc.append_log(3, '>>>')
+
+ sys.exit(tc.get_result())
+
+
+
diff --git a/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/vhdl/tb_apertif_unb1_cor_mesh_ref.vhd b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/vhdl/tb_apertif_unb1_cor_mesh_ref.vhd
new file mode 100644
index 0000000000..bf3b01e8fb
--- /dev/null
+++ b/applications/apertif/designs/apertif_unb1_cor_mesh_ref/tb/vhdl/tb_apertif_unb1_cor_mesh_ref.vhd
@@ -0,0 +1,274 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Verify that unb1_terminal_bg_mesh_db can simulate
+-- Description:
+--
+-- Usage:
+-- > as 8
+-- > run 10 us
+
+LIBRARY IEEE, common_lib, unb1_board_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.tb_unb1_board_pkg.ALL;
+
+ENTITY tb_apertif_unb1_cor_mesh_ref IS
+END tb_apertif_unb1_cor_mesh_ref;
+
+ARCHITECTURE tb OF tb_apertif_unb1_cor_mesh_ref IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_sim_level : NATURAL := 1;
+
+ CONSTANT c_nof_bn : NATURAL := 4;
+ CONSTANT c_nof_fn : NATURAL := 4;
+ CONSTANT c_nof_nodes : NATURAL := c_nof_bn + c_nof_fn;
+ CONSTANT c_ena_mesh_reorder: BOOLEAN := FALSE;--TRUE;
+
+ CONSTANT c_sim_unb_nr : NATURAL := 0;
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+
+ CONSTANT c_ext_clk_period : TIME := 5 ns; -- 200 MHz
+ CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_tr_clk_period : TIME := 6400 ps; -- 156.25 MHz XO on UniBoard
+
+ TYPE t_mesh_arr IS ARRAY (c_nof_nodes-1 DOWNTO 0) OF STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+ -- DUT
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL ext_pps : STD_LOGIC;
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_nof_nodes-1 DOWNTO 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_nof_nodes-1 DOWNTO 0);
+
+ SIGNAL tr_clk : STD_LOGIC := '0';
+
+ SIGNAL FN_BN_0_TX_arr : t_mesh_arr;
+ SIGNAL FN_BN_0_RX_arr : t_mesh_arr;
+ SIGNAL FN_BN_1_TX_arr : t_mesh_arr;
+ SIGNAL FN_BN_1_RX_arr : t_mesh_arr;
+ SIGNAL FN_BN_2_TX_arr : t_mesh_arr;
+ SIGNAL FN_BN_2_RX_arr : t_mesh_arr;
+ SIGNAL FN_BN_3_TX_arr : t_mesh_arr;
+ SIGNAL FN_BN_3_RX_arr : t_mesh_arr;
+
+ ------------------------------------------------------------------------------
+ -- BN & FN mesh side serial I/O
+ ------------------------------------------------------------------------------
+ SIGNAL bn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
+ SIGNAL bn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
+ SIGNAL fn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
+ SIGNAL fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
+
+BEGIN
+
+ -- Run 1 ms
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- 1GbE XO clock (25 MHz)
+ tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2; -- Transceiver clock (156.25 MHz)
+
+ ext_pps <= '0'; -- not used
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ VERSION <= c_version;
+
+ ------------------------------------------------------------------------------
+ -- UniBoard
+ ------------------------------------------------------------------------------
+ gen_bn: FOR BN IN 0 TO c_nof_bn-1 GENERATE
+ u_bn : ENTITY work.apertif_unb1_cor_mesh_ref
+ GENERIC MAP (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => (BN + 4)
+ )
+ PORT MAP (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(BN + c_nof_fn),
+ ETH_SGOUT => eth_txp(BN + c_nof_fn),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
+ );
+
+ -- Use mesh_io block to create 3arr format for the mesh model.
+ u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
+ GENERIC MAP (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ PORT MAP (
+ tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
+ rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
+ );
+ END GENERATE;
+
+ gen_fn: FOR FN IN 0 TO c_nof_fn-1 GENERATE
+ u_fn : ENTITY work.apertif_unb1_cor_mesh_ref
+ GENERIC MAP (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => FN
+ )
+ PORT MAP (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(FN),
+ ETH_SGOUT => eth_txp(FN),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_RX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_TX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_RX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_TX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_RX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_TX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_RX_arr(FN)
+ );
+
+ -- Use mesh_io block to create 3arr format for the mesh model.
+ u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
+ GENERIC MAP (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ PORT MAP (
+ tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
+ rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_TX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_RX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_TX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_RX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_TX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_RX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_TX_arr(FN)
+ );
+ END GENERATE;
+
+ -- Direct interconnect BN0<->FN0.
+ no_mesh : IF c_nof_bn=1 AND c_nof_fn=1 GENERATE
+ fn_in_mesh_serial_3arr(0) <= bn_out_mesh_serial_3arr(0);
+ bn_in_mesh_serial_3arr(0) <= fn_out_mesh_serial_3arr(0);
+ END GENERATE;
+
+ -- Mesh model
+ gen_mesh : IF c_nof_bn>1 OR c_nof_fn>1 GENERATE
+ u_mesh_model_serial : ENTITY unb1_board_lib.unb1_board_mesh_model_sl
+ GENERIC MAP(
+ g_reorder => c_ena_mesh_reorder
+ )
+ PORT MAP (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
+ bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
+ fn_rx_sl_3arr => fn_in_mesh_serial_3arr
+ );
+ END GENERATE;
+
+END tb;
--
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