diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/python/tc_unb1_ddr3_reorder_seq.py b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/python/tc_unb1_ddr3_reorder_seq.py
index 23339e7d8c8eeadc0b031e89126d75f946deeac2..adb3395375beea0b6cc74bad2272f1ba1b59cf6c 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/python/tc_unb1_ddr3_reorder_seq.py
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/python/tc_unb1_ddr3_reorder_seq.py
@@ -63,21 +63,38 @@ if __name__ == "__main__":
     tc.append_log(3, '>>>')
     tc.append_log(1, '>>> Title : Test case for the unb1_ddr3_reorder design on %s' % tc.unb_nodes_string())
     tc.append_log(3, '>>>')
+    tc.append_log(3, '>>> Testcase run mode: %s' % tc.runmode)
     tc.append_log(3, '')
         
+    c_ena_pre_transpose = False
+    c_nof_streams   = 1
+    c_data_w_ratio  = 4
+    c_wr_chunksize  = 176       # must be a factor of c_data_w_ratio=4
+    c_rd_chunksize  = 16        # must be a factor of c_data_w_ratio=4
+    c_rd_nof_chunks = 11        # must be c_wr_chunksize = c_rd_nof_chunks*c_rd_chunksize
+    c_rd_interval   = c_rd_nof_chunks
+    c_gapsize       = 0
+    c_blocksize     = c_wr_chunksize + c_gapsize
+    c_nof_blocks    = 64  #sel_a_b(tc.sim, 16, 800000)  # must be multiple of c_rd_chunksize or of c_rd_nof_chunks FIXME ????
+    c_pagesize      = c_nof_blocks*c_blocksize
+    tc.append_log(3, 'Script transpose parameters, these must match the compile parameters of the design:')
+    tc.append_log(3, '   . c_ena_pre_transpose  = %s ' % c_ena_pre_transpose)
+    tc.append_log(3, '   . c_nof_streams        = %d ' % c_nof_streams)
+    tc.append_log(3, '   . c_data_w_ratio       = %d ' % c_data_w_ratio)
+    tc.append_log(3, '   . c_wr_chunksize       = %d ' % c_wr_chunksize)
+    tc.append_log(3, '   . c_rd_chunksize       = %d ' % c_rd_chunksize)
+    tc.append_log(3, '   . c_rd_nof_chunks      = %d ' % c_rd_nof_chunks)
+    tc.append_log(3, '   . c_rd_interval        = %d ' % c_rd_interval)
+    tc.append_log(3, '   . c_gapsize            = %d ' % c_gapsize)
+    tc.append_log(3, '   . c_blocksize          = %d ' % c_blocksize)
+    tc.append_log(3, '   . c_nof_blocks         = %d ' % c_nof_blocks)
+    tc.append_log(3, '   . c_pagesize           = %d ' % c_pagesize)
+    tc.append_log(3, '')
+    
     # Create access object for all nodes
     io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
         
     # Create instances for the periperals
-    c_ena_pre_transpose = True
-
-    c_nof_streams   = 1
-    c_wr_chunksize  = 176
-    c_rd_chunksize  = 16
-    c_rd_nof_chunks = 11
-    c_rd_interval   = c_rd_chunksize
-    c_gapsize       = 0
-    
     bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=c_nof_streams, ramSizePerChannel=2**14)
     db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, nofStreams=c_nof_streams)
     tx_seq = pi_diag_tx_seq.PiDiagTxSeq(tc, io, nof_inst=c_nof_streams)
@@ -122,18 +139,38 @@ if __name__ == "__main__":
                    ss_list.append(i + j*c_wr_chunksize)
             ss.write_selects(ss_list)
     
-        # Init rx seq
-        step_0 = 1
-        step_1 = c_wr_chunksize                                               #   176
-        step_2 = to_unsigned(-c_wr_chunksize*(c_rd_interval-1)+1, c_word_w)   # -2639
+        # Init rx seq based on description in reorder_sequencer.vhd
+        if c_ena_pre_transpose:
+            step_0 = 1
+            step_1 = c_wr_chunksize
+            step_2 = 1               # FIXME
+            step_3 = 1               # FIXME
+        else:
+            step_0 = 1
+            # FIXME
+            #step_1 = step_0 + c_blocksize * c_rd_interval - c_rd_chunksize
+            #step_2 = step_1 - c_pagesize
+            #step_3 = 1
+            # FIXME : initially this works, but after some sync intervals it fails
+            step_1 = step_0 + c_blocksize * c_rd_chunksize - c_rd_chunksize
+            step_2 = step_0 + c_blocksize * c_rd_chunksize - c_pagesize
+            step_3 = 1
     
-        rx_seq.write_step_3(StepSize=step_2)
-        rx_seq.write_step_2(StepSize=step_2)
-        rx_seq.write_step_1(StepSize=step_1)
-        rx_seq.write_step_0(StepSize=step_0)
+        tc.append_log(3, 'Rx seq step sizes:')
+        tc.append_log(3, '   . step_0  = %d ' % step_0)
+        tc.append_log(3, '   . step_1  = %d ' % step_1)
+        tc.append_log(3, '   . step_2  = %d ' % step_2)
+        tc.append_log(3, '   . step_3  = %d ' % step_3)
+        tc.append_log(3, '')
+        
+        # use to_unsigned() to pass on negative values to MM reg
+        rx_seq.write_step_3(StepSize=to_unsigned(step_3, c_word_w))
+        rx_seq.write_step_2(StepSize=to_unsigned(step_2, c_word_w))
+        rx_seq.write_step_1(StepSize=to_unsigned(step_1, c_word_w))
+        rx_seq.write_step_0(StepSize=to_unsigned(step_0, c_word_w))
         
         # Init bg
-        bg.write_block_gen_settings(samplesPerPacket=c_wr_chunksize, blocksPerSync=16, gapSize=0, BSNInit=0)
+        bg.write_block_gen_settings(samplesPerPacket=c_wr_chunksize, blocksPerSync=c_nof_blocks, gapSize=0, BSNInit=0)
     
         ################################################################################
         # Block sequence start