From 407978a0fa48991840007003fdbd9b529915e6ab Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 23 May 2014 14:15:16 +0000
Subject: [PATCH] Support local paths or using absolute paths with environment
variables in the hdllib.cfg source files list.
---
libraries/external/easics/hdllib.cfg | 112 ++++++++++++-------------
tools/oneclick/base/modelsim_config.py | 18 ++--
2 files changed, 67 insertions(+), 63 deletions(-)
diff --git a/libraries/external/easics/hdllib.cfg b/libraries/external/easics/hdllib.cfg
index 01eb4c9ed0..07ec83130e 100644
--- a/libraries/external/easics/hdllib.cfg
+++ b/libraries/external/easics/hdllib.cfg
@@ -6,60 +6,60 @@ build_sim_dir = $HDL_BUILD_DIR
build_synth_dir =
synth_files =
- src/vhdl/PCK_CRC64_D8.vhd
- src/vhdl/PCK_CRC64_D16.vhd
- src/vhdl/PCK_CRC64_D32.vhd
- src/vhdl/PCK_CRC64_D64.vhd
- src/vhdl/PCK_CRC64_D72.vhd
- src/vhdl/PCK_CRC64_D128.vhd
- src/vhdl/PCK_CRC64_D256.vhd
- src/vhdl/PCK_CRC64_D512.vhd
- src/vhdl/PCK_CRC64_D1024.vhd
- src/vhdl/PCK_CRC32_D4.vhd
- src/vhdl/PCK_CRC32_D8.vhd
- src/vhdl/PCK_CRC32_D9.vhd
- src/vhdl/PCK_CRC32_D10.vhd
- src/vhdl/PCK_CRC32_D16.vhd
- src/vhdl/PCK_CRC32_D18.vhd
- src/vhdl/PCK_CRC32_D20.vhd
- src/vhdl/PCK_CRC32_D24.vhd
- src/vhdl/PCK_CRC32_D32.vhd
- src/vhdl/PCK_CRC32_D36.vhd
- src/vhdl/PCK_CRC32_D40.vhd
- src/vhdl/PCK_CRC32_D48.vhd
- src/vhdl/PCK_CRC32_D64.vhd
- src/vhdl/PCK_CRC32_D72.vhd
- src/vhdl/PCK_CRC32_D128.vhd
- src/vhdl/PCK_CRC32_D256.vhd
- src/vhdl/PCK_CRC32_D512.vhd
- src/vhdl/PCK_CRC32_D1024.vhd
- src/vhdl/PCK_CRC16_D4.vhd
- src/vhdl/PCK_CRC16_D8.vhd
- src/vhdl/PCK_CRC16_D9.vhd
- src/vhdl/PCK_CRC16_D10.vhd
- src/vhdl/PCK_CRC16_D16.vhd
- src/vhdl/PCK_CRC16_D18.vhd
- src/vhdl/PCK_CRC16_D20.vhd
- src/vhdl/PCK_CRC16_D24.vhd
- src/vhdl/PCK_CRC16_D32.vhd
- src/vhdl/PCK_CRC16_D36.vhd
- src/vhdl/PCK_CRC16_D48.vhd
- src/vhdl/PCK_CRC16_D64.vhd
- src/vhdl/PCK_CRC16_D72.vhd
- src/vhdl/PCK_CRC8_D4.vhd
- src/vhdl/PCK_CRC8_D8.vhd
- src/vhdl/PCK_CRC8_D9.vhd
- src/vhdl/PCK_CRC8_D10.vhd
- src/vhdl/PCK_CRC8_D16.vhd
- src/vhdl/PCK_CRC8_D18.vhd
- src/vhdl/PCK_CRC8_D20.vhd
- src/vhdl/PCK_CRC8_D24.vhd
- src/vhdl/PCK_CRC8_D32.vhd
- src/vhdl/PCK_CRC8_D36.vhd
- src/vhdl/PCK_CRC8_D48.vhd
- src/vhdl/PCK_CRC8_D64.vhd
- src/vhdl/PCK_CRC8_D72.vhd
- src/vhdl/RAD_CRC20_D20.vhd
- src/vhdl/RAD_CRC16_D16.vhd
- src/vhdl/RAD_CRC18_D18.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D8.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D16.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D32.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D64.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D72.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D128.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D256.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D512.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC64_D1024.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D4.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D8.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D9.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D10.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D16.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D18.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D20.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D24.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D32.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D36.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D40.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D48.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D64.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D72.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D128.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D256.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D512.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC32_D1024.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D4.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D8.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D9.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D10.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D16.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D18.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D20.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D24.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D32.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D36.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D48.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D64.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC16_D72.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D4.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D8.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D9.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D10.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D16.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D18.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D20.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D24.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D32.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D36.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D48.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D64.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/PCK_CRC8_D72.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/RAD_CRC20_D20.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/RAD_CRC16_D16.vhd
+ $UNB/Firmware/modules/easics/src/vhdl/RAD_CRC18_D18.vhd
test_bench_files =
diff --git a/tools/oneclick/base/modelsim_config.py b/tools/oneclick/base/modelsim_config.py
index cac9dbd7e7..db52b380eb 100644
--- a/tools/oneclick/base/modelsim_config.py
+++ b/tools/oneclick/base/modelsim_config.py
@@ -99,19 +99,23 @@ class ModelsimConfig(hdl_config.HdlConfig):
fp.write('Project_Files_Count = %d\n' % len(sim_files))
lib_path = self.libs.get_filePath(lib_dict)
for i, fn in enumerate(sim_files):
- filePathName = os.path.join(lib_path, fn)
+ fpn = os.path.expandvars(fn) # support using environment variables in the file path
+ if os.path.isabs(fpn):
+ filePathName = fpn # use absolute path to file
+ else:
+ filePathName = os.path.join(lib_path, fpn) # derive absolute path to file from library path and local path to file
fp.write('Project_File_%d = %s\n' % (i, filePathName))
project_file_p_defaults = 'vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 vlog_1995compat 0 last_compile 0 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn3 1 vlog_vopt {} cover_optlevel 3 voptflow 1 vhdl_options {} vhdl_warn4 1 toggle - ood 0 vhdl_warn5 1 cover_noshort 0 compile_to work cover_nosub 0 dont_compile 0 vhdl_use93 2002 cover_stmt 1'
project_folders = []
- if len(synth_files)>0:
+ nof_synth_files = len(synth_files)
+ if nof_synth_files>0:
project_folders.append('synth')
- for i, fn in enumerate(synth_files):
- filePathName = os.path.join(lib_path, fn)
+ for i in range(nof_synth_files):
fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (i, project_folders[-1], i, project_file_p_defaults))
- if len(test_bench_files)>0:
+ nof_test_bench_files = len(test_bench_files)
+ if nof_test_bench_files>0:
project_folders.append('test_bench')
- for j, fn in enumerate(test_bench_files):
- filePathName = os.path.join(lib_path, fn)
+ for j in range(nof_test_bench_files):
fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (i+j+1, project_folders[-1], i+j+1, project_file_p_defaults))
fp.write('Project_Folder_Count = %d\n' % len(project_folders))
for i, fd in enumerate(project_folders):
--
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