From 406ee2761ddbfb516b3073d7c5c240e037903c7f Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Mon, 23 Oct 2023 08:52:26 +0200
Subject: [PATCH] Updated information header to recent standard. Added library
ip_agi027_xxxx_mult_lib. Added generate-block inclusive the instantiation of
a module for the ip_agi027_xxxx_mult and for the ip_agi027_mult_rtl.
---
libraries/technology/mult/tech_mult.vhd | 49 ++++++++++++++++++++++++-
1 file changed, 48 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 02302d5019..30977a71ea 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright (C) 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -18,6 +18,9 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -29,6 +32,7 @@ use work.tech_mult_component_pkg.all;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library ip_stratixiv_mult_lib;
library ip_arria10_mult_lib;
+library ip_agi027_xxxx_mult_lib;
entity tech_mult is
generic (
@@ -146,6 +150,49 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_ip : if (g_technology = c_tech_agi027_xxxx and g_variant = "IP") generate
+ u0 : ip_agi027_xxxx_mult
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => prod
+ );
+ end generate;
+
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => prod
+ );
+ end generate;
+
gen_trunk : for I in 0 to g_nof_mult - 1 generate
-- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
out_p((I + 1) * g_out_p_w - 1 downto I * g_out_p_w) <= RESIZE_SVEC(prod((I + 1) * c_prod_w - 1 downto I * c_prod_w), g_out_p_w) when g_representation = "SIGNED" else
--
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