From 405b73a8d6acbe4301e00876db1891fb8bfc9bdb Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Mon, 23 Oct 2023 08:53:26 +0200
Subject: [PATCH] Replaced information header to recent standard. Added library
ip_agi027_xxxx_mult_add4_lib; Added generate-block inclusive the
instantiation of a module for the ip_agi027_xxxx_mult_add4_rtl.
---
libraries/technology/mult/tech_mult_add4.vhd | 32 +++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index bc2e5da25b..8950d20e49 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright (C) 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -18,6 +18,9 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -31,6 +34,7 @@ library ip_stratixiv_mult_lib;
library ip_arria10_e3sge3_mult_add4_lib;
library ip_arria10_e1sg_mult_add4_lib;
library ip_arria10_e2sg_mult_add4_lib;
+library ip_agi027_xxxx_mult_add4_lib;
entity tech_mult_add4 is
generic (
@@ -165,4 +169,30 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_add4_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ end generate;
+
end str;
--
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