From 3fa0aef998a1ed7f58a8a7544ed68a1e4a8e3f1f Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Fri, 1 Jun 2018 10:00:32 +0000 Subject: [PATCH] reordered PORT list for better readability --- .../tech_10gbase_r_component_pkg.vhd | 81 ++++++++++--------- 1 file changed, 42 insertions(+), 39 deletions(-) diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd index de14ea8cf5..498e0f9798 100644 --- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd +++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd @@ -800,45 +800,48 @@ PACKAGE tech_10gbase_r_component_pkg IS COMPONENT ip_arria10_e1sg_phy_10gbase_r IS PORT ( - tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset - tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset - rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset - rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset - tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy - rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy - tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk - rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk - tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data - rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data - rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref - rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata - tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk - rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk - tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk - rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk - tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data - rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data - tx_pma_div_clkout : out std_logic_vector(0 downto 0); -- tx_pma_div_clkout.clk - tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control - tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins - unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data - unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control - rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control - unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data - unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control - tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid - tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full - tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull - tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty - tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty - rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid - rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full - rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty - rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del - rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert - rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber - rx_enh_blk_lock : out std_logic_vector(0 downto 0) -- rx_enh_blk_lock.rx_enh_blk_lock - ); + rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset + rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy + rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk + rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk + rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control + rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk + rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset + rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock + rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid + rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del + rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty + rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full + rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert + rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber + rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata + rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref + rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data + rx_prbs_done : out std_logic_vector(0 downto 0); -- rx_prbs_done.rx_prbs_done + rx_prbs_err : out std_logic_vector(0 downto 0); -- rx_prbs_err.rx_prbs_err + rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr + rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data + rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken + tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset + tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy + tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk + tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control + tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk + tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset + tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid + tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty + tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full + tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty + tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull + tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins + tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data + tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk + tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data + unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control + unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data + unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control + unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data + ); END COMPONENT; COMPONENT ip_arria10_e1sg_phy_10gbase_r_4 -- GitLab