diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd index dda45ab77071c8e4385e84497e00df11e775e6f1..916bbb2a18196a555303ca81f99dc0f79b188292 100644 --- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd +++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd @@ -1,167 +1,167 @@ -------------------------------------------------------------------------------- --- --- Copyright 2022 --- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> --- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands --- --- Licensed under the Apache License, Version 2.0 (the "License"); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- --- http://www.apache.org/licenses/LICENSE-2.0 --- --- Unless required by applicable law or agreed to in writing, software --- distributed under the License is distributed on an "AS IS" BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- -------------------------------------------------------------------------------- --- Author: Job van Wee --- Purpose: Creates address by counting input valids --- --- Description: --- The counter starts on the first valid = '1' clockcylce, the counter stops --- when valid = '0'. --- --- Remark: --- Use VHDL coding template from: --- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding --- The maximum value of the address is determend by g_tech_ddr. - -LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE technology_lib.technology_pkg.ALL; -USE tech_ddr_lib.tech_ddr_pkg.ALL; -USE common_lib.common_pkg.ALL; -USE common_lib.common_mem_pkg.ALL; -USE dp_lib.dp_stream_pkg.ALL; - - -ENTITY ddrctrl_input_address_counter IS - GENERIC ( - g_tech_ddr : t_c_tech_ddr; -- type of memory - g_max_adr : NATURAL - ); - PORT ( - clk : IN STD_LOGIC; - rst : IN STD_LOGIC; - in_sosi : IN t_dp_sosi; -- input data - in_bsn_ds : IN NATURAL; - in_data_stopped : IN STD_LOGIC; - out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data - out_adr : OUT NATURAL; - out_bsn_adr : OUT NATURAL; - out_bsn_ds : OUT NATURAL; - out_data_stopped : OUT STD_LOGIC - ); -END ddrctrl_input_address_counter; - - -ARCHITECTURE rtl OF ddrctrl_input_address_counter IS - - -- constants for readability - CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576 - - -- type for statemachine - TYPE t_state IS (RESET, COUNTING, MAX, IDLE); - - -- record for readability - TYPE t_reg IS RECORD - state : t_state; - bsn_passed : STD_LOGIC; - out_sosi : t_dp_sosi; - out_bsn_adr : NATURAL; - out_bsn_ds : NATURAL; - out_data_stopped : STD_LOGIC; - s_in_sosi : t_dp_sosi; - s_in_bsn_ds : NATURAL; - s_in_data_stopped : STD_LOGIC; - s_adr : NATURAL; - END RECORD; - - CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, '0', c_dp_sosi_init, 0, '0', 0); - - - -- signals for readability - SIGNAL d_reg : t_reg := c_t_reg_init; - SIGNAL q_reg : t_reg := c_t_reg_init; - -BEGIN - - q_reg <= d_reg WHEN rising_edge(clk); - - -- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0. - p_adr : PROCESS(rst, in_sosi, in_bsn_ds, in_data_stopped, q_reg) - - VARIABLE v : t_reg; - - BEGIN - v := q_reg; - - -- compensate for delay in ddrctrl_input_address_counter - v.out_sosi := q_reg.s_in_sosi; - v.out_bsn_ds := q_reg.s_in_bsn_ds; - v.out_data_stopped := q_reg.s_in_data_stopped; - v.s_in_sosi := in_sosi; - v.s_in_bsn_ds := in_bsn_ds; - v.s_in_data_stopped := in_data_stopped; - - - CASE q_reg.state IS - WHEN RESET => - v.s_adr := 0; - - IF q_reg.s_in_sosi.sop = '1' THEN - v.out_bsn_adr := v.s_adr; - END IF; - - - WHEN COUNTING => - v.s_adr := q_reg.s_adr+1; - - IF q_reg.s_in_sosi.sop = '1' THEN - v.out_bsn_adr := v.s_adr; - END IF; - - - WHEN MAX => - v.s_adr := 0; - - IF q_reg.s_in_sosi.sop = '1' THEN - v.out_bsn_adr := v.s_adr; - END IF; - - - WHEN IDLE => - -- after a reset skip the first data block so the ddr memory can initialize. - IF NOT(q_reg.s_in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN - v.bsn_passed := '1'; - END IF; - - - END CASE; - - IF rst = '1' THEN - v.state := RESET; - ELSIF q_reg.s_adr = g_max_adr-1 AND in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN - v.state := MAX; - ELSIF in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN - v.state := COUNTING; - ELSE - v.state := IDLE; - END IF; - - d_reg <= v; - END PROCESS; - - -- fill outputs - out_sosi <= q_reg.out_sosi; - out_adr <= q_reg.s_adr; - out_bsn_adr <= q_reg.out_bsn_adr; - out_bsn_ds <= q_reg.out_bsn_ds; - out_sosi.bsn <= q_reg.out_sosi.bsn; - out_data_stopped <= q_reg.out_data_stopped; - -END rtl; +------------------------------------------------------------------------------- +-- +-- Copyright 2022 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +------------------------------------------------------------------------------- +-- Author: Job van Wee +-- Purpose: Creates address by counting input valids +-- +-- Description: +-- The counter starts on the first valid = '1' clockcylce, the counter stops +-- when valid = '0'. +-- +-- Remark: +-- Use VHDL coding template from: +-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding +-- The maximum value of the address is determend by g_tech_ddr. + +LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE technology_lib.technology_pkg.ALL; +USE tech_ddr_lib.tech_ddr_pkg.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; + + +ENTITY ddrctrl_input_address_counter IS + GENERIC ( + g_tech_ddr : t_c_tech_ddr; -- type of memory + g_max_adr : NATURAL + ); + PORT ( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + in_sosi : IN t_dp_sosi; -- input data + in_bsn_ds : IN NATURAL; + in_data_stopped : IN STD_LOGIC; + out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data + out_adr : OUT NATURAL; + out_bsn_adr : OUT NATURAL; + out_bsn_ds : OUT NATURAL; + out_data_stopped : OUT STD_LOGIC + ); +END ddrctrl_input_address_counter; + + +ARCHITECTURE rtl OF ddrctrl_input_address_counter IS + + -- constants for readability + CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576 + + -- type for statemachine + TYPE t_state IS (RESET, COUNTING, MAX, IDLE); + + -- record for readability + TYPE t_reg IS RECORD + state : t_state; + bsn_passed : STD_LOGIC; + out_sosi : t_dp_sosi; + out_bsn_adr : NATURAL; + out_bsn_ds : NATURAL; + out_data_stopped : STD_LOGIC; + s_in_sosi : t_dp_sosi; + s_in_bsn_ds : NATURAL; + s_in_data_stopped : STD_LOGIC; + s_adr : NATURAL; + END RECORD; + + CONSTANT c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, 0, '0', c_dp_sosi_init, 0, '0', 0); + + + -- signals for readability + SIGNAL d_reg : t_reg := c_t_reg_init; + SIGNAL q_reg : t_reg := c_t_reg_init; + +BEGIN + + q_reg <= d_reg WHEN rising_edge(clk); + + -- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0. + p_adr : PROCESS(rst, in_sosi, in_bsn_ds, in_data_stopped, q_reg) + + VARIABLE v : t_reg; + + BEGIN + v := q_reg; + + -- compensate for delay in ddrctrl_input_address_counter + v.out_sosi := q_reg.s_in_sosi; + v.out_bsn_ds := q_reg.s_in_bsn_ds; + v.out_data_stopped := q_reg.s_in_data_stopped; + v.s_in_sosi := in_sosi; + v.s_in_bsn_ds := in_bsn_ds; + v.s_in_data_stopped := in_data_stopped; + + + CASE q_reg.state IS + WHEN RESET => + v.s_adr := 0; + + IF q_reg.s_in_sosi.sop = '1' THEN + v.out_bsn_adr := v.s_adr; + END IF; + + + WHEN COUNTING => + v.s_adr := q_reg.s_adr+1; + + IF q_reg.s_in_sosi.sop = '1' THEN + v.out_bsn_adr := v.s_adr; + END IF; + + + WHEN MAX => + v.s_adr := 0; + + IF q_reg.s_in_sosi.sop = '1' THEN + v.out_bsn_adr := v.s_adr; + END IF; + + + WHEN IDLE => + -- after a reset skip the first data block so the ddr memory can initialize. + IF NOT(q_reg.s_in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN + v.bsn_passed := '1'; + END IF; + + + END CASE; + + IF rst = '1' THEN + v.state := RESET; + ELSIF q_reg.s_adr = g_max_adr-1 AND in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN + v.state := MAX; + ELSIF in_sosi.valid = '1' AND q_reg.bsn_passed = '1' THEN + v.state := COUNTING; + ELSE + v.state := IDLE; + END IF; + + d_reg <= v; + END PROCESS; + + -- fill outputs + out_sosi <= q_reg.out_sosi; + out_adr <= q_reg.s_adr; + out_bsn_adr <= q_reg.out_bsn_adr; + out_bsn_ds <= q_reg.out_bsn_ds; + out_sosi.bsn <= q_reg.out_sosi.bsn; + out_data_stopped <= q_reg.out_data_stopped; + +END rtl;