diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 678b55c471096d9927d0cf3818bc1d5c35c489f8..6935c8ddb5f832b8fd6e284a6c93483dd4d3f0ff 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -96,7 +96,8 @@ entity diag_block_gen is
ctrl_hold : out t_diag_block_gen; -- hold current active ctrl
en_sync : in std_logic := '1';
out_siso : in t_dp_siso := c_dp_siso_rdy;
- out_sosi : out t_dp_sosi
+ out_sosi : out t_dp_sosi;
+ out_bsn : out std_logic_vector(c_diag_bg_bsn_init_w-1 downto 0)
);
end diag_block_gen;
@@ -296,11 +297,13 @@ begin
out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w/2-1 downto 0)); -- treat as signed
out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w-1 downto g_buf_dat_w/2)); -- treat as signed
out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w-1 downto 0)); -- treat as unsigned
-
+
out_sosi <= out_sosi_i;
buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
buf_rden <= r.rd_ena;
+ out_bsn <= rin.bsn_cnt when rising_edge(clk) and rin.sop = '1';
+
ctrl_hold <= r.ctrl_hold;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
index 198c4fcddcd4c9da8f485fa79dff385c3ed17998..e5e618122bcf801d80f3a584175df6a138e91091 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
@@ -39,7 +39,8 @@ entity diag_block_gen_reg is
dp_clk : in std_logic;
mm_mosi : in t_mem_mosi; -- Memory Mapped Slave in mm_clk domain
mm_miso : out t_mem_miso := c_mem_miso_rst;
- bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst
+ bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst;
+ bg_bsn : in std_logic_vector(c_diag_bg_bsn_init_w-1 downto 0)
);
end diag_block_gen_reg;
@@ -109,9 +110,9 @@ begin
when 5 =>
mm_miso.rddata(c_diag_bg_mem_high_adrs_w -1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
when 6 =>
- mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
+ mm_miso.rddata(31 downto 0) <= bg_bsn(31 downto 0);
when 7 =>
- mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
+ mm_miso.rddata(31 downto 0) <= bg_bsn(63 downto 32);
when others => null; -- not used MM addresses
end case;
end if;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 93839197c820227c38c773b7a93429bef4e087a6..2d3d2ef172b27d33b71839639e905eb346e6bc70 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -174,7 +174,8 @@ ARCHITECTURE rtl OF mms_diag_block_gen IS
SIGNAL ram_bg_data_mosi_arr : t_mem_mosi_arr(g_nof_streams -1 DOWNTO 0);
SIGNAL ram_bg_data_miso_arr : t_mem_miso_arr(g_nof_streams -1 DOWNTO 0);
SIGNAL bg_ctrl : t_diag_block_gen;
-
+ SIGNAL bg_bsn : STD_LOGIC_VECTOR(c_diag_bg_bsn_init_w-1 downto 0);
+
SIGNAL mux_ctrl : NATURAL RANGE 0 TO c_mux_nof_input-1;
SIGNAL mux_snk_out_2arr_2 : t_dp_siso_2arr_2(g_nof_streams-1 DOWNTO 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
SIGNAL mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_streams-1 DOWNTO 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
@@ -216,7 +217,8 @@ BEGIN
dp_clk => dp_clk,
mm_mosi => reg_bg_ctrl_mosi,
mm_miso => reg_bg_ctrl_miso,
- bg_ctrl => bg_ctrl
+ bg_ctrl => bg_ctrl,
+ bg_bsn => bg_bsn
);
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
@@ -288,7 +290,8 @@ BEGIN
ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
en_sync => en_sync,
out_siso => bg_src_in_arr(I),
- out_sosi => bg_src_out_arr(I)
+ out_sosi => bg_src_out_arr(I),
+ out_bsn => bg_bsn
);
END GENERATE;
END GENERATE;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index 946c94c3b784fe8c59714861cbe9a0319d7edef2..20cc5d3d49a8c6e2ea87a9d746ea78892f1a998b 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -158,9 +158,11 @@ ARCHITECTURE tb OF tb_eth_tester IS
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL eth_corrupt : STD_LOGIC := '0';
- -- Use same bg_ctrl for all streams, this provides sufficient test coverage
+ -- Use same bg_ctrl for all others streams, this provides sufficient test coverage
SIGNAL bg_ctrl_arr : t_diag_block_gen_integer_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL bg_bsn : STD_LOGIC_VECTOR(c_diag_bg_bsn_init_w-1 downto 0);
+
SIGNAL tx_fifo_rd_emp_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
-- ETH UDP data path interface
@@ -360,6 +362,22 @@ BEGIN
END IF;
ASSERT c_bg_nof_bps_total < 10.0**9 REPORT "Tx flow control will keep ETH bitrate < 1Gbps." SEVERITY NOTE;
+ -------------------------------------------------------------------------
+ -- Manually verify: BG nof blocks and BSN
+ -------------------------------------------------------------------------
+ FOR I IN g_nof_streams-1 DOWNTO 0 LOOP
+ v_offset := I * c_diag_bg_reg_adr_span;
+
+ -- Read current BSN from BG
+ proc_mem_mm_bus_rd(v_offset + 6, mm_clk, reg_bg_ctrl_cipo, reg_bg_ctrl_copi); -- low part
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ bg_bsn(31 DOWNTO 0) <= reg_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0);
+ proc_mem_mm_bus_rd(v_offset + 7, mm_clk, reg_bg_ctrl_cipo, reg_bg_ctrl_copi); -- high part
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ bg_bsn(63 DOWNTO 32) <= reg_bg_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ END LOOP;
+
-------------------------------------------------------------------------
-- Verification: Total counts
-------------------------------------------------------------------------