diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 0517a0d49176aea7646bd7a6bd1dbb5a0464c6f5..0d4f4cd8b707069a94b88fad950c7e083f999137 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -112,24 +112,24 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL s_last_burstsize : NATURAL := c_last_burstsize;
-- signals for connecting the components
- SIGNAL ctrl_clk : STD_LOGIC;
- SIGNAL ctrl_rst : STD_LOGIC;
- SIGNAL rst_ddrctrl_input : STD_LOGIC;
- SIGNAL out_of : NATURAL := 0;
- SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
- SIGNAL out_adr : NATURAL := 0;
- SIGNAL dvr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
- SIGNAL dvr_miso : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
- SIGNAL wr_sosi : t_dp_sosi := c_dp_sosi_init;
- SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
- SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init;
- SIGNAL stop : STD_LOGIC;
- SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(c_wr_fifo_uw_w-1 DOWNTO 0);
- SIGNAL rd_fifo_usedw : STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
- SIGNAL rd_ready : STD_LOGIC;
- SIGNAL inp_bsn_adr : NATURAL;
- SIGNAL bsn_co : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
- SIGNAL data_stopped : STD_LOGIC;
+ SIGNAL ctrl_clk : STD_LOGIC;
+ SIGNAL ctrl_rst : STD_LOGIC;
+ SIGNAL rst_ddrctrl_input_ac : STD_LOGIC;
+ SIGNAL out_of : NATURAL := 0;
+ SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL out_adr : NATURAL := 0;
+ SIGNAL dvr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
+ SIGNAL dvr_miso : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
+ SIGNAL wr_sosi : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
+ SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL stop : STD_LOGIC;
+ SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(c_wr_fifo_uw_w-1 DOWNTO 0);
+ SIGNAL rd_fifo_usedw : STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
+ SIGNAL rd_ready : STD_LOGIC;
+ SIGNAL inp_bsn_adr : NATURAL;
+ SIGNAL bsn_co : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL data_stopped : STD_LOGIC;
BEGIN
@@ -149,7 +149,8 @@ BEGIN
)
PORT MAP(
clk => clk,
- rst => rst_ddrctrl_input,
+ rst => rst,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
in_sosi_arr => in_sosi_arr,
in_stop => stop,
out_sosi => out_sosi,
@@ -285,7 +286,7 @@ BEGIN
inp_adr => out_adr,
inp_bsn_adr => inp_bsn_adr,
inp_data_stopped => data_stopped,
- rst_ddrctrl_input => rst_ddrctrl_input,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
-- io_ddr
dvr_mosi => dvr_mosi,
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index edd0f6c160c3e64582a6e4c1e1241984adf7bb1f..0fb19322f7dd5ced667390318f29c79ba9e8e659 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -64,7 +64,7 @@ ENTITY ddrctrl_controller IS
inp_adr : IN NATURAL;
inp_bsn_adr : IN NATURAL;
inp_data_stopped : IN STD_LOGIC;
- rst_ddrctrl_input : OUT STD_LOGIC;
+ rst_ddrctrl_input_ac : OUT STD_LOGIC;
-- io_ddr
dvr_mosi : OUT t_mem_ctlr_mosi;
@@ -112,7 +112,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
last_adr_to_write_to : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
stop_burstsize : NATURAL;
stopped : STD_LOGIC;
- rst_ddrctrl_input : STD_LOGIC;
+ rst_ddrctrl_input_ac : STD_LOGIC;
-- writing signals
wr_burst_en : STD_LOGIC;
@@ -174,7 +174,7 @@ BEGIN
v.wr_sosi.valid := '0';
v.state := WAIT_FOR_SOP;
v.wr_burst_en := '1';
- v.rst_ddrctrl_input := '1';
+ v.rst_ddrctrl_input_ac := '1';
ELSE
v.dvr_mosi.burstbegin := '0';
END IF;
@@ -187,14 +187,14 @@ BEGIN
WHEN WAIT_FOR_SOP =>
- v.dvr_mosi.burstbegin := '0';
- v.rst_ddrctrl_input := '0';
+ v.dvr_mosi.burstbegin := '0';
+ v.rst_ddrctrl_input_ac := '0';
IF q_reg.started = '0' AND inp_sosi.eop = '1' THEN
- v.wr_sosi.valid := '1';
+ v.wr_sosi.valid := '1';
ELSIF inp_sosi.sop = '1' THEN
- v.state := WRITING;
+ v.state := WRITING;
ELSE
- v.wr_sosi.valid := '0';
+ v.wr_sosi.valid := '0';
END IF;
@@ -400,10 +400,10 @@ BEGIN
END PROCESS;
-- fill outputs
- dvr_mosi <= q_reg.dvr_mosi;
- wr_sosi <= q_reg.wr_sosi;
- stop_out <= q_reg.stopped;
- outp_bsn <= q_reg.outp_bsn;
- rst_ddrctrl_input <= q_reg.rst_ddrctrl_input OR rst;
+ dvr_mosi <= q_reg.dvr_mosi;
+ wr_sosi <= q_reg.wr_sosi;
+ stop_out <= q_reg.stopped;
+ outp_bsn <= q_reg.outp_bsn;
+ rst_ddrctrl_input_ac <= q_reg.rst_ddrctrl_input_ac OR rst;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index c27c54acd3401cc8996d26e5dcebcd664ab65fb3..ba0e21be7619d8e0f9c7e1793a1b7b90070c519d 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -53,14 +53,15 @@ ENTITY ddrctrl_input IS
g_block_size : NATURAL
);
PORT (
- clk : IN STD_LOGIC := '0';
- rst : IN STD_LOGIC;
- in_sosi_arr : IN t_dp_sosi_arr; -- input data
- in_stop : IN STD_LOGIC;
- out_sosi : OUT t_dp_sosi; -- output data
- out_adr : OUT NATURAL;
- out_bsn_adr : OUT NATURAL;
- out_data_stopped : OUT STD_LOGIC
+ clk : IN STD_LOGIC := '0';
+ rst : IN STD_LOGIC;
+ rst_ddrctrl_input_ac : IN STD_LOGIC;
+ in_sosi_arr : IN t_dp_sosi_arr; -- input data
+ in_stop : IN STD_LOGIC;
+ out_sosi : OUT t_dp_sosi; -- output data
+ out_adr : OUT NATURAL;
+ out_bsn_adr : OUT NATURAL;
+ out_data_stopped : OUT STD_LOGIC
);
END ddrctrl_input;
@@ -119,7 +120,7 @@ BEGIN
)
PORT MAP(
clk => clk,
- rst => rst,
+ rst => rst_ddrctrl_input_ac,
in_sosi => sosi_rp_ac, -- input data
in_data_stopped => data_stopped_rp_ac,
out_sosi => out_sosi, -- output data
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index a385fc82c94e6ff7d84ff7c1446bf4b23912d55e..b359172bc8bc7d4abffca6faae8d239382d0d53b 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -159,7 +159,7 @@ BEGIN
WHEN RESET =>
v := c_t_reg_init;
- v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
+ v.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
WHEN STOP =>