diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 483d9968983f1978dfc20c426639d7d875cac575..9b14e97efc2f9d4dbc89acfaffd871718961bed8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -214,14 +214,10 @@ peripherals:
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
- - peripheral_name: dp/dp_bsn_scheduler
+ - peripheral_name: dp/dp_bsn_sync_scheduler
peripheral_group: xsub
mm_port_names:
- - REG_BSN_SCHEDULER_XSUB
-
- - peripheral_name: dp/dp_sync_insert_v2
- mm_port_names:
- - REG_DP_SYNC_INSERT_V2
+ - REG_BSN_SYNC_SCHEDULER_XSUB
- peripheral_name: st/st_xst_for_sdp
parameter_overrides:
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index c106dec2035631034d3a53d837eee2ac874e7c52..a9f9b9204a04442abeda25122a0280faeaf6a79e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB40C0' end='0xB4100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4140' end='0xB4160' datawidth='32' /><slave name='reg_remu.mem' start='0xB4160' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4180' end='0xB4190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4190' end='0xB41A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB41A0' end='0xB41B0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41B0' end='0xB41C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41E0' end='0xB41E8' datawidth='32' /><slave name='reg_si.mem' start='0xB41E8' end='0xB41F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41F0' end='0xB41F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41F8' end='0xB4200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB4200' end='0xB4208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB4208' end='0xB4210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB4210' end='0xB4218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB40C0' end='0xB4100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4140' end='0xB4160' datawidth='32' /><slave name='reg_remu.mem' start='0xB4160' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4180' end='0xB4190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4190' end='0xB41A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB41A0' end='0xB41B0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41B0' end='0xB41C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41E0' end='0xB41E8' datawidth='32' /><slave name='reg_si.mem' start='0xB41E8' end='0xB41F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41F0' end='0xB41F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41F8' end='0xB4200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB4200' end='0xB4208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB4208' end='0xB4210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB4210' end='0xB4218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
similarity index 96%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
index e41248d531721555270335dfb2bf93e7bbd6817e..0980bf5700a86bc8295e098702dd601769575e0f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,6 +605,10 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -697,6 +701,10 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -766,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -775,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -838,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -902,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -971,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1366,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1398,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
deleted file mode 100644
index a523d8af9523229c23c36c2005b7d4231b7e137d..0000000000000000000000000000000000000000
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
+++ /dev/null
@@ -1,1439 +0,0 @@
-<?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>address</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_address_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_clk_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>mem</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>address</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_address</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>write</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_write</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>writedata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_writedata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>read</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_read</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>readdata</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>avs_mem_readdata</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>addressAlignment</spirit:name>
- <spirit:displayName>Slave addressing</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressGroup</spirit:name>
- <spirit:displayName>Address group</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressSpan</spirit:name>
- <spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>addressUnits</spirit:name>
- <spirit:displayName>Address units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>alwaysBurstMaxBurst</spirit:name>
- <spirit:displayName>Always burst maximum burst</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>Associated reset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bitsPerSymbol</spirit:name>
- <spirit:displayName>Bits per symbol</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgedAddressOffset</spirit:name>
- <spirit:displayName>Bridged Address Offset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bridgesToMaster</spirit:name>
- <spirit:displayName>Bridges to master</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
- <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>burstcountUnits</spirit:name>
- <spirit:displayName>Burstcount units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>constantBurstBehavior</spirit:name>
- <spirit:displayName>Constant burst behavior</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>explicitAddressSpan</spirit:name>
- <spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>holdTime</spirit:name>
- <spirit:displayName>Hold</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>interleaveBursts</spirit:name>
- <spirit:displayName>Interleave bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isBigEndian</spirit:name>
- <spirit:displayName>Big endian</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isFlash</spirit:name>
- <spirit:displayName>Flash memory</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isMemoryDevice</spirit:name>
- <spirit:displayName>Memory device</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>isNonVolatileStorage</spirit:name>
- <spirit:displayName>Non-volatile storage</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>linewrapBursts</spirit:name>
- <spirit:displayName>Linewrap bursts</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingReadTransactions</spirit:name>
- <spirit:displayName>Maximum pending read transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>maximumPendingWriteTransactions</spirit:name>
- <spirit:displayName>Maximum pending write transactions</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumReadLatency</spirit:name>
- <spirit:displayName>minimumReadLatency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumResponseLatency</spirit:name>
- <spirit:displayName>Minimum response latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>minimumUninterruptedRunLength</spirit:name>
- <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>printableDevice</spirit:name>
- <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readLatency</spirit:name>
- <spirit:displayName>Read latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitStates</spirit:name>
- <spirit:displayName>Read wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>readWaitTime</spirit:name>
- <spirit:displayName>Read wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerIncomingSignals</spirit:name>
- <spirit:displayName>Register incoming signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>registerOutgoingSignals</spirit:name>
- <spirit:displayName>Register outgoing signals</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>setupTime</spirit:name>
- <spirit:displayName>Setup</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>timingUnits</spirit:name>
- <spirit:displayName>Timing units</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>transparentBridge</spirit:name>
- <spirit:displayName>Transparent bridge</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>waitrequestAllowance</spirit:name>
- <spirit:displayName>Waitrequest allowance</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>wellBehavedWaitrequest</spirit:name>
- <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeLatency</spirit:name>
- <spirit:displayName>Write latency</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitStates</spirit:name>
- <spirit:displayName>Write wait states</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>writeWaitTime</spirit:name>
- <spirit:displayName>Write wait</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>read</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_read_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>readdata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_readdata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_reset_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>clockRate</spirit:name>
- <spirit:displayName>Clock rate</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>externallyDriven</spirit:name>
- <spirit:displayName>Externally driven</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>ptfSchematicName</spirit:name>
- <spirit:displayName>PTF schematic name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>system_reset</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>csi_system_reset</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>Associated clock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>synchronousEdges</spirit:name>
- <spirit:displayName>Synchronous edges</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>write</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_write_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>writedata</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>export</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>coe_writedata_export</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>QUARTUS_SYNTH</spirit:name>
- <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>avs_common_mm</spirit:modelName>
- <spirit:fileSetRef>
- <spirit:localName>QUARTUS_SYNTH</spirit:localName>
- </spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>csi_system_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>csi_system_reset</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_write</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_writedata</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_read</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>avs_mem_readdata</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_reset_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_clk_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_address_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_write_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_writedata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_read_export</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>coe_readdata_export</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>31</spirit:right>
- </spirit:vector>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
- <spirit:vendorExtensions>
- <altera:entity_info>
- <spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:library>
- <spirit:name>avs_common_mm</spirit:name>
- <spirit:version>1.0</spirit:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>g_adr_w</spirit:name>
- <spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>g_dat_w</spirit:name>
- <spirit:displayName>g_dat_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
- <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>device</spirit:name>
- <spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceFamily</spirit:name>
- <spirit:displayName>Device family</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>deviceSpeedGrade</spirit:name>
- <spirit:displayName>Device Speed Grade</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>generationId</spirit:name>
- <spirit:displayName>Generation Id</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>bonusData</spirit:name>
- <spirit:displayName>bonusData</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
-{
-}
-</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>hideFromIPCatalog</spirit:name>
- <spirit:displayName>Hide from IP Catalog</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>lockedInterfaceDefinition</spirit:name>
- <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>systemInfos</spirit:name>
- <spirit:displayName>systemInfos</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>3</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index d6f321e7ef38e0d597aceea0693177e2c39b7e8e..3b0fdadb35dc31974e8a9435d792bae7625e2903 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "737280";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "737760";
+ value = "737808";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "737688";
+ value = "737736";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "737648";
+ value = "737712";
type = "String";
}
}
@@ -338,7 +338,7 @@
{
datum _sortIndex
{
- value = "54";
+ value = "52";
type = "int";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "737632";
+ value = "737696";
type = "String";
}
}
@@ -426,39 +426,39 @@
{
datum baseAddress
{
- value = "737712";
+ value = "737760";
type = "String";
}
}
- element reg_bsn_scheduler_xsub
+ element reg_bsn_source_v2
{
datum _sortIndex
{
- value = "53";
+ value = "24";
type = "int";
}
}
- element reg_bsn_scheduler_xsub.mem
+ element reg_bsn_source_v2.mem
{
datum baseAddress
{
- value = "737664";
+ value = "737536";
type = "String";
}
}
- element reg_bsn_source_v2
+ element reg_bsn_sync_scheduler_xsub
{
datum _sortIndex
{
- value = "24";
+ value = "55";
type = "int";
}
}
- element reg_bsn_source_v2.mem
+ element reg_bsn_sync_scheduler_xsub.mem
{
datum baseAddress
{
- value = "737472";
+ value = "12352";
type = "String";
}
}
@@ -466,7 +466,7 @@
{
datum _sortIndex
{
- value = "52";
+ value = "51";
type = "int";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "737280";
+ value = "737344";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "737704";
+ value = "737752";
type = "String";
}
}
@@ -526,22 +526,6 @@
type = "String";
}
}
- element reg_dp_sync_insert_v2
- {
- datum _sortIndex
- {
- value = "51";
- type = "int";
- }
- }
- element reg_dp_sync_insert_v2.mem
- {
- datum baseAddress
- {
- value = "737672";
- type = "String";
- }
- }
element reg_dp_xonoff
{
datum _sortIndex
@@ -554,7 +538,7 @@
{
datum baseAddress
{
- value = "737616";
+ value = "737680";
type = "String";
}
}
@@ -575,7 +559,7 @@
{
datum baseAddress
{
- value = "737752";
+ value = "737800";
type = "String";
}
}
@@ -596,7 +580,7 @@
{
datum baseAddress
{
- value = "737744";
+ value = "737792";
type = "String";
}
}
@@ -617,7 +601,7 @@
{
datum baseAddress
{
- value = "737536";
+ value = "737600";
type = "String";
}
}
@@ -633,7 +617,7 @@
{
datum baseAddress
{
- value = "737504";
+ value = "737568";
type = "String";
}
}
@@ -654,7 +638,7 @@
{
datum baseAddress
{
- value = "737408";
+ value = "737472";
type = "String";
}
}
@@ -691,7 +675,7 @@
{
datum baseAddress
{
- value = "737736";
+ value = "737784";
type = "String";
}
}
@@ -712,7 +696,7 @@
{
datum baseAddress
{
- value = "737728";
+ value = "737776";
type = "String";
}
}
@@ -728,7 +712,7 @@
{
datum baseAddress
{
- value = "737696";
+ value = "737744";
type = "String";
}
}
@@ -765,7 +749,7 @@
{
datum baseAddress
{
- value = "737568";
+ value = "737632";
type = "String";
}
}
@@ -781,7 +765,7 @@
{
datum baseAddress
{
- value = "737344";
+ value = "737408";
type = "String";
}
}
@@ -797,7 +781,7 @@
{
datum baseAddress
{
- value = "737720";
+ value = "737768";
type = "String";
}
}
@@ -813,7 +797,7 @@
{
datum baseAddress
{
- value = "737600";
+ value = "737664";
type = "String";
}
}
@@ -829,7 +813,7 @@
{
datum baseAddress
{
- value = "737680";
+ value = "737728";
type = "String";
}
}
@@ -837,7 +821,7 @@
{
datum _sortIndex
{
- value = "55";
+ value = "53";
type = "int";
}
}
@@ -885,7 +869,7 @@
{
datum _sortIndex
{
- value = "56";
+ value = "54";
type = "int";
}
}
@@ -1766,73 +1750,73 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_address"
- internal="reg_bsn_scheduler_xsub.address"
+ name="reg_bsn_source_v2_address"
+ internal="reg_bsn_source_v2.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_clk"
- internal="reg_bsn_scheduler_xsub.clk"
+ name="reg_bsn_source_v2_clk"
+ internal="reg_bsn_source_v2.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_read"
- internal="reg_bsn_scheduler_xsub.read"
+ name="reg_bsn_source_v2_read"
+ internal="reg_bsn_source_v2.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_readdata"
- internal="reg_bsn_scheduler_xsub.readdata"
+ name="reg_bsn_source_v2_readdata"
+ internal="reg_bsn_source_v2.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_reset"
- internal="reg_bsn_scheduler_xsub.reset"
+ name="reg_bsn_source_v2_reset"
+ internal="reg_bsn_source_v2.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_write"
- internal="reg_bsn_scheduler_xsub.write"
+ name="reg_bsn_source_v2_write"
+ internal="reg_bsn_source_v2.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_scheduler_xsub_writedata"
- internal="reg_bsn_scheduler_xsub.writedata"
+ name="reg_bsn_source_v2_writedata"
+ internal="reg_bsn_source_v2.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_address"
- internal="reg_bsn_source_v2.address"
+ name="reg_bsn_sync_scheduler_xsub_address"
+ internal="reg_bsn_sync_scheduler_xsub.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_clk"
- internal="reg_bsn_source_v2.clk"
+ name="reg_bsn_sync_scheduler_xsub_clk"
+ internal="reg_bsn_sync_scheduler_xsub.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_read"
- internal="reg_bsn_source_v2.read"
+ name="reg_bsn_sync_scheduler_xsub_read"
+ internal="reg_bsn_sync_scheduler_xsub.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_readdata"
- internal="reg_bsn_source_v2.readdata"
+ name="reg_bsn_sync_scheduler_xsub_readdata"
+ internal="reg_bsn_sync_scheduler_xsub.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_reset"
- internal="reg_bsn_source_v2.reset"
+ name="reg_bsn_sync_scheduler_xsub_reset"
+ internal="reg_bsn_sync_scheduler_xsub.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_write"
- internal="reg_bsn_source_v2.write"
+ name="reg_bsn_sync_scheduler_xsub_write"
+ internal="reg_bsn_sync_scheduler_xsub.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_v2_writedata"
- internal="reg_bsn_source_v2.writedata"
+ name="reg_bsn_sync_scheduler_xsub_writedata"
+ internal="reg_bsn_sync_scheduler_xsub.writedata"
type="conduit"
dir="end" />
<interface
@@ -1975,41 +1959,6 @@
internal="reg_dp_shiftram.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_address"
- internal="reg_dp_sync_insert_v2.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_clk"
- internal="reg_dp_sync_insert_v2.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_read"
- internal="reg_dp_sync_insert_v2.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_readdata"
- internal="reg_dp_sync_insert_v2.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_reset"
- internal="reg_dp_sync_insert_v2.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_write"
- internal="reg_dp_sync_insert_v2.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_dp_sync_insert_v2_writedata"
- internal="reg_dp_sync_insert_v2.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_dp_xonoff_address"
internal="reg_dp_xonoff.address"
@@ -5805,7 +5754,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='pio_pps.mem' start='0xB4170' end='0xB4180' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_si.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41E0' end='0xB41E8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB40C0' end='0xB4100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4140' end='0xB4160' datawidth='32' /><slave name='reg_remu.mem' start='0xB4160' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4180' end='0xB4190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4190' end='0xB41A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB41A0' end='0xB41B0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41B0' end='0xB41C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41E0' end='0xB41E8' datawidth='32' /><slave name='reg_si.mem' start='0xB41E8' end='0xB41F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41F0' end='0xB41F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41F8' end='0xB4200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB4200' end='0xB4208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB4208' end='0xB4210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB4210' end='0xB4218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -10878,653 +10827,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="ram_diag_data_buffer_bsn"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>21</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>21</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8388608</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800000' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>23</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_equalizer_gains"
+ name="ram_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11540,7 +10873,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11604,7 +10937,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>21</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11673,7 +11006,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8388608</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12079,11 +11412,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>23</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12110,37 +11443,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_fil_coefs"
+ name="ram_equalizer_gains"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12156,7 +11489,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12220,7 +11553,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12289,7 +11622,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12695,11 +12028,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12726,37 +12059,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_scrap"
+ name="ram_fil_coefs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12772,7 +12105,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12836,7 +12169,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12905,7 +12238,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13311,11 +12644,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13342,37 +12675,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_ss_ss_wide"
+ name="ram_scrap"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13388,7 +12721,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13452,7 +12785,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13521,7 +12854,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13927,11 +13260,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13958,37 +13291,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_bst"
+ name="ram_ss_ss_wide"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14004,7 +13337,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14068,7 +13401,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14137,7 +13470,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14543,11 +13876,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14574,37 +13907,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="ram_st_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14620,7 +13953,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14684,7 +14017,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>12</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14753,7 +14086,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>16384</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15159,11 +14492,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>14</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15190,37 +14523,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_xsq"
+ name="ram_st_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15806,37 +15139,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="ram_st_xsq"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16422,37 +15755,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16468,7 +15801,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16532,7 +15865,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16601,7 +15934,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17007,11 +16340,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17038,37 +16371,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17084,7 +16417,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17148,7 +16481,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17217,7 +16550,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17623,11 +16956,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17654,37 +16987,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17700,7 +17033,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17764,7 +17097,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17833,7 +17166,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18239,11 +17572,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18270,37 +17603,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18316,7 +17649,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18380,7 +17713,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18449,7 +17782,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18855,11 +18188,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18886,37 +18219,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler_xsub"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19502,30 +18835,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -20148,7 +19481,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_bsn_sync_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20734,37 +20067,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20780,7 +20113,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20844,7 +20177,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20913,7 +20246,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21319,11 +20652,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21350,37 +20683,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21396,7 +20729,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21460,7 +20793,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21529,7 +20862,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21935,11 +21268,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21966,37 +21299,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22012,7 +21345,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22076,7 +21409,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22145,7 +21478,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22551,11 +21884,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22582,37 +21915,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_sync_insert_v2"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22628,7 +21961,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22692,7 +22025,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22761,7 +22094,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23167,11 +22500,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23198,30 +22531,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -39356,7 +38689,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000b41e0" />
+ <parameter name="baseAddress" value="0x000b4210" />
</connection>
<connection
kind="avalon"
@@ -39391,7 +38724,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000b4170" />
+ <parameter name="baseAddress" value="0x000b41b0" />
</connection>
<connection
kind="avalon"
@@ -39405,49 +38738,49 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x000b4120" />
+ <parameter name="baseAddress" value="0x000b4160" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x000b4100" />
+ <parameter name="baseAddress" value="0x000b4140" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000b41d8" />
+ <parameter name="baseAddress" value="0x000b4208" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000b41d0" />
+ <parameter name="baseAddress" value="0x000b4200" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000b41c8" />
+ <parameter name="baseAddress" value="0x000b41f8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000b41c0" />
+ <parameter name="baseAddress" value="0x000b41f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x000b40e0" />
+ <parameter name="baseAddress" value="0x000b4120" />
</connection>
<connection
kind="avalon"
@@ -39461,7 +38794,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x000b4080" />
+ <parameter name="baseAddress" value="0x000b40c0" />
</connection>
<connection
kind="avalon"
@@ -39475,7 +38808,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000b41b8" />
+ <parameter name="baseAddress" value="0x000b41e8" />
</connection>
<connection
kind="avalon"
@@ -39517,14 +38850,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000b41b0" />
+ <parameter name="baseAddress" value="0x000b41e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x000b40c0" />
+ <parameter name="baseAddress" value="0x000b4100" />
</connection>
<connection
kind="avalon"
@@ -39552,7 +38885,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000b41a8" />
+ <parameter name="baseAddress" value="0x000b41d8" />
</connection>
<connection
kind="avalon"
@@ -39580,7 +38913,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x000b4160" />
+ <parameter name="baseAddress" value="0x000b41a0" />
</connection>
<connection
kind="avalon"
@@ -39594,7 +38927,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x000b4150" />
+ <parameter name="baseAddress" value="0x000b4190" />
</connection>
<connection
kind="avalon"
@@ -39608,14 +38941,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x000b4040" />
+ <parameter name="baseAddress" value="0x000b4080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000b41a0" />
+ <parameter name="baseAddress" value="0x000b41d0" />
</connection>
<connection
kind="avalon"
@@ -39643,14 +38976,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000b4198" />
+ <parameter name="baseAddress" value="0x000b41c8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000b4190" />
+ <parameter name="baseAddress" value="0x000b41c0" />
</connection>
<connection
kind="avalon"
@@ -39664,7 +38997,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x000b4140" />
+ <parameter name="baseAddress" value="0x000b4180" />
</connection>
<connection
kind="avalon"
@@ -39673,26 +39006,12 @@
end="reg_stat_hdr_dat_bst.mem">
<parameter name="baseAddress" value="0x0200" />
</connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_dp_sync_insert_v2.mem">
- <parameter name="baseAddress" value="0x000b4188" />
- </connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x000b4000" />
- </connection>
- <connection
- kind="avalon"
- version="18.0"
- start="cpu_0.data_master"
- end="reg_bsn_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x000b4180" />
+ <parameter name="baseAddress" value="0x000b4040" />
</connection>
<connection
kind="avalon"
@@ -39715,6 +39034,13 @@
end="reg_stat_hdr_dat_xst.mem">
<parameter name="baseAddress" value="0x0100" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_sync_scheduler_xsub.mem">
+ <parameter name="baseAddress" value="0x3040" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -39727,7 +39053,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x000b4000" />
</connection>
<connection
kind="avalon"
@@ -39957,32 +39283,27 @@
version="18.0"
start="clk_0.clk"
end="reg_stat_hdr_dat_bst.system" />
- <connection
- kind="clock"
- version="18.0"
- start="clk_0.clk"
- end="reg_dp_sync_insert_v2.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
end="reg_crosslets_info.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_st_xsq.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_bsn_scheduler_xsub.system" />
- <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_st_xsq.system" />
+ end="reg_stat_enable_xst.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_enable_xst.system" />
+ end="reg_stat_hdr_dat_xst.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_hdr_dat_xst.system" />
+ end="reg_bsn_sync_scheduler_xsub.system" />
<connection
kind="interrupt"
version="18.0"
@@ -40244,11 +39565,6 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_stat_hdr_dat_bst.system_reset" />
- <connection
- kind="reset"
- version="18.0"
- start="clk_0.clk_reset"
- end="reg_dp_sync_insert_v2.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -40258,22 +39574,22 @@
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_bsn_scheduler_xsub.system_reset" />
+ end="ram_st_xsq.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="ram_st_xsq.system_reset" />
+ end="reg_stat_enable_xst.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_enable_xst.system_reset" />
+ end="reg_stat_hdr_dat_xst.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_hdr_dat_xst.system_reset" />
+ end="reg_bsn_sync_scheduler_xsub.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 405d49e9badd42bf2729bb8c3dc0dbd827c7ff9e..221a18c9fa1123fd006e781a3c175661eaa6c77f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -66,7 +66,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -74,7 +74,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 30a3e73e3ff354cc93a870658dbc35883a503d5d..9a5cfb073c03c44841fcfc2bcd1a5b37b95e28ea 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -74,7 +74,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -82,7 +82,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index 95e95a5df0cdd580a9596813c5dc43147b572de1..2e9b7490409b4ffe75da4c4c07654ee3a3317e8f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -73,7 +73,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -81,7 +81,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index ef1bd83f987c514f911651c6752052c0fb215fe6..11ba0e50633755c40968d46b363c344c6cb45749 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -89,7 +89,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
-- WG
CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/1; -- in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
index 55e0af625cc4394681a6002faa68592fc2d60209..db33170b4fe7ab81d610a984a840dfdb135ee6a0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -70,7 +70,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -78,7 +78,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index c15743f6c693c88222d3f2db2d8659e9ab9c2653..1185fdc46bd686aa632a55b797a551836acc0112 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -73,7 +73,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
@@ -81,7 +81,6 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index a8e0635b63a96c82458a3f1efcd46c679643a3af..cef00a959f44a6bb15c1c6d5fc8c70edbc325092 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -81,7 +81,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
-
+ CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync;
+
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
@@ -111,7 +112,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
- CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
+ CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
-- Tb
@@ -285,8 +286,10 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-- bsn_scheduler_xsub
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- enable
-- Wait for enough WG data and start of sync interval
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index a3a44d2dc0893d3abfd2d7b6f3c4b426ca1fb190..723dd616251ae04fe207abe9e7c7e0e32723f92c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -74,11 +74,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+ CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync;
-- MM
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
- CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
+ CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
@@ -218,9 +219,10 @@ BEGIN
----------------------------------------------------------------------------
-- Enable xsub
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- first write low then high part
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 2, 1, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- enable
----------------------------------------------------------------------------
-- Offload enable
----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 36bda1b4a0f7ccb59831c8fee5b23f0573f6d8d4..537221081a4f60aff65bfd85c1363dd4c44e1613 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -274,17 +274,13 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
----------------------------------------------
-- XSUB
----------------------------------------------
- -- dp_sync_insert_v2
- SIGNAL reg_dp_sync_insert_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_sync_insert_v2_miso : t_mem_miso := c_mem_miso_rst;
-
-- crosslets_info
SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
- SIGNAL reg_bsn_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
-- st_xsq
SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -640,12 +636,10 @@ BEGIN
reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso
);
@@ -739,12 +733,10 @@ BEGIN
reg_sdp_info_miso => reg_sdp_info_miso,
-- XSUB
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index e0ec6e62de04ecc0ccf238b673762acbd6f07454..4d630d837dc215e44b3c217eb7c8d6baa74a73e5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -206,17 +206,13 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
- -- dp_sync_insert_v2
- reg_dp_sync_insert_v2_mosi : OUT t_mem_mosi;
- reg_dp_sync_insert_v2_miso : IN t_mem_miso;
-
-- crosslets_info
reg_crosslets_info_mosi : OUT t_mem_mosi;
reg_crosslets_info_miso : IN t_mem_miso;
- -- bsn_scheduler_xsub
- reg_bsn_scheduler_xsub_mosi : OUT t_mem_mosi;
- reg_bsn_scheduler_xsub_miso : IN t_mem_miso;
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
+ reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
-- st_xsq (XST)
ram_st_xsq_mosi : OUT t_mem_mosi;
@@ -365,14 +361,11 @@ BEGIN
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
- u_mm_file_reg_dp_sync_insert_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SYNC_INSERT_V2")
- PORT MAP(mm_rst, mm_clk, reg_dp_sync_insert_v2_mosi, reg_dp_sync_insert_v2_miso);
-
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
- u_mm_file_reg_bsn_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_xsub_mosi, reg_bsn_scheduler_xsub_miso);
+ u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
@@ -775,14 +768,6 @@ BEGIN
reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_clk_export => OPEN,
- reg_dp_sync_insert_v2_reset_export => OPEN,
- reg_dp_sync_insert_v2_address_export => reg_dp_sync_insert_v2_mosi.address(c_sdp_reg_dp_sync_insert_v2_addr_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_write_export => reg_dp_sync_insert_v2_mosi.wr,
- reg_dp_sync_insert_v2_writedata_export => reg_dp_sync_insert_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_sync_insert_v2_read_export => reg_dp_sync_insert_v2_mosi.rd,
- reg_dp_sync_insert_v2_readdata_export => reg_dp_sync_insert_v2_miso.rddata(c_word_w-1 DOWNTO 0),
-
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
@@ -791,13 +776,13 @@ BEGIN
reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_clk_export => OPEN,
- reg_bsn_scheduler_xsub_reset_export => OPEN,
- reg_bsn_scheduler_xsub_address_export => reg_bsn_scheduler_xsub_mosi.address(c_sdp_reg_bsn_scheduler_xsub_addr_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_write_export => reg_bsn_scheduler_xsub_mosi.wr,
- reg_bsn_scheduler_xsub_writedata_export => reg_bsn_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_xsub_read_export => reg_bsn_scheduler_xsub_mosi.rd,
- reg_bsn_scheduler_xsub_readdata_export => reg_bsn_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 181b0649ce2ec4ba52ea38891fdbb873192a6a20..6bc6268484537c132de481cd2dd4ad4fc5c66db8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -329,13 +329,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_sync_insert_v2_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_sync_insert_v2_clk_export : out std_logic; -- export
- reg_dp_sync_insert_v2_read_export : out std_logic; -- export
- reg_dp_sync_insert_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_sync_insert_v2_reset_export : out std_logic; -- export
- reg_dp_sync_insert_v2_write_export : out std_logic; -- export
- reg_dp_sync_insert_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
reg_crosslets_info_clk_export : out std_logic; -- export
reg_crosslets_info_read_export : out std_logic; -- export
@@ -343,13 +336,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_crosslets_info_reset_export : out std_logic; -- export
reg_crosslets_info_write_export : out std_logic; -- export
reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_xsub_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_st_xsq_address_export : out std_logic_vector(13 downto 0); -- export
ram_st_xsq_clk_export : out std_logic; -- export
ram_st_xsq_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 191577e824056e530783ed46a88fcb65a9133d2b..4e578e7da26853edc548e0ea26fa1247d5e1d7dc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -54,18 +54,16 @@ ENTITY node_sdp_correlator IS
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
- reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_sync_insert_v2_miso : OUT t_mem_miso;
- reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso;
- reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso;
- reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_enable_miso : OUT t_mem_miso;
- reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_hdr_dat_miso : OUT t_mem_miso;
+ reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso;
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso;
+ reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_miso : OUT t_mem_miso;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -77,9 +75,6 @@ END node_sdp_correlator;
ARCHITECTURE str OF node_sdp_correlator IS
- CONSTANT c_nof_blk_per_sync_max : NATURAL := c_sdp_xst_nof_blk_per_sync_max;
- CONSTANT c_nof_blk_per_sync_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min;
-
CONSTANT c_nof_masters : POSITIVE := 2;
-- crosslet statistics offload
@@ -91,14 +86,14 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
- SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_bsn_sync_scheduler_src_out : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
- SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
+ SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
-- Requantize 18b to 16b
@@ -125,28 +120,6 @@ BEGIN
);
END GENERATE;
- ---------------------------------------------------------------
- -- dp_sync_insert_v2
- ---------------------------------------------------------------
- u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
- GENERIC MAP (
- g_nof_streams => c_sdp_P_pfb,
- g_nof_blk_per_sync => c_nof_blk_per_sync_max,
- g_nof_blk_per_sync_min => c_nof_blk_per_sync_min
- )
- PORT MAP (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_sync_insert_v2_mosi,
- reg_miso => reg_dp_sync_insert_v2_miso,
-
- in_sosi_arr => quant_sosi_arr,
- out_sosi_arr => xin_sosi_arr
- );
-
---------------------------------------------------------------
-- Crosslet Subband Select
---------------------------------------------------------------
@@ -158,7 +131,7 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- in_sosi_arr => xin_sosi_arr,
+ in_sosi_arr => quant_sosi_arr,
out_sosi => xsel_sosi,
mm_rst => mm_rst,
@@ -166,10 +139,10 @@ BEGIN
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
-
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
+
out_crosslets_info => crosslets_info
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 826d47e29b25e8ac3b2f7f6e336999536647d7de..ef1f8c9fa55915372aa0a96300df36465b723b18 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -41,7 +41,8 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_crosslets_subband_select IS
GENERIC (
- g_N_crosslets : NATURAL := c_sdp_N_crosslets
+ g_N_crosslets : NATURAL := c_sdp_N_crosslets;
+ g_ctrl_interval_size_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min
);
PORT (
dp_clk : IN STD_LOGIC;
@@ -56,8 +57,8 @@ ENTITY sdp_crosslets_subband_select IS
reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
- reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
@@ -96,6 +97,7 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
SIGNAL col_select_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL row_select_slv : STD_LOGIC_VECTOR(c_row_select_slv_w-1 DOWNTO 0);
+ SIGNAL dp_bsn_sync_scheduler_src_out_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL col_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL row_sosi : t_dp_sosi;
@@ -104,27 +106,27 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
BEGIN
---------------------------------------------------------------
- -- BSN scheduler
+ -- BSN sync scheduler
---------------------------------------------------------------
- u_bsn_scheduler : ENTITY dp_lib.mms_dp_bsn_scheduler
+ u_mmp_dp_bsn_sync_scheduler_arr : ENTITY dp_lib.mmp_dp_bsn_sync_scheduler_arr
GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_bsn_w => c_dp_stream_bsn_w
+ g_nof_streams => c_sdp_P_pfb,
+ g_block_size => c_sdp_N_fft,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
)
PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_miso => reg_bsn_scheduler_xsub_miso,
+ reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_miso => reg_bsn_sync_scheduler_xsub_miso,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
- snk_in => in_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => start_trigger
+ out_start => start_trigger
);
---------------------------------------------------------------
@@ -161,7 +163,7 @@ BEGIN
END IF;
END PROCESS;
- p_comb_crosslets_control : PROCESS(r, start_trigger, crosslets_info_reg, in_sosi_arr, col_select_miso)
+ p_comb_crosslets_control : PROCESS(r, start_trigger, crosslets_info_reg, dp_bsn_sync_scheduler_src_out_arr, col_select_miso)
VARIABLE v : t_crosslets_control_reg;
-- Use extra variable to simplify col_select_mosi address selection.
-- Also using v_offsets instead of v.offsets to clearly indicate we do not only use this variable on the left side but also on the right side of assignments.
@@ -178,7 +180,8 @@ BEGIN
v.row_index := 0;
v.col_index := 0;
v.sync_detected := '0'; -- set sync_detected to 0 in the case that a sync has been detected before the initial start_trigger.
- -- start_trigger is active on the eop so we can immediatly reset the offsets/step such that they are used in the next packet.
+
+ -- start_trigger is active on the sync so we can immediatly reset the offsets/step such that they are used in the next packet.
-- It is up to the user to schedule the start trigger on a BSN that coincides with a sync interval if that is desired.
v.step := TO_UINT(crosslets_info_reg(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w));
FOR I IN 0 TO g_N_crosslets-1 LOOP
@@ -186,21 +189,18 @@ BEGIN
END LOOP;
END IF;
- IF in_sosi_arr(0).sync = '1' THEN
+ -- Do not set sync_detected if start_trigger = 1 because the first sync interval after (re)start
+ -- already has set the indices for the first interval and we do not want to increase them with the step.
+ IF dp_bsn_sync_scheduler_src_out_arr(0).sync = '1' AND start_trigger = '0' THEN
v.sync_detected := '1';
END IF;
IF r.started = '1' THEN -- Once started r.started remains active.
-- add step to offsets
- IF in_sosi_arr(0).eop = '1' AND r.sync_detected = '1' THEN -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select
+ IF dp_bsn_sync_scheduler_src_out_arr(0).eop = '1' AND r.sync_detected = '1' THEN -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select
v.sync_detected := '0';
FOR I IN 0 TO g_N_crosslets-1 LOOP
- IF start_trigger = '1' THEN
- -- Using the crosslets_info_reg directly instead of r.step when start trigger coincides with the current eop as step can have a new value.
- v_offsets(I) := r.offsets(I) + TO_UINT(crosslets_info_reg(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w));
- ELSE
- v_offsets(I) := r.offsets(I) + r.step;
- END IF;
+ v_offsets(I) := r.offsets(I) + r.step;
END LOOP;
END IF;
@@ -265,7 +265,7 @@ BEGIN
col_select_miso => col_select_miso,
-- Streaming
- input_sosi_arr => in_sosi_arr,
+ input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
output_sosi_arr => col_sosi_arr
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 1fd2d2c1e333e3104de5eef5c38b77fe25b05fc5..34b60a15799eb9df0f09cf094161f44206c08df7 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -329,10 +329,9 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_xst_nof_blk_per_sync_min : NATURAL := 19530;
-- XSUB MM address widths
- CONSTANT c_sdp_reg_dp_sync_insert_v2_addr_w : NATURAL := 1;
- CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
- CONSTANT c_sdp_reg_bsn_scheduler_xsub_addr_w : NATURAL := 1;
- CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
+ CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
+ CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
END PACKAGE sdp_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 15b936c1d5495941c4748df81b6ab6e6d649c810..539d746a1009a53a7ae7dfbcf07e5b2e11ac2ce8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -170,21 +170,17 @@ ENTITY sdp_station IS
----------------------------------------------
-- XSUB
----------------------------------------------
- -- dp_sync_insert_v2
- reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_sync_insert_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
-
-- crosslets_info
- reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
- reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
-- st_xsq
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
----------------------------------------------
-- BF
@@ -506,36 +502,34 @@ BEGIN
g_P_sq => g_P_sq
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
-
- xst_udp_sosi => udp_tx_sosi_arr(1),
- xst_udp_siso => udp_tx_siso_arr(1),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
-
- reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
- sdp_info => sdp_info,
- gn_id => gn_id,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => xst_udp_src_port
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
);
END GENERATE;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 127f1499fa098add9f4dadca0f90ce6c0071c054..7c77ebee3ecb18b9bede4a495e1fa4540781b9e6 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -65,7 +65,9 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
CONSTANT c_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval
CONSTANT c_nof_ch_sel : NATURAL := c_N_crosslets*c_nof_ch_sel_col*c_nof_ch_sel_row;
- CONSTANT scheduled_bsn : NATURAL := 11;
+ CONSTANT c_ctrl_interval_size : NATURAL := c_nof_block_per_sync * c_nof_ch_in;
+ CONSTANT c_scheduled_bsn : NATURAL := 11;
+ CONSTANT c_nof_block_dly : NATURAL := c_nof_block_per_sync;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
@@ -83,7 +85,7 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL exp_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL bsn : NATURAL := scheduled_bsn-1;
+ SIGNAL bsn : NATURAL := c_scheduled_bsn - c_nof_block_dly;
SIGNAL in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
@@ -105,8 +107,11 @@ BEGIN
proc_common_wait_until_low(mm_clk, rst);
proc_common_wait_some_cycles(mm_clk, 50); -- Give dut some time to start
-- BSN Scheduler
- proc_mem_mm_bus_wr(0, scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
- proc_mem_mm_bus_wr(1, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(1, c_ctrl_interval_size, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(2, c_scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(3, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
+ proc_mem_mm_bus_wr(0, 1, mm_clk, mm_trigger_miso, mm_trigger_mosi); --enable
+
-- crosslet info
FOR I IN 0 TO c_N_crosslets-1 LOOP
@@ -198,8 +203,8 @@ BEGIN
exp_sosi.eop <= '1';
END IF;
- exp_sosi.re <= TO_DP_DSP_DATA( I * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
- exp_sosi.im <= TO_DP_DSP_DATA(1+ I * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ exp_sosi.re <= TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
+ exp_sosi.im <= TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
proc_common_wait_some_cycles(clk, 1);
END LOOP;
@@ -225,7 +230,8 @@ BEGIN
u_dut : ENTITY work.sdp_crosslets_subband_select
GENERIC MAP (
- g_N_crosslets => c_N_crosslets
+ g_N_crosslets => c_N_crosslets,
+ g_ctrl_interval_size_min => 1
)
PORT MAP (
dp_rst => rst,
@@ -237,8 +243,8 @@ BEGIN
reg_crosslets_info_mosi => mm_mosi,
reg_crosslets_info_miso => mm_miso,
- reg_bsn_scheduler_xsub_mosi => mm_trigger_mosi,
- reg_bsn_scheduler_xsub_miso => mm_trigger_miso,
+ reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
-- Streaming
in_sosi_arr => in_sosi_arr,
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 9cc984efdde5e083ce57a73815e6cb4d062c570b..d073bc7656d3f1d807df2b3a5661317f7fd26f45 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -93,6 +93,7 @@ synth_files =
src/vhdl/mms_dp_bsn_scheduler.vhd
src/vhdl/dp_bsn_sync_scheduler.vhd
src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+ src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
src/vhdl/dp_bsn_delay.vhd
src/vhdl/dp_bsn_align.vhd
src/vhdl/dp_bsn_align_reg.vhd
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 842fa3175e688d1c4048b4417abd2a526e9e6579..75b42316d077b32591da03f6a12aff7ee6da26d9 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -62,8 +62,9 @@ USE work.dp_stream_pkg.ALL;
ENTITY mmp_dp_bsn_sync_scheduler IS
GENERIC (
- g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256 -- = number of data valid per BSN block, must be >= 2
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
);
PORT (
-- Clocks and reset
@@ -126,7 +127,8 @@ BEGIN
-- Register mapping
-- . Write
wr_ctrl_enable <= reg_wr( 0);
- ctrl_interval_size <= TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w));
+ ctrl_interval_size <= TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w)) WHEN
+ g_ctrl_interval_size_min < TO_UINT(reg_wr( 2*c_word_w-1 DOWNTO 1*c_word_w)) ELSE g_ctrl_interval_size_min;
wr_start_bsn_64( c_word_w-1 DOWNTO 0) <= reg_wr( 3*c_word_w-1 DOWNTO 2*c_word_w); -- low word
wr_start_bsn_64(2*c_word_w-1 DOWNTO 1*c_word_w) <= reg_wr( 4*c_word_w-1 DOWNTO 3*c_word_w); -- high word
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..38a473d061ab50d2a974dc5bc071b5a8d8f9225f
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
@@ -0,0 +1,117 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+--
+-- Author : R. vd Walle
+-- Purpose : Array wrapper for mmp_dp_bsn_sync_scheduler.vhd
+-- Description: This component is wrapper that uses mmp_dp_bsn_sync_scheduler.vhd
+-- with input 0 to determine the streaming control (sync, sop, eop, valid). So
+-- it is assumed that all inputs in in_sosi_arr have identical control signals.
+--
+-- Remarks: See mmp_dp_bsn_sync_scheduler.vhd
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+
+ENTITY mmp_dp_bsn_sync_scheduler_arr IS
+ GENERIC (
+ g_nof_streams : POSITIVE := 1;
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- MM control
+ reg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_miso : OUT t_mem_miso;
+
+ -- Streaming
+ in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_start : OUT STD_LOGIC;
+ out_enable : OUT STD_LOGIC
+ );
+END mmp_dp_bsn_sync_scheduler_arr;
+
+ARCHITECTURE str OF mmp_dp_bsn_sync_scheduler_arr IS
+ CONSTANT c_pipeline : NATURAL := 1;
+
+ SIGNAL single_src_out : t_dp_sosi;
+
+ SIGNAL in_sosi_arr_piped : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+BEGIN
+
+ -- dp_bsn_sync_scheduler
+ u_mmp_dp_bsn_sync_scheduler : ENTITY work.mmp_dp_bsn_sync_scheduler
+ GENERIC MAP (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ in_sosi => in_sosi_arr(0),
+ out_sosi => single_src_out,
+
+ out_start => out_start,
+ out_enable => out_enable
+ );
+
+ -- Pipeline in_sosi_arr to compensate for the latency in mmp_dp_bsn_sync_scheduler
+ u_dp_pipeline_arr : ENTITY work.dp_pipeline_arr
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_piped
+ );
+
+ p_streams : PROCESS(in_sosi_arr_piped, single_src_out)
+ BEGIN
+ out_sosi_arr <= in_sosi_arr_piped;
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ out_sosi_arr(I).sop <= single_src_out.sop;
+ out_sosi_arr(I).eop <= single_src_out.eop;
+ out_sosi_arr(I).valid <= single_src_out.valid;
+ out_sosi_arr(I).sync <= single_src_out.sync;
+ END LOOP;
+ END PROCESS;
+
+END str;