diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
index bcf7bcb336f04ca6d178e8290dbe30c38ded18d5..44841b83ea909e6ece0c310b9ff30d6257483eb0 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
@@ -47,6 +47,13 @@ PACKAGE tb_tech_mac_10g_pkg IS
FUNCTION func_tech_mac_10g_header_size(data_type : NATURAL) RETURN NATURAL; -- raw ethernet: 4 header words, protocol ethernet: 11 header words
-- Configure the 10G MAC
+ PROCEDURE proc_tech_mac_10g_setup(CONSTANT c_technology : IN NATURAL;
+ CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
+ CONSTANT mm_offset : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mem_miso;
+ SIGNAL mm_mosi : OUT t_mem_mosi);
+
PROCEDURE proc_tech_mac_10g_setup(CONSTANT c_technology : IN NATURAL;
CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
SIGNAL mm_clk : IN STD_LOGIC;
@@ -54,11 +61,13 @@ PACKAGE tb_tech_mac_10g_pkg IS
SIGNAL mm_mosi : OUT t_mem_mosi);
PROCEDURE proc_tech_mac_10g_setup_stratixiv(CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
+ CONSTANT mm_offset : IN NATURAL;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi);
PROCEDURE proc_tech_mac_10g_setup_arria10(CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
+ CONSTANT mm_offset : IN NATURAL;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi);
@@ -108,22 +117,34 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
END func_tech_mac_10g_header_size;
- -- Configure the 10G MAC
+ -- Configure the 10G MAC
PROCEDURE proc_tech_mac_10g_setup(CONSTANT c_technology : IN NATURAL;
CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
+ CONSTANT mm_offset : IN NATURAL;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi) IS
BEGIN
CASE c_technology IS
- WHEN c_tech_stratixiv => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_clk, mm_miso, mm_mosi);
- WHEN c_tech_arria10 => proc_tech_mac_10g_setup_arria10( src_mac, mm_clk, mm_miso, mm_mosi);
- WHEN OTHERS => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
+ WHEN c_tech_stratixiv => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
+ WHEN c_tech_arria10 => proc_tech_mac_10g_setup_arria10( src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
+ WHEN OTHERS => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
END CASE;
END proc_tech_mac_10g_setup;
+ PROCEDURE proc_tech_mac_10g_setup(CONSTANT c_technology : IN NATURAL;
+ CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mem_miso;
+ SIGNAL mm_mosi : OUT t_mem_mosi) IS
+ BEGIN
+ proc_tech_mac_10g_setup(c_technology, src_mac, 0, mm_clk, mm_miso, mm_mosi);
+ END proc_tech_mac_10g_setup;
+
+
-- . The src_mac[47:0] = 0x123456789ABC for MAC address 12-34-56-78-9A-BC
PROCEDURE proc_tech_mac_10g_setup_stratixiv(CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
+ CONSTANT mm_offset : IN NATURAL;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi) IS
@@ -134,48 +155,49 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
BEGIN
-- MAC control
-- . rx read
- proc_mem_mm_bus_rd(16#0040#, mm_clk, mm_miso, mm_mosi); -- RW, rx_padcrc_control = 0x1, remove CRC (use 0x3 to also remove padding)
- proc_mem_mm_bus_rd(16#0080#, mm_clk, mm_miso, mm_mosi); -- RW, rx_padcheck_control = 0x2, check CRC
- proc_mem_mm_bus_rd(16#0800#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_control = 0x3, for promiscuous (transparent) mode
- -- [0] = 0 only receive SRC_MAC, 1 accept all unicast
- -- [1] = 0 drop multi cast, 1 to accept all multicast
- proc_mem_mm_bus_rd(16#0801#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_maxlength = 1518 = 0x5EE
- proc_mem_mm_bus_rd(16#0802#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_addr0 = 0, e.g. 0x56789ABC,
- proc_mem_mm_bus_rd(16#0803#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_addr1 = 0, e.g. 0x1234, for primary SRC_MAC = 12-34-56-78-9A-BC
+ proc_mem_mm_bus_rd(mm_offset+16#0040#, mm_clk, mm_miso, mm_mosi); -- RW, rx_padcrc_control = 0x1, remove CRC (use 0x3 to also remove padding)
+ proc_mem_mm_bus_rd(mm_offset+16#0080#, mm_clk, mm_miso, mm_mosi); -- RW, rx_padcheck_control = 0x2, check CRC
+ proc_mem_mm_bus_rd(mm_offset+16#0800#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_control = 0x3, for promiscuous (transparent) mode
+ -- [0] = 0 only receive SRC_MAC, 1 accept all unicast
+ -- [1] = 0 drop multi cast, 1 to accept all multicast
+ proc_mem_mm_bus_rd(mm_offset+16#0801#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_maxlength = 1518 = 0x5EE
+ proc_mem_mm_bus_rd(mm_offset+16#0802#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_addr0 = 0, e.g. 0x56789ABC,
+ proc_mem_mm_bus_rd(mm_offset+16#0803#, mm_clk, mm_miso, mm_mosi); -- RW, rx_frame_addr1 = 0, e.g. 0x1234, for primary SRC_MAC = 12-34-56-78-9A-BC
proc_common_wait_some_cycles(mm_clk, 10);
-- . tx read
- proc_mem_mm_bus_rd(16#1040#, mm_clk, mm_miso, mm_mosi); -- RW, tx_padins_control = 1, insert padding to ensure 64 bytes including CRC
- proc_mem_mm_bus_rd(16#1080#, mm_clk, mm_miso, mm_mosi); -- RW, tx_crcins_control = 3, compute and insert CRC
- proc_mem_mm_bus_rd(16#1120#, mm_clk, mm_miso, mm_mosi); -- RW, tx_unidir_control = 0, use 0x1 to enable unidirectional mode
- proc_mem_mm_bus_rd(16#1200#, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_control = 0, use 0x1 to overwrite frame SRC_MAC with tx_addrins_macaddr0,1
- proc_mem_mm_bus_rd(16#1201#, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_macaddr0 = 0, e.g. 0x56789ABC,
- proc_mem_mm_bus_rd(16#1202#, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_macaddr1 = 0, e.g. 0x1234, for frame SRC_MAC = 12-34-56-78-9A-BC
- proc_mem_mm_bus_rd(16#1801#, mm_clk, mm_miso, mm_mosi); -- RW, tx_frame_maxlength = 1518 = 0x5EE
+ proc_mem_mm_bus_rd(mm_offset+16#1040#, mm_clk, mm_miso, mm_mosi); -- RW, tx_padins_control = 1, insert padding to ensure 64 bytes including CRC
+ proc_mem_mm_bus_rd(mm_offset+16#1080#, mm_clk, mm_miso, mm_mosi); -- RW, tx_crcins_control = 3, compute and insert CRC
+ proc_mem_mm_bus_rd(mm_offset+16#1120#, mm_clk, mm_miso, mm_mosi); -- RW, tx_unidir_control = 0, use 0x1 to enable unidirectional mode
+ proc_mem_mm_bus_rd(mm_offset+16#1200#, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_control = 0, use 0x1 to overwrite frame SRC_MAC with tx_addrins_macaddr0,1
+ proc_mem_mm_bus_rd(mm_offset+16#1201#, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_macaddr0 = 0, e.g. 0x56789ABC,
+ proc_mem_mm_bus_rd(mm_offset+16#1202#, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_macaddr1 = 0, e.g. 0x1234, for frame SRC_MAC = 12-34-56-78-9A-BC
+ proc_mem_mm_bus_rd(mm_offset+16#1801#, mm_clk, mm_miso, mm_mosi); -- RW, tx_frame_maxlength = 1518 = 0x5EE
proc_common_wait_some_cycles(mm_clk, 10);
---- . rx set primary SRC_MAC
- --proc_mem_mm_bus_wr(16#0802#, c_mac0, mm_clk, mm_miso, mm_mosi); -- src_mac(31 DOWNTO 0)
- --proc_mem_mm_bus_wr(16#0803#, c_mac1, mm_clk, mm_miso, mm_mosi); -- src_mac(47 DOWNTO 32) <-- primary SRC_MAC = 12-34-56-78-9A-BC
- --proc_mem_mm_bus_rd(16#0802#, mm_clk, mm_miso, mm_mosi); -- src_mac(31 DOWNTO 0)
- --proc_mem_mm_bus_rd(16#0803#, mm_clk, mm_miso, mm_mosi); -- src_mac(47 DOWNTO 32)
+ --proc_mem_mm_bus_wr(mm_offset+16#0802#, c_mac0, mm_clk, mm_miso, mm_mosi); -- src_mac(31 DOWNTO 0)
+ --proc_mem_mm_bus_wr(mm_offset+16#0803#, c_mac1, mm_clk, mm_miso, mm_mosi); -- src_mac(47 DOWNTO 32) <-- primary SRC_MAC = 12-34-56-78-9A-BC
+ --proc_mem_mm_bus_rd(mm_offset+16#0802#, mm_clk, mm_miso, mm_mosi); -- src_mac(31 DOWNTO 0)
+ --proc_mem_mm_bus_rd(mm_offset+16#0803#, mm_clk, mm_miso, mm_mosi); -- src_mac(47 DOWNTO 32)
--proc_common_wait_some_cycles(mm_clk, 10);
--
---- . tx insert frame SRC_MAC
- --proc_mem_mm_bus_wr(16#1200#, 1, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_control = 1 to overwrite frame SRC_MAC with tx_addrins_macaddr0,1
- --proc_mem_mm_bus_wr(16#1201#, c_mac0, mm_clk, mm_miso, mm_mosi); -- src_mac(31 DOWNTO 0)
- --proc_mem_mm_bus_wr(16#1202#, c_mac1, mm_clk, mm_miso, mm_mosi); -- src_mac(47 DOWNTO 32) <-- frame SRC_MAC = 12-34-56-78-9A-BC
+ --proc_mem_mm_bus_wr(mm_offset+16#1200#, 1, mm_clk, mm_miso, mm_mosi); -- RW, tx_addrins_control = 1 to overwrite frame SRC_MAC with tx_addrins_macaddr0,1
+ --proc_mem_mm_bus_wr(mm_offset+16#1201#, c_mac0, mm_clk, mm_miso, mm_mosi); -- src_mac(31 DOWNTO 0)
+ --proc_mem_mm_bus_wr(mm_offset+16#1202#, c_mac1, mm_clk, mm_miso, mm_mosi); -- src_mac(47 DOWNTO 32) <-- frame SRC_MAC = 12-34-56-78-9A-BC
--proc_common_wait_some_cycles(mm_clk, 10);
WAIT UNTIL rising_edge(mm_clk);
END proc_tech_mac_10g_setup_stratixiv;
PROCEDURE proc_tech_mac_10g_setup_arria10(CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
+ CONSTANT mm_offset : IN NATURAL;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi) IS
BEGIN
- proc_tech_mac_10g_setup_stratixiv(src_mac, mm_clk, mm_miso, mm_mosi);
+ proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
END proc_tech_mac_10g_setup_arria10;
-- Transmit user packet
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd
index eb0369b9e41b3e5b801b646ce139ab2fa6a84c76..52b16a336298c4e59b54557a77b55b2e21d98c24 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd
@@ -30,21 +30,23 @@ USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-USE WORK.tb_tech_mac_10g_pkg.ALL;
+USE work.tb_tech_mac_10g_pkg.ALL;
+USE work.tech_mac_10g_component_pkg.ALL;
ENTITY tb_tech_mac_10g_setup IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_nof_macs : POSITIVE := 1;
g_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"123456789ABC" -- = 12-34-56-78-9A-BC
);
PORT (
- tb_end : IN STD_LOGIC := '0';
- mm_clk : OUT STD_LOGIC;
- mm_rst : OUT STD_LOGIC;
- mm_init : OUT STD_LOGIC;
- mm_mosi : OUT t_mem_mosi;
- mm_miso : IN t_mem_miso
+ tb_end : IN STD_LOGIC := '0';
+ mm_clk : OUT STD_LOGIC;
+ mm_rst : OUT STD_LOGIC;
+ mm_init : OUT STD_LOGIC;
+ mac_mosi : OUT t_mem_mosi;
+ mac_miso : IN t_mem_miso
);
END tb_tech_mac_10g_setup;
@@ -66,18 +68,23 @@ BEGIN
i_mm_rst <= '1', '0' AFTER mm_clk_period*10;
p_mm_setup : PROCESS
+ VARIABLE v_mm_offset : NATURAL;
BEGIN
mm_init <= '1';
- mm_mosi.wr <= '0';
- mm_mosi.rd <= '0';
+ mac_mosi.wr <= '0';
+ mac_mosi.rd <= '0';
-- wait until after reset release
proc_common_wait_until_low(i_mm_clk, i_mm_rst);
proc_common_wait_some_cycles(i_mm_clk, 10);
- proc_tech_mac_10g_setup(g_technology,
- g_src_mac,
- i_mm_clk, mm_miso, mm_mosi);
+ FOR I IN 0 TO g_nof_macs-1 LOOP
+ v_mm_offset := I * 2**func_tech_mac_10g_csr_addr_w(g_technology);
+ proc_tech_mac_10g_setup(g_technology,
+ g_src_mac,
+ v_mm_offset,
+ i_mm_clk, mac_miso, mac_mosi);
+ END LOOP;
mm_init <= '0';
WAIT;
END PROCESS;