diff --git a/libraries/base/reorder/src/vhdl/reorder_col.vhd b/libraries/base/reorder/src/vhdl/reorder_col.vhd
index e4805d9aaf30dc1516fa4a56a126ea4d8e85a60b..81932c31863338395eb670f9305ed7118e1f006d 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col.vhd
@@ -61,7 +61,9 @@ use technology_lib.technology_select_pkg.all;
entity reorder_col is
generic (
g_technology : natural := c_tech_select_default;
- g_use_output_rl_adapter : boolean := false; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which is fine if no flow control is needed.
+ -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which
+ -- is fine if no flow control is needed.
+ g_use_output_rl_adapter : boolean := false;
g_dsp_data_w : natural := 18; -- complex data width, = c_data_w / 2
g_nof_ch_in : natural := 512;
g_nof_ch_sel : natural := 252; -- g_nof_ch_sel < g_nof_ch_in
@@ -106,7 +108,8 @@ architecture str of reorder_col is
constant c_info_nof_pages : natural := 2; -- fixed, fits the dual page block latency and logic latency of the SS
constant c_retrieve_lat : natural := c_select_buf.latency + c_store_buf.latency; -- = 2
- constant c_output_rl : natural := sel_a_b(g_use_output_rl_adapter, 1, c_retrieve_lat); -- force SS RL from 2 -> 1 or leave it at 2
+ -- force output ready latency (RL) from 2 -> 1 or leave it at 2
+ constant c_output_rl : natural := sel_a_b(g_use_output_rl_adapter, 1, c_retrieve_lat);
signal info_sop_wr_en : std_logic_vector(c_info_nof_pages - 1 downto 0);
signal info_eop_wr_en : std_logic_vector(c_info_nof_pages - 1 downto 0);
@@ -157,10 +160,8 @@ begin
-- Streaming
input_sosi => input_sosi,
-
-- Timing
store_done => store_done,
-
-- Write store buffer control
store_mosi => store_mosi
);
@@ -260,7 +261,8 @@ begin
src_out => ss_sosi
);
- -- Page delay the input_sosi info (sync, BSN, channel at sop and err, empty at eop) and combine it with the retrieved SS data to get the output_sosi
+ -- Page delay the input_sosi info (sync, BSN, channel at sop and err, empty at eop) and combine
+ -- it with the retrieved SS data to get the output_sosi.
info_sop_wr_en <= input_sosi.sop & store_done;
info_eop_wr_en <= input_sosi.eop & store_done;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
index dc2c4dcf332348b501c228bc2f343cf873fe14d3..240353b0dd1b65c2b3aad18f7d66e2b322ea3051 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
@@ -209,9 +209,11 @@ begin
retrieve_sosi.im <= RESIZE_DP_DSP_DATA(i_col_select_miso.rddata(c_nof_complex * g_dsp_data_w - 1 downto g_dsp_data_w));
retrieve_sosi.data <= RESIZE_DP_DATA(i_col_select_miso.rddata(c_data_w - 1 downto 0));
retrieve_sosi.valid <= i_col_select_miso.rdval;
- retrieve_sosi.sop <= retrieve_sop_dly(c_retrieve_lat) and i_col_select_miso.rdval; -- Only set sop/eop when valid.
+ -- Only set sop/eop when valid.
+ retrieve_sosi.sop <= retrieve_sop_dly(c_retrieve_lat) and i_col_select_miso.rdval;
retrieve_sosi.eop <= retrieve_eop_dly(c_retrieve_lat) and i_col_select_miso.rdval;
- -- Page delay the input_sosi info (sync, BSN, channel at sop and err, empty at eop) and combine it with the retrieved SS data to get the output_sosi
+ -- Page delay the input_sosi info (sync, BSN, channel at sop and err, empty at eop) and combine
+ -- it with the retrieved SS data to get the output_sosi
info_sop_wr_en <= input_sosi.sop & store_done;
info_eop_wr_en <= input_sosi.eop & store_done;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
index 0d30faaf07885fe57a878e20da0eee3d2c09e6a4..3f466937dce702952ab8e8f19ee6edc5462030e4 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
@@ -59,10 +59,10 @@ entity reorder_col_wide is
ram_ss_ss_wide_miso : out t_mem_miso;
-- Streaming
- input_sosi_arr : in t_dp_sosi_arr(g_wb_factor - 1 downto 0); -- complex input
- input_siso_arr : out t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy); -- complex input
+ input_sosi_arr : in t_dp_sosi_arr(g_wb_factor - 1 downto 0);
+ input_siso_arr : out t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy);
- output_sosi_arr : out t_dp_sosi_arr(g_wb_factor - 1 downto 0); -- selected complex output with flow control
+ output_sosi_arr : out t_dp_sosi_arr(g_wb_factor - 1 downto 0); -- selected output
output_siso_arr : in t_dp_siso_arr(g_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy)
);
end reorder_col_wide;
diff --git a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
index 12ddc0c35852bc2eccba44f8dbaea6893b73d650..099f85a16e4b0bec33889d98a660f8fd9ff333ce 100644
--- a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
@@ -116,7 +116,8 @@ begin
u_retrieve_en : entity common_lib.common_switch
generic map (
g_rst_level => '0',
- g_priority_lo => false, -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ -- store_done has priority over nxt_retrieve_done when they occur simultaneously
+ g_priority_lo => false,
g_or_high => true,
g_and_low => false
)
@@ -124,7 +125,9 @@ begin
rst => rst,
clk => clk,
switch_high => store_done,
- switch_low => nxt_retrieve_done, -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done occurs after next store_done then that page gets missed
+ -- can not use retrieve_done with g_and_low = TRUE, because if retrieve_done
+ -- occurs after next store_done then that page gets missed
+ switch_low => nxt_retrieve_done,
out_level => retrieve_en
);
@@ -158,7 +161,8 @@ begin
retrieve_mosi.rd <= prev_retrieve_ready;
retrieve_mosi.address <= RESIZE_MEM_ADDRESS(select_miso.rddata(ceil_log2(g_nof_ch_in) - 1 downto 0));
- -- The output_sosi has RL=2, because of the read accesses to the select buf followed by the read access to the store buf, both with read latency is 1, so c_retrieve_lat=2
+ -- The output_sosi has RL=2, because of the read accesses to the select buf followed by the
+ -- read access to the store buf, both with read latency is 1, so c_retrieve_lat=2.
output_sosi.re <= RESIZE_DP_DSP_DATA(retrieve_miso.rddata( g_dsp_data_w - 1 downto 0));
output_sosi.im <= RESIZE_DP_DSP_DATA(retrieve_miso.rddata(c_nof_complex * g_dsp_data_w - 1 downto g_dsp_data_w));
output_sosi.data <= RESIZE_DP_DATA(retrieve_miso.rddata(c_data_w - 1 downto 0));
diff --git a/libraries/base/reorder/src/vhdl/reorder_row.vhd b/libraries/base/reorder/src/vhdl/reorder_row.vhd
index 7a6b8edeca6f9b8c0e9ed3eac8fdb99c4cfd5a2d..e241da3b4c8e921a61cabfd8350f86d185a9e3d3 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row.vhd
@@ -46,6 +46,7 @@ entity reorder_row is
g_frame_size : natural := 256;
g_nof_inputs : natural := 8;
g_nof_outputs : natural := 16;
+ g_use_complex : boolean := true;
g_ram_init_file : string := "../../../src/data/select_buf"; -- or "UNUSED"
g_pipeline_in : natural := 1; -- pipeline in_data
g_pipeline_in_m : natural := 1; -- pipeline in_data for M-fold fan out
@@ -123,8 +124,15 @@ begin
-- selection buffer.
---------------------------------------------------------------
gen_input : for I in g_nof_inputs - 1 downto 0 generate
- reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <= r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w - 1 downto 0) &
- r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w - 1 downto 0);
+ use_complex : if g_use_complex generate
+ reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
+ r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w - 1 downto 0) &
+ r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w - 1 downto 0);
+ end generate;
+ use_data : if not g_use_complex generate
+ reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
+ r.pipe_sosi_2arr(0)(I).data(c_data_w - 1 downto 0);
+ end generate;
end generate;
---------------------------------------------------------------
@@ -217,16 +225,22 @@ begin
---------------------------------------------------------------
comb : process(r, input_sosi_arr, reorder_out_dat)
variable v : reg_type;
+ -- Use intermediate variables to avoid too long code lines
+ variable v_re : std_logic_vector(g_dsp_data_w - 1 downto 0);
+ variable v_im : std_logic_vector(g_dsp_data_w - 1 downto 0);
begin
v := r;
v.pipe_sosi_2arr(0) := input_sosi_arr;
v.pipe_sosi_2arr(c_tot_pipeline-1 downto 1) := r.pipe_sosi_2arr(c_tot_pipeline-2 downto 0);
-- Merge data output to the outgoing SOSI record.
+ -- Assigning re,im is don't care when g_use_complex is false.
for I in g_nof_outputs - 1 downto 0 loop
+ v_im := reorder_out_dat((I + 1) * c_data_w - 1 downto I * c_data_w + g_dsp_data_w);
+ v_re := reorder_out_dat((I + 1) * c_data_w - g_dsp_data_w - 1 downto I * c_data_w);
v.output_sosi_arr(I) := r.pipe_sosi_2arr(c_tot_pipeline-1)(0);
- v.output_sosi_arr(I).im := RESIZE_DP_DSP_DATA(reorder_out_dat((I + 1) * c_data_w - 1 downto I * c_data_w + g_dsp_data_w));
- v.output_sosi_arr(I).re := RESIZE_DP_DSP_DATA(reorder_out_dat((I + 1) * c_data_w - g_dsp_data_w - 1 downto I * c_data_w));
+ v.output_sosi_arr(I).im := RESIZE_DP_DSP_DATA(v_im);
+ v.output_sosi_arr(I).re := RESIZE_DP_DSP_DATA(v_re);
end loop;
rin <= v;
diff --git a/libraries/base/reorder/src/vhdl/reorder_store.vhd b/libraries/base/reorder/src/vhdl/reorder_store.vhd
index 924bfb69b3f3609a8571652a4ab49c8f85eaa4a3..71253d4adbc95b3b68b4e95821619b80aeafc25c 100644
--- a/libraries/base/reorder/src/vhdl/reorder_store.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_store.vhd
@@ -74,6 +74,9 @@ architecture rtl of reorder_store is
signal ch_cnt : integer range 0 to g_nof_ch_in - 1;
signal nxt_ch_cnt : integer;
+ signal input_im_re : std_logic_vector(c_data_w - 1 downto 0);
+ signal input_data : std_logic_vector(c_data_w - 1 downto 0);
+
signal i_store_mosi : t_mem_mosi;
signal nxt_store_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -117,13 +120,17 @@ begin
nxt_store_mosi.wr <= input_sosi.valid;
nxt_store_mosi.address <= TO_MEM_ADDRESS(ch_cnt) when input_sosi.valid = '1' else i_store_mosi.address;
+ -- Use intermediate signals to avoid too long code lines
+ input_im_re <= input_sosi.im(g_dsp_data_w - 1 downto 0) & input_sosi.re(g_dsp_data_w - 1 downto 0);
+ input_data <= input_sosi.data(c_data_w - 1 downto 0);
+
-- Use complex data fields
- gen_complex : if g_use_complex generate
- nxt_store_mosi.wrdata <= RESIZE_MEM_DATA(input_sosi.im(g_dsp_data_w - 1 downto 0) & input_sosi.re(g_dsp_data_w - 1 downto 0)) when input_sosi.valid = '1' else i_store_mosi.wrdata;
+ use_complex : if g_use_complex generate
+ nxt_store_mosi.wrdata <= RESIZE_MEM_DATA(input_im_re) when input_sosi.valid = '1' else i_store_mosi.wrdata;
end generate;
-- Use regular data field
- gen_data : if not(g_use_complex) generate
- nxt_store_mosi.wrdata <= RESIZE_MEM_DATA(input_sosi.data(c_data_w - 1 downto 0)) when input_sosi.valid = '1' else i_store_mosi.wrdata;
+ use_data : if not g_use_complex generate
+ nxt_store_mosi.wrdata <= RESIZE_MEM_DATA(input_data) when input_sosi.valid = '1' else i_store_mosi.wrdata;
end generate;
end rtl;