diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
index 00c40d89cdda2b6b57b84a71a45ed853a3750c0c..21af65d82ada812cdef1c9640d0e2ab6c8d853ed 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
@@ -25,8 +25,10 @@
 --   tr_ref_clk_644.
 --   The tb is self checking based on that tb_tech_eth_10g is self checking
 --   and both tb_tech_eth_10g instances send the same and expect the same.
+-- Remarks:
+--   . For c_tech_arria10 the test fails when g_nof_10ppm /= 0 (erko, 21 nov 2014)
 -- Usage:
---   > as 14
+--   > as 16
 --   > run -all
 
 LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib;
@@ -38,7 +40,8 @@ USE tech_pll_lib.tech_pll_component_pkg.ALL;
 ENTITY tb_tech_eth_10g_ppm IS
   -- Test bench control parameters
   GENERIC (
-    g_technology : NATURAL := c_tech_select_default
+    g_technology : NATURAL := c_tech_select_default;
+    g_nof_10ppm  : INTEGER := 1    -- use /= 0 to verify XO ppm offset between two devices
   );
 END tb_tech_eth_10g_ppm;
 
@@ -52,9 +55,9 @@ BEGIN
   u_tb_tech_eth_10g_0 : ENTITY work.tb_tech_eth_10g
   GENERIC MAP (
     g_technology              => g_technology,
-    g_tech_pll_clk_644_period => tech_pll_clk_644_period - tech_pll_clk_644_10ppm,
+    g_tech_pll_clk_644_period => tech_pll_clk_644_period,
     g_verify_link_recovery    => FALSE,
-    g_link_status_check       => "01",
+    g_link_status_check       => "11",
     g_use_rx_serial_in        => TRUE
   )
   PORT MAP (
@@ -65,9 +68,9 @@ BEGIN
   u_tb_tech_eth_10g_1 : ENTITY work.tb_tech_eth_10g
   GENERIC MAP (
     g_technology              => g_technology,
-    g_tech_pll_clk_644_period => tech_pll_clk_644_period + tech_pll_clk_644_10ppm,
+    g_tech_pll_clk_644_period => tech_pll_clk_644_period + tech_pll_clk_644_10ppm * g_nof_10ppm,
     g_verify_link_recovery    => FALSE,
-    g_link_status_check       => "01",
+    g_link_status_check       => "11",
     g_use_rx_serial_in        => TRUE
   )
   PORT MAP (