diff --git a/libraries/technology/altera/stratixiv/hdllib.cfg b/libraries/technology/altera/stratixiv/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..580ea5fe8978fc22e8b3ac07557045a1d3536e96 --- /dev/null +++ b/libraries/technology/altera/stratixiv/hdllib.cfg @@ -0,0 +1,12 @@ +hdl_lib_name = ip_stratixiv +hdl_library_clause_name = ip_stratixiv_lib +hdl_lib_uses = + +build_sim_dir = $HDL_BUILD_DIR +build_synth_dir = + +synth_files = + ip_stratixiv_asmi_parallel.vhd + ip_stratixiv_remote_update.vhd + +test_bench_files = diff --git a/libraries/technology/altera/stratixiv/ip_stratixiv_asmi_parallel.vhd b/libraries/technology/altera/stratixiv/ip_stratixiv_asmi_parallel.vhd new file mode 100644 index 0000000000000000000000000000000000000000..cd9445467748dc76d1cd911b26c9a754f48a1e22 --- /dev/null +++ b/libraries/technology/altera/stratixiv/ip_stratixiv_asmi_parallel.vhd @@ -0,0 +1,2391 @@ +-- megafunction wizard: %ALTASMI_PARALLEL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: ALTASMI_PARALLEL + +-- ============================================================ +-- File Name: ip_stratixiv_asmi_parallel.vhd +-- Megafunction Name(s): +-- ALTASMI_PARALLEL +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2011 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +--altasmi_parallel CBX_AUTO_BLACKBOX="ALL" DATA_WIDTH="STANDARD" DEVICE_FAMILY="Stratix IV" EPCS_TYPE="EPCS128" PAGE_SIZE=256 PORT_BULK_ERASE="PORT_UNUSED" PORT_EN4B_ADDR="PORT_UNUSED" PORT_FAST_READ="PORT_UNUSED" PORT_ILLEGAL_ERASE="PORT_USED" PORT_ILLEGAL_WRITE="PORT_USED" PORT_RDID_OUT="PORT_UNUSED" PORT_READ_ADDRESS="PORT_UNUSED" PORT_READ_RDID="PORT_UNUSED" PORT_READ_SID="PORT_UNUSED" PORT_READ_STATUS="PORT_UNUSED" PORT_SECTOR_ERASE="PORT_USED" PORT_SECTOR_PROTECT="PORT_UNUSED" PORT_SHIFT_BYTES="PORT_USED" PORT_WREN="PORT_USED" PORT_WRITE="PORT_USED" USE_EAB="ON" addr busy clkin data_valid datain dataout illegal_erase illegal_write rden read sector_erase shift_bytes wren write INTENDED_DEVICE_FAMILY="Stratix IV" ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106 +--VERSION_BEGIN 11.1SP2 cbx_a_gray2bin 2012:01:25:21:12:11:SJ cbx_a_graycounter 2012:01:25:21:12:11:SJ cbx_altasmi_parallel 2012:01:25:21:12:11:SJ cbx_altdpram 2012:01:25:21:12:11:SJ cbx_altsyncram 2012:01:25:21:12:11:SJ cbx_cyclone 2012:01:25:21:12:11:SJ cbx_cycloneii 2012:01:25:21:12:11:SJ cbx_fifo_common 2012:01:25:21:12:11:SJ cbx_lpm_add_sub 2012:01:25:21:12:11:SJ cbx_lpm_compare 2012:01:25:21:12:11:SJ cbx_lpm_counter 2012:01:25:21:12:11:SJ cbx_lpm_decode 2012:01:25:21:12:11:SJ cbx_lpm_mux 2012:01:25:21:12:11:SJ cbx_mgl 2012:01:25:21:26:09:SJ cbx_scfifo 2012:01:25:21:12:11:SJ cbx_stratix 2012:01:25:21:12:11:SJ cbx_stratixii 2012:01:25:21:12:11:SJ cbx_stratixiii 2012:01:25:21:12:11:SJ cbx_stratixv 2012:01:25:21:12:11:SJ cbx_util_mgl 2012:01:25:21:12:11:SJ VERSION_END + + LIBRARY altera_mf; + USE altera_mf.all; + + LIBRARY lpm; + USE lpm.all; + + LIBRARY stratixiv; + USE stratixiv.all; + +--synthesis_resources = a_graycounter 4 lpm_compare 2 lpm_counter 2 lut 29 mux21 1 reg 106 stratixiv_asmiblock 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY ip_stratixiv_asmi_parallel_altasmi_parallel_15a2 IS + PORT + ( + addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + busy : OUT STD_LOGIC; + clkin : IN STD_LOGIC; + data_valid : OUT STD_LOGIC; + datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0'); + dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + illegal_erase : OUT STD_LOGIC; + illegal_write : OUT STD_LOGIC; + rden : IN STD_LOGIC; + read : IN STD_LOGIC := '0'; + sector_erase : IN STD_LOGIC := '0'; + shift_bytes : IN STD_LOGIC := '0'; + wren : IN STD_LOGIC := '1'; + write : IN STD_LOGIC := '0' + ); + END ip_stratixiv_asmi_parallel_altasmi_parallel_15a2; + + ARCHITECTURE RTL OF ip_stratixiv_asmi_parallel_altasmi_parallel_15a2 IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2; + ATTRIBUTE ALTERA_ATTRIBUTE : string; + ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "SUPPRESS_DA_RULE_INTERNAL=C106"; + + SIGNAL wire_addbyte_cntr_w_lg_w_q_range119w124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addbyte_cntr_w_lg_w_q_range122w123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addbyte_cntr_clk_en : STD_LOGIC; + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addbyte_cntr_clock : STD_LOGIC; + SIGNAL wire_addbyte_cntr_q : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_addbyte_cntr_w_q_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addbyte_cntr_w_q_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_gen_cntr_w_lg_w_q_range91w92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_gen_cntr_w_lg_w_q_range89w90w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_gen_cntr_clk_en : STD_LOGIC; + SIGNAL wire_w_lg_in_operation35w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_gen_cntr_q : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL wire_gen_cntr_w_q_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_gen_cntr_w_q_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w229w230w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w229w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w234w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w84w226w227w228w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w84w231w232w233w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w82w83w239w240w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w86w304w305w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w251w252w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w226w227w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w231w232w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w82w83w239w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range81w86w304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range81w84w251w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range81w84w226w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range81w84w231w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range81w84w117w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range80w85w99w100w101w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range80w85w99w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_q_range81w82w83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_q_range81w86w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_q_range81w84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range80w85w99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_q_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_lg_w_q_range81w82w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_clk_en : STD_LOGIC; + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w73w74w75w76w77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_q : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_stage_cntr_w_q_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stage_cntr_w_q_range81w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_wrstage_cntr_w_lg_w_q_range455w456w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_wrstage_cntr_w_lg_w_q_range453w454w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_wrstage_cntr_clk_en : STD_LOGIC; + SIGNAL wire_w_lg_w451w452w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_wrstage_cntr_clock : STD_LOGIC; + SIGNAL wire_wrstage_cntr_q : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL wire_wrstage_cntr_w_q_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_wrstage_cntr_w_q_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL add_msb_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_add_msb_reg_ena : STD_LOGIC; + SIGNAL wire_addr_reg_d : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL addr_reg : STD_LOGIC_VECTOR(23 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL wire_addr_reg_ena : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w500w501w502w503w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w500w501w502w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w492w493w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w496w497w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w500w501w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w492w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w496w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w500w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w480w481w482w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w491w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w495w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w480w481w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w484w485w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_q_range308w474w475w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_q_range308w479w480w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_lg_w_q_range308w479w484w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_q_range308w474w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_lg_w_q_range308w479w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_q_range499w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_q_range494w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_q_range489w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_q_range483w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_q_range283w : STD_LOGIC_VECTOR (22 DOWNTO 0); + SIGNAL wire_addr_reg_w_q_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_addr_reg_w_q_range308w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_asmi_opcode_reg_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL asmi_opcode_reg : STD_LOGIC_VECTOR(7 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL wire_asmi_opcode_reg_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL wire_asmi_opcode_reg_w_q_range129w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL buf_empty_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL busy_det_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL clr_addmsb_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL clr_endrbyte_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_clr_endrbyte_reg_w_lg_q370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL clr_read_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL clr_read_reg2 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL clr_rstat_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL clr_rstat_reg2 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL clr_write_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL clr_write_reg2 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL cnt_bfend_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL do_wrmemadd_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL dvalid_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_dvalid_reg_ena : STD_LOGIC; + SIGNAL dvalid_reg2 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL end1_cyc_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL end1_cyc_reg2 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL end_op_hdlyreg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL end_op_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL end_pgwrop_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_end_pgwrop_reg_ena : STD_LOGIC; + SIGNAL end_rbyte_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_end_rbyte_reg_ena : STD_LOGIC; + SIGNAL end_read_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL ill_erase_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL ill_write_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL max_cnt_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL maxcnt_shift_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL maxcnt_shift_reg2 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL ncs_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_ncs_reg_ena : STD_LOGIC; + SIGNAL wire_ncs_reg_w_lg_q273w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwrbuf_dataout_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL pgwrbuf_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL wire_pgwrbuf_dataout_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL wire_pgwrbuf_dataout_w_q_range399w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL read_bufdly_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_read_data_reg_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL read_data_reg : STD_LOGIC_VECTOR(7 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL wire_read_data_reg_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL wire_read_dout_reg_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL read_dout_reg : STD_LOGIC_VECTOR(7 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL wire_read_dout_reg_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL read_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_read_reg_ena : STD_LOGIC; + SIGNAL sec_erase_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_sec_erase_reg_ena : STD_LOGIC; + SIGNAL shftpgwr_data_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL shift_op_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL stage2_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL stage3_dly_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL stage3_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL stage4_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL start_wrpoll_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_start_wrpoll_reg_ena : STD_LOGIC; + SIGNAL start_wrpoll_reg2 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_statreg_int_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL statreg_int : STD_LOGIC_VECTOR(7 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL wire_statreg_int_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL write_prot_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_write_prot_reg_ena : STD_LOGIC; + SIGNAL write_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_write_reg_ena : STD_LOGIC; + SIGNAL write_rstat_reg : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_cmpr4_aeb : STD_LOGIC; + SIGNAL wire_cmpr4_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_cmpr4_datab : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_cmpr5_aeb : STD_LOGIC; + SIGNAL wire_cmpr5_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_cmpr5_datab : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_clk_en : STD_LOGIC; + SIGNAL wire_w_lg_w_lg_w_lg_shift_bytes_wire395w411w412w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_q : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_data_cntr_w_q_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_pgwr_read_cntr_q : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL wire_mux211_dataout : STD_LOGIC; + SIGNAL wire_scfifo3_data : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_scfifo3_q : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wire_scfifo3_rdreq : STD_LOGIC; + SIGNAL wire_w_lg_read_buf397w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_scfifo3_wrreq : STD_LOGIC; + SIGNAL wire_w_lg_w_lg_shift_bytes_wire395w396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_scfifo3_w_q_range402w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_scfifo3_w_q_range407w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_stratixii_asmiblock2_data0out : STD_LOGIC; + SIGNAL wire_w552w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w359w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode140w141w142w192w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode140w141w142w143w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode145w146w147w194w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode145w146w147w148w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode164w165w166w204w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode164w165w166w167w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_read256w257w258w259w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write394w549w550w551w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w554w555w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_read312w356w357w358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_sec_erase300w301w302w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_load_opcode140w141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_load_opcode145w146w147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_load_opcode164w165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_read256w257w258w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_read256w257w303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_write394w549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w554w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_read312w356w357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_bp2_wire471w472w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_4baddr132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_polling379w380w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_sec_erase300w301w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_write153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_write47w235w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode134w188w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode134w135w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode155w198w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode155w156w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode140w141w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode158w200w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode158w159w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode161w202w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode161w162w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode169w206w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode169w170w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode172w208w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode172w173w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode150w196w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode150w151w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode145w146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode164w165w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode137w190w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_load_opcode137w138w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_reach_max_cnt445w446w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_start_poll241w242w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_read256w257w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_write394w549w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_read_bufdly400w401w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w451w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write56w57w460w553w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_write56w57w449w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_write56w57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_read312w356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_write56w293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_end_operation381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_rden_wire297w298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_bp2_wire471w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_4baddr132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_bulk_erase236w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_polling379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_sec_erase300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_write153w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_write54w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_write47w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode161w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode169w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode172w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode145w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode137w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_not_busy291w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_not_busy286w : STD_LOGIC_VECTOR (22 DOWNTO 0); + SIGNAL wire_w_lg_reach_max_cnt445w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_bufdly408w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_bufdly403w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_shift_opcode130w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_stage3_wire296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_stage3_wire323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_stage3_wire284w : STD_LOGIC_VECTOR (22 DOWNTO 0); + SIGNAL wire_w_lg_stage4_wire325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_start_poll241w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_write47w254w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_bp0_wire473w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_bp1_wire477w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_bp2_wire488w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_buf_empty518w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_busy_wire1w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_clkin_wire79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_4baddr546w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_bulk_erase547w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_fast_read255w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_memadd309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_polling250w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_read256w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_read_rdid36w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_read_stat37w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_sec_erase548w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_wren38w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_write394w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_end_add_cycle66w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_end_fast_read60w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_end_ophdly34w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_end_pgwr_data46w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_end_read63w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rden_wire371w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_reach_max_cnt410w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_bufdly400w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_rdid_wire8w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_sid_wire7w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_status_wire21w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_sec_protect_wire6w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_st_busy_wire94w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_prot_true448w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_wire16w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range52w53w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w554w555w556w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_load_opcode172w208w209w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_load_opcode172w173w174w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write56w57w449w450w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_write56w293w294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_rden_wire297w298w299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_not_busy286w287w : STD_LOGIC_VECTOR (22 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_read_bufdly403w404w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_stage4_wire325w326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode172w208w209w210w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_load_opcode172w173w174w175w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_write56w293w294w295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w211w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w176w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w211w212w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w176w177w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w211w212w213w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w176w177w178w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w211w212w213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w176w177w178w179w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w211w212w213w214w215w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w176w177w178w179w180w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w211w212w213w214w215w216w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w_lg_w176w177w178w179w180w181w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w217w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w182w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w217w218w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w182w183w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w182w183w184w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_w_lg_do_read_sid112w113w114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_read312w313w314w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_read_sid112w113w114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_do_write56w57w460w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_read312w324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_read312w313w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_read_sid112w113w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_sec_erase462w463w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_do_write56w57w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_data0out_wire328w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_4baddr237w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_read312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_read_sid112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_read_stat322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_sec_erase462w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_wren238w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_do_write56w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_end_operation381w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_load_opcode220w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rden_wire297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_bufdly398w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range414w417w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range418w420w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_pagewr_buf_not_empty_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL b4addr_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL be_write_prot : STD_LOGIC; + SIGNAL berase_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL bp0_wire : STD_LOGIC; + SIGNAL bp1_wire : STD_LOGIC; + SIGNAL bp2_wire : STD_LOGIC; + SIGNAL bp3_wire : STD_LOGIC; + SIGNAL buf_empty : STD_LOGIC; + SIGNAL busy_wire : STD_LOGIC; + SIGNAL clkin_wire : STD_LOGIC; + SIGNAL clr_read_wire : STD_LOGIC; + SIGNAL clr_rstat_wire : STD_LOGIC; + SIGNAL clr_write_wire : STD_LOGIC; + SIGNAL cnt_bfend_wire_in : STD_LOGIC; + SIGNAL data0out_wire : STD_LOGIC; + SIGNAL data_valid_wire : STD_LOGIC; + SIGNAL dataout_wire : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL do_4baddr : STD_LOGIC; + SIGNAL do_bulk_erase : STD_LOGIC; + SIGNAL do_fast_read : STD_LOGIC; + SIGNAL do_memadd : STD_LOGIC; + SIGNAL do_polling : STD_LOGIC; + SIGNAL do_read : STD_LOGIC; + SIGNAL do_read_rdid : STD_LOGIC; + SIGNAL do_read_sid : STD_LOGIC; + SIGNAL do_read_stat : STD_LOGIC; + SIGNAL do_sec_erase : STD_LOGIC; + SIGNAL do_sec_prot : STD_LOGIC; + SIGNAL do_secprot_wren : STD_LOGIC; + SIGNAL do_sprot_polling : STD_LOGIC; + SIGNAL do_sprot_rstat : STD_LOGIC; + SIGNAL do_wren : STD_LOGIC; + SIGNAL do_write : STD_LOGIC; + SIGNAL do_write_polling : STD_LOGIC; + SIGNAL do_write_rstat : STD_LOGIC; + SIGNAL do_write_wren : STD_LOGIC; + SIGNAL dummy_read_buf : STD_LOGIC; + SIGNAL end1_cyc_gen_cntr_wire : STD_LOGIC; + SIGNAL end1_cyc_normal_in_wire : STD_LOGIC; + SIGNAL end1_cyc_reg_in_wire : STD_LOGIC; + SIGNAL end_add_cycle : STD_LOGIC; + SIGNAL end_add_cycle_mux_datab_wire : STD_LOGIC; + SIGNAL end_fast_read : STD_LOGIC; + SIGNAL end_one_cyc_pos : STD_LOGIC; + SIGNAL end_one_cycle : STD_LOGIC; + SIGNAL end_operation : STD_LOGIC; + SIGNAL end_ophdly : STD_LOGIC; + SIGNAL end_pgwr_data : STD_LOGIC; + SIGNAL end_read : STD_LOGIC; + SIGNAL end_read_byte : STD_LOGIC; + SIGNAL end_wrstage : STD_LOGIC; + SIGNAL fast_read_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL fast_read_wire : STD_LOGIC; + SIGNAL ill_erase_wire : STD_LOGIC; + SIGNAL ill_write_wire : STD_LOGIC; + SIGNAL illegal_erase_b4out_wire : STD_LOGIC; + SIGNAL illegal_write_b4out_wire : STD_LOGIC; + SIGNAL in_operation : STD_LOGIC; + SIGNAL load_opcode : STD_LOGIC; + SIGNAL memadd_sdoin : STD_LOGIC; + SIGNAL not_busy : STD_LOGIC; + SIGNAL oe_wire : STD_LOGIC; + SIGNAL page_size_wire : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL pagewr_buf_not_empty : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL rden_wire : STD_LOGIC; + SIGNAL rdid_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL reach_max_cnt : STD_LOGIC; + SIGNAL read_buf : STD_LOGIC; + SIGNAL read_bufdly : STD_LOGIC; + SIGNAL read_data_reg_in_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL read_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL read_rdid_wire : STD_LOGIC; + SIGNAL read_sid_wire : STD_LOGIC; + SIGNAL read_status_wire : STD_LOGIC; + SIGNAL read_wire : STD_LOGIC; + SIGNAL rsid_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL rsid_sdoin : STD_LOGIC; + SIGNAL rstat_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL scein_wire : STD_LOGIC; + SIGNAL sdoin_wire : STD_LOGIC; + SIGNAL sec_erase_wire : STD_LOGIC; + SIGNAL sec_protect_wire : STD_LOGIC; + SIGNAL secprot_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL secprot_sdoin : STD_LOGIC; + SIGNAL serase_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL shift_bytes_wire : STD_LOGIC; + SIGNAL shift_opcode : STD_LOGIC; + SIGNAL shift_opdata : STD_LOGIC; + SIGNAL shift_pgwr_data : STD_LOGIC; + SIGNAL st_busy_wire : STD_LOGIC; + SIGNAL stage2_wire : STD_LOGIC; + SIGNAL stage3_wire : STD_LOGIC; + SIGNAL stage4_wire : STD_LOGIC; + SIGNAL start_poll : STD_LOGIC; + SIGNAL start_sppoll : STD_LOGIC; + SIGNAL start_wrpoll : STD_LOGIC; + SIGNAL to_sdoin_wire : STD_LOGIC; + SIGNAL wren_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL wren_wire : STD_LOGIC; + SIGNAL write_opcode : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL write_prot_true : STD_LOGIC; + SIGNAL write_sdoin : STD_LOGIC; + SIGNAL write_wire : STD_LOGIC; + SIGNAL wire_w_addr_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_addr_range285w : STD_LOGIC_VECTOR (22 DOWNTO 0); + SIGNAL wire_w_b4addr_opcode_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_b4addr_opcode_range131w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_berase_opcode_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_berase_opcode_range139w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_dataout_wire_range327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_fast_read_opcode_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_fast_read_opcode_range157w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range414w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range418w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_pagewr_buf_not_empty_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rdid_opcode_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rdid_opcode_range168w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_read_opcode_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_read_opcode_range160w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_rsid_opcode_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rsid_opcode_range171w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_rstat_opcode_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_rstat_opcode_range149w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_secprot_opcode_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_secprot_opcode_range163w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_serase_opcode_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_serase_opcode_range144w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_wren_opcode_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_wren_opcode_range136w : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL wire_w_write_opcode_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_write_opcode_range152w : STD_LOGIC_VECTOR (6 DOWNTO 0); + COMPONENT a_graycounter + GENERIC + ( + PVALUE : NATURAL := 0; + WIDTH : NATURAL := 8; + lpm_type : STRING := "a_graycounter" + ); + PORT + ( + aclr : IN STD_LOGIC := '0'; + clk_en : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC; + cnt_en : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0); + qbin : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0); + sclr : IN STD_LOGIC := '0'; + updown : IN STD_LOGIC := '1' + ); + END COMPONENT; + COMPONENT lpm_compare + GENERIC + ( + LPM_PIPELINE : NATURAL := 0; + LPM_REPRESENTATION : STRING := "UNSIGNED"; + LPM_WIDTH : NATURAL; + lpm_hint : STRING := "UNUSED"; + lpm_type : STRING := "lpm_compare" + ); + PORT + ( + aclr : IN STD_LOGIC := '0'; + aeb : OUT STD_LOGIC; + agb : OUT STD_LOGIC; + ageb : OUT STD_LOGIC; + alb : OUT STD_LOGIC; + aleb : OUT STD_LOGIC; + aneb : OUT STD_LOGIC; + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '0'; + dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0') + ); + END COMPONENT; + COMPONENT lpm_counter + GENERIC + ( + lpm_avalue : STRING := "0"; + lpm_direction : STRING := "DEFAULT"; + lpm_modulus : NATURAL := 0; + lpm_port_updown : STRING := "PORT_CONNECTIVITY"; + lpm_pvalue : STRING := "0"; + lpm_svalue : STRING := "0"; + lpm_width : NATURAL; + lpm_type : STRING := "lpm_counter" + ); + PORT + ( + aclr : IN STD_LOGIC := '0'; + aload : IN STD_LOGIC := '0'; + aset : IN STD_LOGIC := '0'; + cin : IN STD_LOGIC := '1'; + clk_en : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC; + cnt_en : IN STD_LOGIC := '1'; + cout : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); + sclr : IN STD_LOGIC := '0'; + sload : IN STD_LOGIC := '0'; + sset : IN STD_LOGIC := '0'; + updown : IN STD_LOGIC := '1' + ); + END COMPONENT; + COMPONENT scfifo + GENERIC + ( + ADD_RAM_OUTPUT_REGISTER : STRING := "OFF"; + ALLOW_RWCYCLE_WHEN_FULL : STRING := "OFF"; + ALMOST_EMPTY_VALUE : NATURAL := 0; + ALMOST_FULL_VALUE : NATURAL := 0; + LPM_NUMWORDS : NATURAL; + LPM_SHOWAHEAD : STRING := "OFF"; + LPM_WIDTH : NATURAL; + LPM_WIDTHU : NATURAL := 1; + OVERFLOW_CHECKING : STRING := "ON"; + UNDERFLOW_CHECKING : STRING := "ON"; + USE_EAB : STRING := "ON"; + lpm_type : STRING := "scfifo" + ); + PORT + ( + aclr : IN STD_LOGIC := '0'; + almost_empty : OUT STD_LOGIC; + almost_full : OUT STD_LOGIC; + clock : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); + empty : OUT STD_LOGIC; + full : OUT STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); + rdreq : IN STD_LOGIC; + sclr : IN STD_LOGIC := '0'; + usedw : OUT STD_LOGIC_VECTOR(LPM_WIDTHU-1 DOWNTO 0); + wrreq : IN STD_LOGIC + ); + END COMPONENT; + COMPONENT stratixiv_asmiblock + PORT + ( + data0in : IN STD_LOGIC := '0'; + data0out : OUT STD_LOGIC; + dclkin : IN STD_LOGIC; + dclkout : OUT STD_LOGIC; + oe : IN STD_LOGIC := '0'; + scein : IN STD_LOGIC; + sceout : OUT STD_LOGIC; + sdoin : IN STD_LOGIC; + sdoout : OUT STD_LOGIC + ); + END COMPONENT; + BEGIN + + -- ASTRON, DS: + -- ========== + -- synthesis translate_off + u_M25P128: ENTITY work.M25P128 + GENERIC MAP( + MemoryFileName => "../../../tb/vhdl/m25p128_model/sim/memory_file", + TimingCheckOn => FALSE + ) + PORT MAP ( + VCC => 3.3, + C => clkin_wire, + D => sdoin_wire, + S => scein_wire, + W_Vpp => 9.0, + HOLD => '1', + Q => wire_stratixii_asmiblock2_data0out + ); + -- synthesis translate_on + + wire_w552w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_write394w549w550w551w(0) AND end_operation; + wire_w359w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_read312w356w357w358w(0) AND end_read_byte; + wire_w_lg_w_lg_w_lg_w_lg_load_opcode140w141w142w192w(0) <= wire_w_lg_w_lg_w_lg_load_opcode140w141w142w(0) AND wire_w_berase_opcode_range191w(0); + loop0 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_w_lg_load_opcode140w141w142w143w(i) <= wire_w_lg_w_lg_w_lg_load_opcode140w141w142w(0) AND wire_w_berase_opcode_range139w(i); + END GENERATE loop0; + wire_w_lg_w_lg_w_lg_w_lg_load_opcode145w146w147w194w(0) <= wire_w_lg_w_lg_w_lg_load_opcode145w146w147w(0) AND wire_w_serase_opcode_range193w(0); + loop1 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_w_lg_load_opcode145w146w147w148w(i) <= wire_w_lg_w_lg_w_lg_load_opcode145w146w147w(0) AND wire_w_serase_opcode_range144w(i); + END GENERATE loop1; + wire_w_lg_w_lg_w_lg_w_lg_load_opcode164w165w166w204w(0) <= wire_w_lg_w_lg_w_lg_load_opcode164w165w166w(0) AND wire_w_secprot_opcode_range203w(0); + loop2 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_w_lg_load_opcode164w165w166w167w(i) <= wire_w_lg_w_lg_w_lg_load_opcode164w165w166w(0) AND wire_w_secprot_opcode_range163w(i); + END GENERATE loop2; + wire_w_lg_w_lg_w_lg_w_lg_do_read256w257w258w259w(0) <= wire_w_lg_w_lg_w_lg_do_read256w257w258w(0) AND end_one_cycle; + wire_w_lg_w_lg_w_lg_w_lg_do_write394w549w550w551w(0) <= wire_w_lg_w_lg_w_lg_do_write394w549w550w(0) AND wire_w_lg_do_4baddr546w(0); + wire_w_lg_w554w555w(0) <= wire_w554w(0) AND end_operation; + wire_w_lg_w_lg_w_lg_w_lg_do_read312w356w357w358w(0) <= wire_w_lg_w_lg_w_lg_do_read312w356w357w(0) AND end_one_cyc_pos; + wire_w_lg_w_lg_w_lg_do_sec_erase300w301w302w(0) <= wire_w_lg_w_lg_do_sec_erase300w301w(0) AND end_operation; + wire_w_lg_w_lg_w_lg_load_opcode140w141w142w(0) <= wire_w_lg_w_lg_load_opcode140w141w(0) AND wire_w_lg_do_read_stat37w(0); + wire_w_lg_w_lg_w_lg_load_opcode145w146w147w(0) <= wire_w_lg_w_lg_load_opcode145w146w(0) AND wire_w_lg_do_read_stat37w(0); + wire_w_lg_w_lg_w_lg_load_opcode164w165w166w(0) <= wire_w_lg_w_lg_load_opcode164w165w(0) AND wire_w_lg_do_read_stat37w(0); + wire_w_lg_w_lg_w_lg_do_read256w257w258w(0) <= wire_w_lg_w_lg_do_read256w257w(0) AND wire_w_lg_w_lg_do_write47w254w(0); + wire_w_lg_w_lg_w_lg_do_read256w257w303w(0) <= wire_w_lg_w_lg_do_read256w257w(0) AND clr_write_wire; + wire_w_lg_w_lg_w_lg_do_write394w549w550w(0) <= wire_w_lg_w_lg_do_write394w549w(0) AND wire_w_lg_do_bulk_erase547w(0); + wire_w554w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_write56w57w460w553w(0) AND wire_wrstage_cntr_w_lg_w_q_range453w454w(0); + wire_w_lg_w_lg_w_lg_do_read312w356w357w(0) <= wire_w_lg_w_lg_do_read312w356w(0) AND wire_stage_cntr_w_lg_w_q_range80w85w(0); + wire_w_lg_w_lg_bp2_wire471w472w(0) <= wire_w_lg_bp2_wire471w(0) AND bp0_wire; + wire_w_lg_w_lg_do_4baddr132w133w(0) <= wire_w_lg_do_4baddr132w(0) AND wire_w_lg_do_wren38w(0); + wire_w_lg_w_lg_do_polling379w380w(0) <= wire_w_lg_do_polling379w(0) AND stage3_dly_reg; + wire_w_lg_w_lg_do_sec_erase300w301w(0) <= wire_w_lg_do_sec_erase300w(0) AND wire_w_lg_do_read_stat37w(0); + wire_w_lg_w_lg_do_write153w154w(0) <= wire_w_lg_do_write153w(0) AND wire_w_lg_do_wren38w(0); + wire_w_lg_w_lg_do_write47w235w(0) <= wire_w_lg_do_write47w(0) AND end_pgwr_data; + wire_w_lg_w_lg_load_opcode134w188w(0) <= wire_w_lg_load_opcode134w(0) AND wire_w_b4addr_opcode_range187w(0); + loop3 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode134w135w(i) <= wire_w_lg_load_opcode134w(0) AND wire_w_b4addr_opcode_range131w(i); + END GENERATE loop3; + wire_w_lg_w_lg_load_opcode155w198w(0) <= wire_w_lg_load_opcode155w(0) AND wire_w_write_opcode_range197w(0); + loop4 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode155w156w(i) <= wire_w_lg_load_opcode155w(0) AND wire_w_write_opcode_range152w(i); + END GENERATE loop4; + wire_w_lg_w_lg_load_opcode140w141w(0) <= wire_w_lg_load_opcode140w(0) AND wire_w_lg_do_wren38w(0); + wire_w_lg_w_lg_load_opcode158w200w(0) <= wire_w_lg_load_opcode158w(0) AND wire_w_fast_read_opcode_range199w(0); + loop5 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode158w159w(i) <= wire_w_lg_load_opcode158w(0) AND wire_w_fast_read_opcode_range157w(i); + END GENERATE loop5; + wire_w_lg_w_lg_load_opcode161w202w(0) <= wire_w_lg_load_opcode161w(0) AND wire_w_read_opcode_range201w(0); + loop6 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode161w162w(i) <= wire_w_lg_load_opcode161w(0) AND wire_w_read_opcode_range160w(i); + END GENERATE loop6; + wire_w_lg_w_lg_load_opcode169w206w(0) <= wire_w_lg_load_opcode169w(0) AND wire_w_rdid_opcode_range205w(0); + loop7 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode169w170w(i) <= wire_w_lg_load_opcode169w(0) AND wire_w_rdid_opcode_range168w(i); + END GENERATE loop7; + wire_w_lg_w_lg_load_opcode172w208w(0) <= wire_w_lg_load_opcode172w(0) AND wire_w_rsid_opcode_range207w(0); + loop8 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode172w173w(i) <= wire_w_lg_load_opcode172w(0) AND wire_w_rsid_opcode_range171w(i); + END GENERATE loop8; + wire_w_lg_w_lg_load_opcode150w196w(0) <= wire_w_lg_load_opcode150w(0) AND wire_w_rstat_opcode_range195w(0); + loop9 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode150w151w(i) <= wire_w_lg_load_opcode150w(0) AND wire_w_rstat_opcode_range149w(i); + END GENERATE loop9; + wire_w_lg_w_lg_load_opcode145w146w(0) <= wire_w_lg_load_opcode145w(0) AND wire_w_lg_do_wren38w(0); + wire_w_lg_w_lg_load_opcode164w165w(0) <= wire_w_lg_load_opcode164w(0) AND wire_w_lg_do_wren38w(0); + wire_w_lg_w_lg_load_opcode137w190w(0) <= wire_w_lg_load_opcode137w(0) AND wire_w_wren_opcode_range189w(0); + loop10 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_load_opcode137w138w(i) <= wire_w_lg_load_opcode137w(0) AND wire_w_wren_opcode_range136w(i); + END GENERATE loop10; + wire_w_lg_w_lg_reach_max_cnt445w446w(0) <= wire_w_lg_reach_max_cnt445w(0) AND wren_wire; + wire_w_lg_w_lg_start_poll241w242w(0) <= wire_w_lg_start_poll241w(0) AND do_polling; + wire_w_lg_w_lg_do_read256w257w(0) <= wire_w_lg_do_read256w(0) AND wire_w_lg_do_fast_read255w(0); + wire_w_lg_w_lg_do_write394w549w(0) <= wire_w_lg_do_write394w(0) AND wire_w_lg_do_sec_erase548w(0); + loop11 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_read_bufdly400w401w(i) <= wire_w_lg_read_bufdly400w(0) AND wire_pgwrbuf_dataout_w_q_range399w(i); + END GENERATE loop11; + wire_w451w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_write56w57w449w450w(0) AND end_wrstage; + wire_w_lg_w_lg_w_lg_w_lg_do_write56w57w460w553w(0) <= wire_w_lg_w_lg_w_lg_do_write56w57w460w(0) AND wire_wrstage_cntr_w_q_range455w(0); + wire_w_lg_w_lg_w_lg_do_write56w57w449w(0) <= wire_w_lg_w_lg_do_write56w57w(0) AND wire_w_lg_write_prot_true448w(0); + wire_w_lg_w_lg_w_lg_do_write56w57w58w(0) <= wire_w_lg_w_lg_do_write56w57w(0) AND write_prot_true; + wire_w_lg_w_lg_do_read312w356w(0) <= wire_w_lg_do_read312w(0) AND wire_stage_cntr_w_q_range81w(0); + wire_w_lg_w_lg_do_write56w293w(0) <= wire_w_lg_do_write56w(0) AND do_memadd; + wire_w_lg_w_lg_end_operation381w382w(0) <= wire_w_lg_end_operation381w(0) AND do_read_stat; + wire_w_lg_w_lg_rden_wire297w298w(0) <= wire_w_lg_rden_wire297w(0) AND not_busy; + wire_w_lg_bp2_wire471w(0) <= bp2_wire AND bp1_wire; + wire_w_lg_do_4baddr132w(0) <= do_4baddr AND wire_w_lg_do_read_stat37w(0); + wire_w_lg_do_bulk_erase236w(0) <= do_bulk_erase AND wire_w_lg_do_read_stat37w(0); + wire_w_lg_do_polling379w(0) <= do_polling AND end_one_cyc_pos; + wire_w_lg_do_sec_erase300w(0) <= do_sec_erase AND wire_w_lg_do_wren38w(0); + wire_w_lg_do_write153w(0) <= do_write AND wire_w_lg_do_read_stat37w(0); + wire_w_lg_do_write54w(0) <= do_write AND wire_w_lg_w_pagewr_buf_not_empty_range52w53w(0); + wire_w_lg_do_write47w(0) <= do_write AND shift_pgwr_data; + wire_w_lg_load_opcode134w(0) <= load_opcode AND wire_w_lg_w_lg_do_4baddr132w133w(0); + wire_w_lg_load_opcode155w(0) <= load_opcode AND wire_w_lg_w_lg_do_write153w154w(0); + wire_w_lg_load_opcode140w(0) <= load_opcode AND do_bulk_erase; + wire_w_lg_load_opcode158w(0) <= load_opcode AND do_fast_read; + wire_w_lg_load_opcode161w(0) <= load_opcode AND do_read; + wire_w_lg_load_opcode169w(0) <= load_opcode AND do_read_rdid; + wire_w_lg_load_opcode172w(0) <= load_opcode AND do_read_sid; + wire_w_lg_load_opcode150w(0) <= load_opcode AND do_read_stat; + wire_w_lg_load_opcode145w(0) <= load_opcode AND do_sec_erase; + wire_w_lg_load_opcode164w(0) <= load_opcode AND do_sec_prot; + wire_w_lg_load_opcode137w(0) <= load_opcode AND do_wren; + wire_w_lg_not_busy291w(0) <= not_busy AND wire_w_addr_range290w(0); + loop12 : FOR i IN 0 TO 22 GENERATE + wire_w_lg_not_busy286w(i) <= not_busy AND wire_w_addr_range285w(i); + END GENERATE loop12; + wire_w_lg_reach_max_cnt445w(0) <= reach_max_cnt AND shift_bytes_wire; + wire_w_lg_read_bufdly408w(0) <= read_bufdly AND wire_scfifo3_w_q_range407w(0); + loop13 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_read_bufdly403w(i) <= read_bufdly AND wire_scfifo3_w_q_range402w(i); + END GENERATE loop13; + loop14 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_shift_opcode130w(i) <= shift_opcode AND wire_asmi_opcode_reg_w_q_range129w(i); + END GENERATE loop14; + wire_w_lg_stage3_wire296w(0) <= stage3_wire AND wire_w_lg_w_lg_w_lg_w_lg_do_write56w293w294w295w(0); + wire_w_lg_stage3_wire323w(0) <= stage3_wire AND wire_w_lg_do_read_stat322w(0); + loop15 : FOR i IN 0 TO 22 GENERATE + wire_w_lg_stage3_wire284w(i) <= stage3_wire AND wire_addr_reg_w_q_range283w(i); + END GENERATE loop15; + wire_w_lg_stage4_wire325w(0) <= stage4_wire AND wire_w_lg_w_lg_do_read312w324w(0); + wire_w_lg_start_poll241w(0) <= start_poll AND do_read_stat; + wire_w_lg_w_lg_do_write47w254w(0) <= NOT wire_w_lg_do_write47w(0); + wire_w_lg_bp0_wire473w(0) <= NOT bp0_wire; + wire_w_lg_bp1_wire477w(0) <= NOT bp1_wire; + wire_w_lg_bp2_wire488w(0) <= NOT bp2_wire; + wire_w_lg_buf_empty518w(0) <= NOT buf_empty; + wire_w_lg_busy_wire1w(0) <= NOT busy_wire; + wire_w_lg_clkin_wire79w(0) <= NOT clkin_wire; + wire_w_lg_do_4baddr546w(0) <= NOT do_4baddr; + wire_w_lg_do_bulk_erase547w(0) <= NOT do_bulk_erase; + wire_w_lg_do_fast_read255w(0) <= NOT do_fast_read; + wire_w_lg_do_memadd309w(0) <= NOT do_memadd; + wire_w_lg_do_polling250w(0) <= NOT do_polling; + wire_w_lg_do_read256w(0) <= NOT do_read; + wire_w_lg_do_read_rdid36w(0) <= NOT do_read_rdid; + wire_w_lg_do_read_stat37w(0) <= NOT do_read_stat; + wire_w_lg_do_sec_erase548w(0) <= NOT do_sec_erase; + wire_w_lg_do_wren38w(0) <= NOT do_wren; + wire_w_lg_do_write394w(0) <= NOT do_write; + wire_w_lg_end_add_cycle66w(0) <= NOT end_add_cycle; + wire_w_lg_end_fast_read60w(0) <= NOT end_fast_read; + wire_w_lg_end_ophdly34w(0) <= NOT end_ophdly; + wire_w_lg_end_pgwr_data46w(0) <= NOT end_pgwr_data; + wire_w_lg_end_read63w(0) <= NOT end_read; + wire_w_lg_rden_wire371w(0) <= NOT rden_wire; + wire_w_lg_reach_max_cnt410w(0) <= NOT reach_max_cnt; + wire_w_lg_read_bufdly400w(0) <= NOT read_bufdly; + wire_w_lg_read_rdid_wire8w(0) <= NOT read_rdid_wire; + wire_w_lg_read_sid_wire7w(0) <= NOT read_sid_wire; + wire_w_lg_read_status_wire21w(0) <= NOT read_status_wire; + wire_w_lg_sec_protect_wire6w(0) <= NOT sec_protect_wire; + wire_w_lg_st_busy_wire94w(0) <= NOT st_busy_wire; + wire_w_lg_write_prot_true448w(0) <= NOT write_prot_true; + wire_w_lg_write_wire16w(0) <= NOT write_wire; + wire_w_lg_w_pagewr_buf_not_empty_range52w53w(0) <= NOT wire_w_pagewr_buf_not_empty_range52w(0); + wire_w_lg_w_lg_w554w555w556w(0) <= wire_w_lg_w554w555w(0) OR write_prot_true; + wire_w_lg_w_lg_w_lg_load_opcode172w208w209w(0) <= wire_w_lg_w_lg_load_opcode172w208w(0) OR wire_w_lg_w_lg_load_opcode169w206w(0); + loop16 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_load_opcode172w173w174w(i) <= wire_w_lg_w_lg_load_opcode172w173w(i) OR wire_w_lg_w_lg_load_opcode169w170w(i); + END GENERATE loop16; + wire_w_lg_w_lg_w_lg_w_lg_do_write56w57w449w450w(0) <= wire_w_lg_w_lg_w_lg_do_write56w57w449w(0) OR do_4baddr; + wire_w_lg_w_lg_w_lg_do_write56w293w294w(0) <= wire_w_lg_w_lg_do_write56w293w(0) OR do_read; + wire_w_lg_w_lg_w_lg_rden_wire297w298w299w(0) <= wire_w_lg_w_lg_rden_wire297w298w(0) OR wire_w_lg_stage3_wire296w(0); + loop17 : FOR i IN 0 TO 22 GENERATE + wire_w_lg_w_lg_not_busy286w287w(i) <= wire_w_lg_not_busy286w(i) OR wire_w_lg_stage3_wire284w(i); + END GENERATE loop17; + loop18 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_read_bufdly403w404w(i) <= wire_w_lg_read_bufdly403w(i) OR wire_w_lg_w_lg_read_bufdly400w401w(i); + END GENERATE loop18; + wire_w_lg_w_lg_stage4_wire325w326w(0) <= wire_w_lg_stage4_wire325w(0) OR wire_w_lg_stage3_wire323w(0); + wire_w_lg_w_lg_w_lg_w_lg_load_opcode172w208w209w210w(0) <= wire_w_lg_w_lg_w_lg_load_opcode172w208w209w(0) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode164w165w166w204w(0); + loop19 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_w_lg_load_opcode172w173w174w175w(i) <= wire_w_lg_w_lg_w_lg_load_opcode172w173w174w(i) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode164w165w166w167w(i); + END GENERATE loop19; + wire_w_lg_w_lg_w_lg_w_lg_do_write56w293w294w295w(0) <= wire_w_lg_w_lg_w_lg_do_write56w293w294w(0) OR do_fast_read; + wire_w211w(0) <= wire_w_lg_w_lg_w_lg_w_lg_load_opcode172w208w209w210w(0) OR wire_w_lg_w_lg_load_opcode161w202w(0); + loop20 : FOR i IN 0 TO 6 GENERATE + wire_w176w(i) <= wire_w_lg_w_lg_w_lg_w_lg_load_opcode172w173w174w175w(i) OR wire_w_lg_w_lg_load_opcode161w162w(i); + END GENERATE loop20; + wire_w_lg_w211w212w(0) <= wire_w211w(0) OR wire_w_lg_w_lg_load_opcode158w200w(0); + loop21 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w176w177w(i) <= wire_w176w(i) OR wire_w_lg_w_lg_load_opcode158w159w(i); + END GENERATE loop21; + wire_w_lg_w_lg_w211w212w213w(0) <= wire_w_lg_w211w212w(0) OR wire_w_lg_w_lg_load_opcode155w198w(0); + loop22 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w176w177w178w(i) <= wire_w_lg_w176w177w(i) OR wire_w_lg_w_lg_load_opcode155w156w(i); + END GENERATE loop22; + wire_w_lg_w_lg_w_lg_w211w212w213w214w(0) <= wire_w_lg_w_lg_w211w212w213w(0) OR wire_w_lg_w_lg_load_opcode150w196w(0); + loop23 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_w176w177w178w179w(i) <= wire_w_lg_w_lg_w176w177w178w(i) OR wire_w_lg_w_lg_load_opcode150w151w(i); + END GENERATE loop23; + wire_w_lg_w_lg_w_lg_w_lg_w211w212w213w214w215w(0) <= wire_w_lg_w_lg_w_lg_w211w212w213w214w(0) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode145w146w147w194w(0); + loop24 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_w_lg_w176w177w178w179w180w(i) <= wire_w_lg_w_lg_w_lg_w176w177w178w179w(i) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode145w146w147w148w(i); + END GENERATE loop24; + wire_w_lg_w_lg_w_lg_w_lg_w_lg_w211w212w213w214w215w216w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w211w212w213w214w215w(0) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode140w141w142w192w(0); + loop25 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w_lg_w_lg_w_lg_w176w177w178w179w180w181w(i) <= wire_w_lg_w_lg_w_lg_w_lg_w176w177w178w179w180w(i) OR wire_w_lg_w_lg_w_lg_w_lg_load_opcode140w141w142w143w(i); + END GENERATE loop25; + wire_w217w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w211w212w213w214w215w216w(0) OR wire_w_lg_w_lg_load_opcode137w190w(0); + loop26 : FOR i IN 0 TO 6 GENERATE + wire_w182w(i) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w176w177w178w179w180w181w(i) OR wire_w_lg_w_lg_load_opcode137w138w(i); + END GENERATE loop26; + wire_w_lg_w217w218w(0) <= wire_w217w(0) OR wire_w_lg_w_lg_load_opcode134w188w(0); + loop27 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w182w183w(i) <= wire_w182w(i) OR wire_w_lg_w_lg_load_opcode134w135w(i); + END GENERATE loop27; + loop28 : FOR i IN 0 TO 6 GENERATE + wire_w_lg_w_lg_w182w183w184w(i) <= wire_w_lg_w182w183w(i) OR wire_w_lg_shift_opcode130w(i); + END GENERATE loop28; + wire_w116w(0) <= wire_w_lg_w_lg_w_lg_w_lg_do_read_sid112w113w114w115w(0) OR do_read_rdid; + wire_w_lg_w_lg_w_lg_w_lg_do_read_sid112w113w114w115w(0) <= wire_w_lg_w_lg_w_lg_do_read_sid112w113w114w(0) OR do_sec_erase; + wire_w_lg_w_lg_w_lg_do_read312w313w314w(0) <= wire_w_lg_w_lg_do_read312w313w(0) OR do_sec_erase; + wire_w_lg_w_lg_w_lg_do_read_sid112w113w114w(0) <= wire_w_lg_w_lg_do_read_sid112w113w(0) OR do_write; + wire_w_lg_w_lg_w_lg_do_write56w57w460w(0) <= wire_w_lg_w_lg_do_write56w57w(0) OR do_4baddr; + wire_w_lg_w_lg_do_read312w324w(0) <= wire_w_lg_do_read312w(0) OR do_read_sid; + wire_w_lg_w_lg_do_read312w313w(0) <= wire_w_lg_do_read312w(0) OR do_write; + wire_w_lg_w_lg_do_read_sid112w113w(0) <= wire_w_lg_do_read_sid112w(0) OR do_fast_read; + wire_w_lg_w_lg_do_sec_erase462w463w(0) <= wire_w_lg_do_sec_erase462w(0) OR do_bulk_erase; + wire_w_lg_w_lg_do_write56w57w(0) <= wire_w_lg_do_write56w(0) OR do_bulk_erase; + wire_w_lg_data0out_wire328w(0) <= data0out_wire OR wire_w_dataout_wire_range327w(0); + wire_w_lg_do_4baddr237w(0) <= do_4baddr OR wire_w_lg_do_bulk_erase236w(0); + wire_w_lg_do_read312w(0) <= do_read OR do_fast_read; + wire_w_lg_do_read_sid112w(0) <= do_read_sid OR do_read; + wire_w_lg_do_read_stat322w(0) <= do_read_stat OR do_read_rdid; + wire_w_lg_do_sec_erase462w(0) <= do_sec_erase OR do_write; + wire_w_lg_do_wren238w(0) <= do_wren OR wire_w_lg_do_4baddr237w(0); + wire_w_lg_do_write56w(0) <= do_write OR do_sec_erase; + wire_w_lg_end_operation381w(0) <= end_operation OR wire_w_lg_w_lg_do_polling379w380w(0); + wire_w_lg_load_opcode220w(0) <= load_opcode OR shift_opcode; + wire_w_lg_rden_wire297w(0) <= rden_wire OR wren_wire; + wire_w_lg_read_bufdly398w(0) <= read_bufdly OR shift_pgwr_data; + wire_w_lg_w_pagewr_buf_not_empty_range414w417w(0) <= wire_w_pagewr_buf_not_empty_range414w(0) OR wire_pgwr_data_cntr_w_q_range416w(0); + wire_w_lg_w_pagewr_buf_not_empty_range418w420w(0) <= wire_w_pagewr_buf_not_empty_range418w(0) OR wire_pgwr_data_cntr_w_q_range419w(0); + wire_w_lg_w_pagewr_buf_not_empty_range421w423w(0) <= wire_w_pagewr_buf_not_empty_range421w(0) OR wire_pgwr_data_cntr_w_q_range422w(0); + wire_w_lg_w_pagewr_buf_not_empty_range424w426w(0) <= wire_w_pagewr_buf_not_empty_range424w(0) OR wire_pgwr_data_cntr_w_q_range425w(0); + wire_w_lg_w_pagewr_buf_not_empty_range427w429w(0) <= wire_w_pagewr_buf_not_empty_range427w(0) OR wire_pgwr_data_cntr_w_q_range428w(0); + wire_w_lg_w_pagewr_buf_not_empty_range430w432w(0) <= wire_w_pagewr_buf_not_empty_range430w(0) OR wire_pgwr_data_cntr_w_q_range431w(0); + wire_w_lg_w_pagewr_buf_not_empty_range433w435w(0) <= wire_w_pagewr_buf_not_empty_range433w(0) OR wire_pgwr_data_cntr_w_q_range434w(0); + wire_w_lg_w_pagewr_buf_not_empty_range436w438w(0) <= wire_w_pagewr_buf_not_empty_range436w(0) OR wire_pgwr_data_cntr_w_q_range437w(0); + b4addr_opcode <= (OTHERS => '0'); + be_write_prot <= (do_bulk_erase AND (((bp3_wire OR bp2_wire) OR bp1_wire) OR bp0_wire)); + berase_opcode <= (OTHERS => '0'); + bp0_wire <= statreg_int(2); + bp1_wire <= statreg_int(3); + bp2_wire <= statreg_int(4); + bp3_wire <= statreg_int(6); + buf_empty <= buf_empty_reg; + busy <= busy_wire; + busy_wire <= (((((((((do_read_rdid OR do_read_sid) OR do_read) OR do_fast_read) OR do_write) OR do_sec_prot) OR do_read_stat) OR do_sec_erase) OR do_bulk_erase) OR do_4baddr); + clkin_wire <= clkin; + clr_read_wire <= clr_read_reg2; + clr_rstat_wire <= clr_rstat_reg2; + clr_write_wire <= clr_write_reg2; + cnt_bfend_wire_in <= (wire_gen_cntr_w_lg_w_q_range91w92w(0) AND wire_gen_cntr_q(0)); + data0out_wire <= wire_stratixii_asmiblock2_data0out; + data_valid <= data_valid_wire; + data_valid_wire <= dvalid_reg2; + dataout <= ( read_data_reg(7 DOWNTO 0)); + dataout_wire <= ( "0000"); + do_4baddr <= '0'; + do_bulk_erase <= '0'; + do_fast_read <= '0'; + do_memadd <= do_wrmemadd_reg; + do_polling <= (do_write_polling OR do_sprot_polling); + do_read <= (((wire_w_lg_read_rdid_wire8w(0) AND wire_w_lg_read_sid_wire7w(0)) AND wire_w_lg_sec_protect_wire6w(0)) AND read_wire); + do_read_rdid <= '0'; + do_read_sid <= '0'; + do_read_stat <= (((((((wire_w_lg_read_rdid_wire8w(0) AND wire_w_lg_read_sid_wire7w(0)) AND wire_w_lg_sec_protect_wire6w(0)) AND (NOT (read_wire OR fast_read_wire))) AND wire_w_lg_write_wire16w(0)) AND read_status_wire) OR do_write_rstat) OR do_sprot_rstat); + do_sec_erase <= ((((((wire_w_lg_read_rdid_wire8w(0) AND wire_w_lg_read_sid_wire7w(0)) AND wire_w_lg_sec_protect_wire6w(0)) AND (NOT (read_wire OR fast_read_wire))) AND wire_w_lg_write_wire16w(0)) AND wire_w_lg_read_status_wire21w(0)) AND sec_erase_wire); + do_sec_prot <= '0'; + do_secprot_wren <= '0'; + do_sprot_polling <= '0'; + do_sprot_rstat <= '0'; + do_wren <= (do_write_wren OR do_secprot_wren); + do_write <= ((((wire_w_lg_read_rdid_wire8w(0) AND wire_w_lg_read_sid_wire7w(0)) AND wire_w_lg_sec_protect_wire6w(0)) AND (NOT (read_wire OR fast_read_wire))) AND write_wire); + do_write_polling <= ((wire_w_lg_w_lg_do_write56w57w(0) AND wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_w_lg_w_q_range453w454w(0)); + do_write_rstat <= write_rstat_reg; + do_write_wren <= ((NOT wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_q(0)); + dummy_read_buf <= maxcnt_shift_reg2; + end1_cyc_gen_cntr_wire <= (wire_gen_cntr_w_lg_w_q_range91w92w(0) AND (NOT wire_gen_cntr_q(0))); + end1_cyc_normal_in_wire <= (((((((((wire_stage_cntr_w_lg_w_lg_w_q_range80w85w99w(0) AND (NOT wire_gen_cntr_q(2))) AND wire_gen_cntr_q(1)) AND wire_gen_cntr_q(0)) OR wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range80w85w99w100w101w(0)) OR (do_read AND end_read)) OR (do_fast_read AND end_fast_read)) OR wire_w_lg_w_lg_w_lg_do_write56w57w58w(0)) OR wire_w_lg_do_write54w(0)) OR ((do_read_stat AND start_poll) AND wire_w_lg_st_busy_wire94w(0))); + end1_cyc_reg_in_wire <= end1_cyc_normal_in_wire; + end_add_cycle <= wire_mux211_dataout; + end_add_cycle_mux_datab_wire <= (wire_addbyte_cntr_q(2) AND wire_addbyte_cntr_q(1)); + end_fast_read <= end_read_reg; + end_one_cyc_pos <= end1_cyc_reg2; + end_one_cycle <= end1_cyc_reg; + end_operation <= end_op_reg; + end_ophdly <= end_op_hdlyreg; + end_pgwr_data <= end_pgwrop_reg; + end_read <= end_read_reg; + end_read_byte <= end_rbyte_reg; + end_wrstage <= end_operation; + fast_read_opcode <= (OTHERS => '0'); + fast_read_wire <= '0'; + ill_erase_wire <= ill_erase_reg; + ill_write_wire <= ill_write_reg; + illegal_erase <= ill_erase_wire; + illegal_erase_b4out_wire <= ((do_sec_erase OR do_bulk_erase) AND write_prot_true); + illegal_write <= ill_write_wire; + illegal_write_b4out_wire <= ((do_write AND write_prot_true) OR wire_w_lg_do_write54w(0)); + in_operation <= busy_wire; + load_opcode <= ((((wire_stage_cntr_w_lg_w_q_range81w82w(0) AND wire_stage_cntr_w_lg_w_q_range80w85w(0)) AND (NOT wire_gen_cntr_q(2))) AND wire_gen_cntr_w_lg_w_q_range89w90w(0)) AND wire_gen_cntr_q(0)); + memadd_sdoin <= add_msb_reg; + not_busy <= busy_det_reg; + oe_wire <= '0'; + page_size_wire <= "100000000"; + pagewr_buf_not_empty <= ( wire_w_lg_w_pagewr_buf_not_empty_range436w438w & wire_w_lg_w_pagewr_buf_not_empty_range433w435w & wire_w_lg_w_pagewr_buf_not_empty_range430w432w & wire_w_lg_w_pagewr_buf_not_empty_range427w429w & wire_w_lg_w_pagewr_buf_not_empty_range424w426w & wire_w_lg_w_pagewr_buf_not_empty_range421w423w & wire_w_lg_w_pagewr_buf_not_empty_range418w420w & wire_w_lg_w_pagewr_buf_not_empty_range414w417w & wire_pgwr_data_cntr_q(0)); + rden_wire <= rden; + rdid_opcode <= (OTHERS => '0'); + reach_max_cnt <= max_cnt_reg; + read_buf <= (((((end_one_cycle AND do_write) AND wire_w_lg_do_read_stat37w(0)) AND wire_w_lg_do_wren38w(0)) AND (wire_stage_cntr_w_lg_w_q_range81w86w(0) OR wire_addbyte_cntr_w_lg_w_q_range119w124w(0))) AND wire_w_lg_buf_empty518w(0)); + read_bufdly <= read_bufdly_reg; + read_data_reg_in_wire <= ( read_dout_reg(7 DOWNTO 0)); + read_opcode <= "00000011"; + read_rdid_wire <= '0'; + read_sid_wire <= '0'; + read_status_wire <= '0'; + read_wire <= read_reg; + rsid_opcode <= (OTHERS => '0'); + rsid_sdoin <= '0'; + rstat_opcode <= "00000101"; + scein_wire <= wire_ncs_reg_w_lg_q273w(0); + sdoin_wire <= to_sdoin_wire; + sec_erase_wire <= sec_erase_reg; + sec_protect_wire <= '0'; + secprot_opcode <= (OTHERS => '0'); + secprot_sdoin <= '0'; + serase_opcode <= "11011000"; + shift_bytes_wire <= shift_bytes; + shift_opcode <= shift_op_reg; + shift_opdata <= stage2_wire; + shift_pgwr_data <= shftpgwr_data_reg; + st_busy_wire <= statreg_int(0); + stage2_wire <= stage2_reg; + stage3_wire <= stage3_reg; + stage4_wire <= stage4_reg; + start_poll <= (start_wrpoll OR start_sppoll); + start_sppoll <= '0'; + start_wrpoll <= start_wrpoll_reg2; + to_sdoin_wire <= (((((shift_opdata AND asmi_opcode_reg(7)) OR rsid_sdoin) OR memadd_sdoin) OR write_sdoin) OR secprot_sdoin); + wren_opcode <= "00000110"; + wren_wire <= wren; + write_opcode <= "00000010"; + write_prot_true <= write_prot_reg; + write_sdoin <= ((((do_write AND stage4_wire) AND wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_q(0)) AND pgwrbuf_dataout(7)); + write_wire <= write_reg; + wire_w_addr_range290w(0) <= addr(0); + wire_w_addr_range285w <= addr(23 DOWNTO 1); + wire_w_b4addr_opcode_range187w(0) <= b4addr_opcode(0); + wire_w_b4addr_opcode_range131w <= b4addr_opcode(7 DOWNTO 1); + wire_w_berase_opcode_range191w(0) <= berase_opcode(0); + wire_w_berase_opcode_range139w <= berase_opcode(7 DOWNTO 1); + wire_w_dataout_wire_range327w(0) <= dataout_wire(1); + wire_w_fast_read_opcode_range199w(0) <= fast_read_opcode(0); + wire_w_fast_read_opcode_range157w <= fast_read_opcode(7 DOWNTO 1); + wire_w_pagewr_buf_not_empty_range414w(0) <= pagewr_buf_not_empty(0); + wire_w_pagewr_buf_not_empty_range418w(0) <= pagewr_buf_not_empty(1); + wire_w_pagewr_buf_not_empty_range421w(0) <= pagewr_buf_not_empty(2); + wire_w_pagewr_buf_not_empty_range424w(0) <= pagewr_buf_not_empty(3); + wire_w_pagewr_buf_not_empty_range427w(0) <= pagewr_buf_not_empty(4); + wire_w_pagewr_buf_not_empty_range430w(0) <= pagewr_buf_not_empty(5); + wire_w_pagewr_buf_not_empty_range433w(0) <= pagewr_buf_not_empty(6); + wire_w_pagewr_buf_not_empty_range436w(0) <= pagewr_buf_not_empty(7); + wire_w_pagewr_buf_not_empty_range52w(0) <= pagewr_buf_not_empty(8); + wire_w_rdid_opcode_range205w(0) <= rdid_opcode(0); + wire_w_rdid_opcode_range168w <= rdid_opcode(7 DOWNTO 1); + wire_w_read_opcode_range201w(0) <= read_opcode(0); + wire_w_read_opcode_range160w <= read_opcode(7 DOWNTO 1); + wire_w_rsid_opcode_range207w(0) <= rsid_opcode(0); + wire_w_rsid_opcode_range171w <= rsid_opcode(7 DOWNTO 1); + wire_w_rstat_opcode_range195w(0) <= rstat_opcode(0); + wire_w_rstat_opcode_range149w <= rstat_opcode(7 DOWNTO 1); + wire_w_secprot_opcode_range203w(0) <= secprot_opcode(0); + wire_w_secprot_opcode_range163w <= secprot_opcode(7 DOWNTO 1); + wire_w_serase_opcode_range193w(0) <= serase_opcode(0); + wire_w_serase_opcode_range144w <= serase_opcode(7 DOWNTO 1); + wire_w_wren_opcode_range189w(0) <= wren_opcode(0); + wire_w_wren_opcode_range136w <= wren_opcode(7 DOWNTO 1); + wire_w_write_opcode_range197w(0) <= write_opcode(0); + wire_w_write_opcode_range152w <= write_opcode(7 DOWNTO 1); + wire_addbyte_cntr_w_lg_w_q_range119w124w(0) <= wire_addbyte_cntr_w_q_range119w(0) AND wire_addbyte_cntr_w_lg_w_q_range122w123w(0); + wire_addbyte_cntr_w_lg_w_q_range122w123w(0) <= NOT wire_addbyte_cntr_w_q_range122w(0); + wire_addbyte_cntr_clk_en <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w117w118w(0); + wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w117w118w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range81w84w117w(0) AND wire_w116w(0); + wire_addbyte_cntr_clock <= wire_w_lg_clkin_wire79w(0); + wire_addbyte_cntr_w_q_range122w(0) <= wire_addbyte_cntr_q(0); + wire_addbyte_cntr_w_q_range119w(0) <= wire_addbyte_cntr_q(1); + addbyte_cntr : a_graycounter + GENERIC MAP ( + WIDTH => 3 + ) + PORT MAP ( + aclr => end_operation, + clk_en => wire_addbyte_cntr_clk_en, + clock => wire_addbyte_cntr_clock, + q => wire_addbyte_cntr_q + ); + wire_gen_cntr_w_lg_w_q_range91w92w(0) <= wire_gen_cntr_w_q_range91w(0) AND wire_gen_cntr_w_lg_w_q_range89w90w(0); + wire_gen_cntr_w_lg_w_q_range89w90w(0) <= NOT wire_gen_cntr_w_q_range89w(0); + wire_gen_cntr_clk_en <= wire_w_lg_in_operation35w(0); + wire_w_lg_in_operation35w(0) <= in_operation AND wire_w_lg_end_ophdly34w(0); + wire_gen_cntr_w_q_range89w(0) <= wire_gen_cntr_q(1); + wire_gen_cntr_w_q_range91w(0) <= wire_gen_cntr_q(2); + gen_cntr : a_graycounter + GENERIC MAP ( + WIDTH => 3 + ) + PORT MAP ( + aclr => end_one_cycle, + clk_en => wire_gen_cntr_clk_en, + clock => clkin_wire, + q => wire_gen_cntr_q + ); + wire_stage_cntr_w_lg_w229w230w(0) <= wire_stage_cntr_w229w(0) AND end_one_cycle; + wire_stage_cntr_w229w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w84w226w227w228w(0) AND end_add_cycle; + wire_stage_cntr_w234w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w84w231w232w233w(0) AND end_one_cycle; + wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w84w226w227w228w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w226w227w(0) AND wire_w_lg_do_read_stat37w(0); + wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w84w231w232w233w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w231w232w(0) AND wire_w_lg_do_read_stat37w(0); + wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w82w83w239w240w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w82w83w239w(0) AND end_one_cycle; + wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w86w304w305w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range81w86w304w(0) AND end_one_cyc_pos; + wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w251w252w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range81w84w251w(0) AND end_one_cycle; + wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w226w227w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range81w84w226w(0) AND wire_w_lg_do_wren38w(0); + wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w231w232w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range81w84w231w(0) AND wire_w_lg_do_wren38w(0); + wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w82w83w239w(0) <= wire_stage_cntr_w_lg_w_lg_w_q_range81w82w83w(0) AND wire_w_lg_do_wren238w(0); + wire_stage_cntr_w_lg_w_lg_w_q_range81w86w304w(0) <= wire_stage_cntr_w_lg_w_q_range81w86w(0) AND end_add_cycle; + wire_stage_cntr_w_lg_w_lg_w_q_range81w84w251w(0) <= wire_stage_cntr_w_lg_w_q_range81w84w(0) AND do_read_stat; + wire_stage_cntr_w_lg_w_lg_w_q_range81w84w226w(0) <= wire_stage_cntr_w_lg_w_q_range81w84w(0) AND do_sec_erase; + wire_stage_cntr_w_lg_w_lg_w_q_range81w84w231w(0) <= wire_stage_cntr_w_lg_w_q_range81w84w(0) AND do_sec_prot; + wire_stage_cntr_w_lg_w_lg_w_q_range81w84w117w(0) <= wire_stage_cntr_w_lg_w_q_range81w84w(0) AND end_one_cyc_pos; + wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range80w85w99w100w101w(0) <= wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range80w85w99w100w(0) AND end1_cyc_gen_cntr_wire; + wire_stage_cntr_w_lg_w_lg_w_q_range80w85w99w(0) <= wire_stage_cntr_w_lg_w_q_range80w85w(0) AND wire_stage_cntr_w_lg_w_q_range81w82w(0); + wire_stage_cntr_w_lg_w_lg_w_q_range81w82w83w(0) <= wire_stage_cntr_w_lg_w_q_range81w82w(0) AND wire_stage_cntr_w_q_range80w(0); + wire_stage_cntr_w_lg_w_q_range81w86w(0) <= wire_stage_cntr_w_q_range81w(0) AND wire_stage_cntr_w_lg_w_q_range80w85w(0); + wire_stage_cntr_w_lg_w_q_range81w84w(0) <= wire_stage_cntr_w_q_range81w(0) AND wire_stage_cntr_w_q_range80w(0); + wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range80w85w99w100w(0) <= NOT wire_stage_cntr_w_lg_w_lg_w_q_range80w85w99w(0); + wire_stage_cntr_w_lg_w_q_range80w85w(0) <= NOT wire_stage_cntr_w_q_range80w(0); + wire_stage_cntr_w_lg_w_q_range81w82w(0) <= NOT wire_stage_cntr_w_q_range81w(0); + wire_stage_cntr_clk_en <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w73w74w75w76w77w78w(0); + wire_w_lg_w_lg_w_lg_w_lg_w_lg_w73w74w75w76w77w78w(0) <= (((((((((in_operation AND end_one_cycle) AND (NOT (stage3_wire AND wire_w_lg_end_add_cycle66w(0)))) AND (NOT (stage4_wire AND wire_w_lg_end_read63w(0)))) AND (NOT (stage4_wire AND wire_w_lg_end_fast_read60w(0)))) AND (NOT wire_w_lg_w_lg_w_lg_do_write56w57w58w(0))) AND (NOT wire_w_lg_do_write54w(0))) AND (NOT (stage3_wire AND st_busy_wire))) AND (NOT (wire_w_lg_do_write47w(0) AND wire_w_lg_end_pgwr_data46w(0)))) AND (NOT (stage2_wire AND do_wren))) AND (NOT ((((stage3_wire AND do_sec_erase) AND wire_w_lg_do_wren38w(0)) AND wire_w_lg_do_read_stat37w(0)) AND wire_w_lg_do_read_rdid36w(0))); + wire_stage_cntr_w_q_range80w(0) <= wire_stage_cntr_q(0); + wire_stage_cntr_w_q_range81w(0) <= wire_stage_cntr_q(1); + stage_cntr : a_graycounter + GENERIC MAP ( + WIDTH => 2 + ) + PORT MAP ( + aclr => end_ophdly, + clk_en => wire_stage_cntr_clk_en, + clock => clkin_wire, + q => wire_stage_cntr_q + ); + wire_wrstage_cntr_w_lg_w_q_range455w456w(0) <= wire_wrstage_cntr_w_q_range455w(0) AND wire_wrstage_cntr_w_lg_w_q_range453w454w(0); + wire_wrstage_cntr_w_lg_w_q_range453w454w(0) <= NOT wire_wrstage_cntr_w_q_range453w(0); + wire_wrstage_cntr_clk_en <= wire_w_lg_w451w452w(0); + wire_w_lg_w451w452w(0) <= wire_w451w(0) AND wire_w_lg_st_busy_wire94w(0); + wire_wrstage_cntr_clock <= wire_w_lg_clkin_wire79w(0); + wire_wrstage_cntr_w_q_range453w(0) <= wire_wrstage_cntr_q(0); + wire_wrstage_cntr_w_q_range455w(0) <= wire_wrstage_cntr_q(1); + wrstage_cntr : a_graycounter + GENERIC MAP ( + WIDTH => 2 + ) + PORT MAP ( + aclr => clr_write_wire, + clk_en => wire_wrstage_cntr_clk_en, + clock => wire_wrstage_cntr_clock, + q => wire_wrstage_cntr_q + ); + PROCESS (clkin_wire, clr_addmsb_reg) + BEGIN + IF (clr_addmsb_reg = '1') THEN add_msb_reg <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_add_msb_reg_ena = '1') THEN add_msb_reg <= wire_addr_reg_w_q_range308w(0); + END IF; + END IF; + END PROCESS; + wire_add_msb_reg_ena <= (((wire_w_lg_w_lg_w_lg_do_read312w313w314w(0) AND (NOT (wire_w_lg_do_write56w(0) AND wire_w_lg_do_memadd309w(0)))) AND wire_stage_cntr_q(1)) AND wire_stage_cntr_q(0)); + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(0) = '1') THEN addr_reg(0) <= wire_addr_reg_d(0); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(1) = '1') THEN addr_reg(1) <= wire_addr_reg_d(1); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(2) = '1') THEN addr_reg(2) <= wire_addr_reg_d(2); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(3) = '1') THEN addr_reg(3) <= wire_addr_reg_d(3); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(4) = '1') THEN addr_reg(4) <= wire_addr_reg_d(4); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(5) = '1') THEN addr_reg(5) <= wire_addr_reg_d(5); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(6) = '1') THEN addr_reg(6) <= wire_addr_reg_d(6); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(7) = '1') THEN addr_reg(7) <= wire_addr_reg_d(7); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(8) = '1') THEN addr_reg(8) <= wire_addr_reg_d(8); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(9) = '1') THEN addr_reg(9) <= wire_addr_reg_d(9); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(10) = '1') THEN addr_reg(10) <= wire_addr_reg_d(10); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(11) = '1') THEN addr_reg(11) <= wire_addr_reg_d(11); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(12) = '1') THEN addr_reg(12) <= wire_addr_reg_d(12); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(13) = '1') THEN addr_reg(13) <= wire_addr_reg_d(13); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(14) = '1') THEN addr_reg(14) <= wire_addr_reg_d(14); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(15) = '1') THEN addr_reg(15) <= wire_addr_reg_d(15); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(16) = '1') THEN addr_reg(16) <= wire_addr_reg_d(16); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(17) = '1') THEN addr_reg(17) <= wire_addr_reg_d(17); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(18) = '1') THEN addr_reg(18) <= wire_addr_reg_d(18); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(19) = '1') THEN addr_reg(19) <= wire_addr_reg_d(19); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(20) = '1') THEN addr_reg(20) <= wire_addr_reg_d(20); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(21) = '1') THEN addr_reg(21) <= wire_addr_reg_d(21); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(22) = '1') THEN addr_reg(22) <= wire_addr_reg_d(22); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_addr_reg_ena(23) = '1') THEN addr_reg(23) <= wire_addr_reg_d(23); + END IF; + END IF; + END PROCESS; + wire_addr_reg_d <= ( wire_w_lg_w_lg_not_busy286w287w & wire_w_lg_not_busy291w); + loop29 : FOR i IN 0 TO 23 GENERATE + wire_addr_reg_ena(i) <= wire_w_lg_w_lg_w_lg_rden_wire297w298w299w(0); + END GENERATE loop29; + wire_addr_reg_w_lg_w_lg_w_lg_w500w501w502w503w(0) <= wire_addr_reg_w_lg_w_lg_w500w501w502w(0) AND bp0_wire; + wire_addr_reg_w_lg_w_lg_w500w501w502w(0) <= wire_addr_reg_w_lg_w500w501w(0) AND wire_w_lg_bp1_wire477w(0); + wire_addr_reg_w_lg_w492w493w(0) <= wire_addr_reg_w492w(0) AND bp0_wire; + wire_addr_reg_w_lg_w496w497w(0) <= wire_addr_reg_w496w(0) AND bp1_wire; + wire_addr_reg_w_lg_w500w501w(0) <= wire_addr_reg_w500w(0) AND wire_w_lg_bp2_wire488w(0); + wire_addr_reg_w492w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w491w(0) AND bp1_wire; + wire_addr_reg_w496w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w495w(0) AND wire_w_lg_bp2_wire488w(0); + wire_addr_reg_w500w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w495w(0) AND wire_addr_reg_w_q_range499w(0); + wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w480w481w482w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w480w481w(0) AND bp0_wire; + wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w491w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w(0) AND wire_w_lg_bp2_wire488w(0); + wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w495w(0) <= wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w(0) AND wire_addr_reg_w_q_range494w(0); + wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w480w481w(0) <= wire_addr_reg_w_lg_w_lg_w_q_range308w479w480w(0) AND wire_w_lg_bp1_wire477w(0); + wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w484w485w(0) <= wire_addr_reg_w_lg_w_lg_w_q_range308w479w484w(0) AND bp2_wire; + wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w484w490w(0) <= wire_addr_reg_w_lg_w_lg_w_q_range308w479w484w(0) AND wire_addr_reg_w_q_range489w(0); + wire_addr_reg_w_lg_w_lg_w_q_range308w474w475w(0) <= wire_addr_reg_w_lg_w_q_range308w474w(0) AND bp1_wire; + wire_addr_reg_w_lg_w_lg_w_q_range308w479w480w(0) <= wire_addr_reg_w_lg_w_q_range308w479w(0) AND bp2_wire; + wire_addr_reg_w_lg_w_lg_w_q_range308w479w484w(0) <= wire_addr_reg_w_lg_w_q_range308w479w(0) AND wire_addr_reg_w_q_range483w(0); + wire_addr_reg_w_lg_w_q_range308w474w(0) <= wire_addr_reg_w_q_range308w(0) AND bp2_wire; + wire_addr_reg_w_lg_w_q_range308w479w(0) <= wire_addr_reg_w_q_range308w(0) AND wire_addr_reg_w_q_range478w(0); + wire_addr_reg_w_q_range499w(0) <= addr_reg(18); + wire_addr_reg_w_q_range494w(0) <= addr_reg(19); + wire_addr_reg_w_q_range489w(0) <= addr_reg(20); + wire_addr_reg_w_q_range483w(0) <= addr_reg(21); + wire_addr_reg_w_q_range283w <= addr_reg(22 DOWNTO 0); + wire_addr_reg_w_q_range478w(0) <= addr_reg(22); + wire_addr_reg_w_q_range308w(0) <= addr_reg(23); + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(0) = '1') THEN asmi_opcode_reg(0) <= wire_asmi_opcode_reg_d(0); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(1) = '1') THEN asmi_opcode_reg(1) <= wire_asmi_opcode_reg_d(1); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(2) = '1') THEN asmi_opcode_reg(2) <= wire_asmi_opcode_reg_d(2); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(3) = '1') THEN asmi_opcode_reg(3) <= wire_asmi_opcode_reg_d(3); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(4) = '1') THEN asmi_opcode_reg(4) <= wire_asmi_opcode_reg_d(4); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(5) = '1') THEN asmi_opcode_reg(5) <= wire_asmi_opcode_reg_d(5); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(6) = '1') THEN asmi_opcode_reg(6) <= wire_asmi_opcode_reg_d(6); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_asmi_opcode_reg_ena(7) = '1') THEN asmi_opcode_reg(7) <= wire_asmi_opcode_reg_d(7); + END IF; + END IF; + END PROCESS; + wire_asmi_opcode_reg_d <= ( wire_w_lg_w_lg_w182w183w184w & wire_w_lg_w217w218w); + loop30 : FOR i IN 0 TO 7 GENERATE + wire_asmi_opcode_reg_ena(i) <= wire_w_lg_load_opcode220w(0); + END GENERATE loop30; + wire_asmi_opcode_reg_w_q_range129w <= asmi_opcode_reg(6 DOWNTO 0); + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN buf_empty_reg <= wire_cmpr5_aeb; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN busy_det_reg <= wire_w_lg_busy_wire1w(0); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_addmsb_reg <= ((wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w86w304w305w(0) OR wire_w_lg_w_lg_w_lg_do_read256w257w303w(0)) OR wire_w_lg_w_lg_w_lg_do_sec_erase300w301w302w(0)); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN clr_endrbyte_reg <= ((((wire_w_lg_do_read312w(0) AND (NOT wire_gen_cntr_q(2))) AND wire_gen_cntr_q(1)) AND wire_gen_cntr_q(0)) OR clr_read_wire); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_read_reg <= ((end_operation OR do_read_sid) OR do_sec_prot); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_read_reg2 <= clr_read_reg; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_rstat_reg <= ((end_operation OR do_read_sid) OR do_read); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_rstat_reg2 <= clr_rstat_reg; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_write_reg <= ((((((wire_w_lg_w_lg_w554w555w556w(0) OR wire_w_lg_do_write54w(0)) OR wire_w552w(0)) OR do_read_sid) OR do_sec_prot) OR do_read) OR do_fast_read); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN clr_write_reg2 <= clr_write_reg; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN cnt_bfend_reg <= cnt_bfend_wire_in; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN do_wrmemadd_reg <= (wire_wrstage_cntr_q(1) AND wire_wrstage_cntr_q(0)); + END IF; + END PROCESS; + PROCESS (clkin_wire, end_operation) + BEGIN + IF (end_operation = '1') THEN dvalid_reg <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_dvalid_reg_ena = '1') THEN dvalid_reg <= (end_read_byte AND end_one_cyc_pos); + END IF; + END IF; + END PROCESS; + wire_dvalid_reg_ena <= wire_w_lg_do_read312w(0); + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN dvalid_reg2 <= dvalid_reg; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN end1_cyc_reg <= end1_cyc_reg_in_wire; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN end1_cyc_reg2 <= end_one_cycle; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN end_op_hdlyreg <= end_operation; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN end_op_reg <= ((((((((((wire_stage_cntr_w_lg_w_q_range81w86w(0) AND ((wire_w_lg_w_lg_w_lg_w_lg_do_read256w257w258w259w(0) OR (do_read AND end_read)) OR (do_fast_read AND end_fast_read))) OR (wire_stage_cntr_w_lg_w_lg_w_lg_w_q_range81w84w251w252w(0) AND wire_w_lg_do_polling250w(0))) OR ((((((do_read_rdid AND end_one_cycle) AND wire_stage_cntr_q(1)) AND wire_stage_cntr_q(0)) AND wire_addbyte_cntr_q(2)) AND wire_addbyte_cntr_q(1)) AND wire_addbyte_cntr_q(0))) OR (wire_w_lg_w_lg_start_poll241w242w(0) AND wire_w_lg_st_busy_wire94w(0))) OR wire_stage_cntr_w_lg_w_lg_w_lg_w_lg_w_q_range81w82w83w239w240w(0)) OR wire_w_lg_w_lg_w_lg_do_write56w57w58w(0)) OR wire_w_lg_w_lg_do_write47w235w(0)) OR wire_w_lg_do_write54w(0)) OR wire_stage_cntr_w234w(0)) OR wire_stage_cntr_w_lg_w229w230w(0)); + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN end_pgwrop_reg <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_end_pgwrop_reg_ena = '1') THEN end_pgwrop_reg <= buf_empty; + END IF; + END IF; + END PROCESS; + wire_end_pgwrop_reg_ena <= ((cnt_bfend_reg AND do_write) AND shift_pgwr_data); + PROCESS (clkin_wire, clr_endrbyte_reg) + BEGIN + IF (clr_endrbyte_reg = '1') THEN end_rbyte_reg <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_end_rbyte_reg_ena = '1') THEN end_rbyte_reg <= wire_w_lg_w_lg_w_lg_do_read312w356w357w(0); + END IF; + END IF; + END PROCESS; + wire_end_rbyte_reg_ena <= (wire_gen_cntr_w_lg_w_q_range91w92w(0) AND wire_gen_cntr_q(0)); + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN end_read_reg <= (((wire_w_lg_rden_wire371w(0) AND wire_w_lg_do_read312w(0)) AND data_valid_wire) AND end_read_byte); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN ill_erase_reg <= illegal_erase_b4out_wire; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN ill_write_reg <= illegal_write_b4out_wire; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN max_cnt_reg <= wire_cmpr4_aeb; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN maxcnt_shift_reg <= (wire_w_lg_w_lg_reach_max_cnt445w446w(0) AND wire_w_lg_do_write394w(0)); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN maxcnt_shift_reg2 <= maxcnt_shift_reg; + END IF; + END PROCESS; + PROCESS (clkin_wire, end_ophdly) + BEGIN + IF (end_ophdly = '1') THEN ncs_reg <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_ncs_reg_ena = '1') THEN ncs_reg <= '1'; + END IF; + END IF; + END PROCESS; + wire_ncs_reg_ena <= (wire_stage_cntr_w_lg_w_lg_w_q_range81w82w83w(0) AND end_one_cyc_pos); + wire_ncs_reg_w_lg_q273w(0) <= NOT ncs_reg; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(0) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(0) = '1') THEN pgwrbuf_dataout(0) <= wire_pgwrbuf_dataout_d(0); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(1) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(1) = '1') THEN pgwrbuf_dataout(1) <= wire_pgwrbuf_dataout_d(1); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(2) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(2) = '1') THEN pgwrbuf_dataout(2) <= wire_pgwrbuf_dataout_d(2); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(3) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(3) = '1') THEN pgwrbuf_dataout(3) <= wire_pgwrbuf_dataout_d(3); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(4) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(4) = '1') THEN pgwrbuf_dataout(4) <= wire_pgwrbuf_dataout_d(4); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(5) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(5) = '1') THEN pgwrbuf_dataout(5) <= wire_pgwrbuf_dataout_d(5); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(6) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(6) = '1') THEN pgwrbuf_dataout(6) <= wire_pgwrbuf_dataout_d(6); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN pgwrbuf_dataout(7) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_pgwrbuf_dataout_ena(7) = '1') THEN pgwrbuf_dataout(7) <= wire_pgwrbuf_dataout_d(7); + END IF; + END IF; + END PROCESS; + wire_pgwrbuf_dataout_d <= ( wire_w_lg_w_lg_read_bufdly403w404w & wire_w_lg_read_bufdly408w); + loop31 : FOR i IN 0 TO 7 GENERATE + wire_pgwrbuf_dataout_ena(i) <= wire_w_lg_read_bufdly398w(0); + END GENERATE loop31; + wire_pgwrbuf_dataout_w_q_range399w <= pgwrbuf_dataout(6 DOWNTO 0); + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN read_bufdly_reg <= read_buf; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(0) = '1') THEN read_data_reg(0) <= wire_read_data_reg_d(0); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(1) = '1') THEN read_data_reg(1) <= wire_read_data_reg_d(1); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(2) = '1') THEN read_data_reg(2) <= wire_read_data_reg_d(2); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(3) = '1') THEN read_data_reg(3) <= wire_read_data_reg_d(3); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(4) = '1') THEN read_data_reg(4) <= wire_read_data_reg_d(4); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(5) = '1') THEN read_data_reg(5) <= wire_read_data_reg_d(5); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(6) = '1') THEN read_data_reg(6) <= wire_read_data_reg_d(6); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_read_data_reg_ena(7) = '1') THEN read_data_reg(7) <= wire_read_data_reg_d(7); + END IF; + END IF; + END PROCESS; + wire_read_data_reg_d <= ( read_data_reg_in_wire(7 DOWNTO 0)); + loop32 : FOR i IN 0 TO 7 GENERATE + wire_read_data_reg_ena(i) <= wire_w359w(0); + END GENERATE loop32; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(0) = '1') THEN read_dout_reg(0) <= wire_read_dout_reg_d(0); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(1) = '1') THEN read_dout_reg(1) <= wire_read_dout_reg_d(1); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(2) = '1') THEN read_dout_reg(2) <= wire_read_dout_reg_d(2); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(3) = '1') THEN read_dout_reg(3) <= wire_read_dout_reg_d(3); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(4) = '1') THEN read_dout_reg(4) <= wire_read_dout_reg_d(4); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(5) = '1') THEN read_dout_reg(5) <= wire_read_dout_reg_d(5); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(6) = '1') THEN read_dout_reg(6) <= wire_read_dout_reg_d(6); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_dout_reg_ena(7) = '1') THEN read_dout_reg(7) <= wire_read_dout_reg_d(7); + END IF; + END IF; + END PROCESS; + wire_read_dout_reg_d <= ( read_dout_reg(6 DOWNTO 0) & wire_w_lg_data0out_wire328w); + loop33 : FOR i IN 0 TO 7 GENERATE + wire_read_dout_reg_ena(i) <= wire_w_lg_w_lg_stage4_wire325w326w(0); + END GENERATE loop33; + PROCESS (clkin_wire, clr_read_wire) + BEGIN + IF (clr_read_wire = '1') THEN read_reg <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_read_reg_ena = '1') THEN read_reg <= read; + END IF; + END IF; + END PROCESS; + wire_read_reg_ena <= (wire_w_lg_busy_wire1w(0) AND rden_wire); + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN sec_erase_reg <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_sec_erase_reg_ena = '1') THEN sec_erase_reg <= sector_erase; + END IF; + END IF; + END PROCESS; + wire_sec_erase_reg_ena <= (wire_w_lg_busy_wire1w(0) AND wren_wire); + PROCESS (clkin_wire, end_ophdly) + BEGIN + IF (end_ophdly = '1') THEN shftpgwr_data_reg <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN shftpgwr_data_reg <= ((wire_stage_cntr_w_lg_w_q_range81w86w(0) AND wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_q(0)); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN shift_op_reg <= wire_stage_cntr_w_lg_w_lg_w_q_range81w82w83w(0); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN stage2_reg <= wire_stage_cntr_w_lg_w_lg_w_q_range81w82w83w(0); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '1' AND clkin_wire'event) THEN stage3_dly_reg <= wire_stage_cntr_w_lg_w_q_range81w84w(0); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN stage3_reg <= wire_stage_cntr_w_lg_w_q_range81w84w(0); + END IF; + END PROCESS; + PROCESS (clkin_wire) + BEGIN + IF (clkin_wire = '0' AND clkin_wire'event) THEN stage4_reg <= wire_stage_cntr_w_lg_w_q_range81w86w(0); + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN start_wrpoll_reg <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_start_wrpoll_reg_ena = '1') THEN start_wrpoll_reg <= wire_stage_cntr_w_lg_w_q_range81w84w(0); + END IF; + END IF; + END PROCESS; + wire_start_wrpoll_reg_ena <= ((do_write_rstat AND do_polling) AND end_one_cycle); + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN start_wrpoll_reg2 <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN start_wrpoll_reg2 <= start_wrpoll_reg; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(0) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(0) = '1') THEN statreg_int(0) <= wire_statreg_int_d(0); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(1) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(1) = '1') THEN statreg_int(1) <= wire_statreg_int_d(1); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(2) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(2) = '1') THEN statreg_int(2) <= wire_statreg_int_d(2); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(3) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(3) = '1') THEN statreg_int(3) <= wire_statreg_int_d(3); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(4) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(4) = '1') THEN statreg_int(4) <= wire_statreg_int_d(4); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(5) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(5) = '1') THEN statreg_int(5) <= wire_statreg_int_d(5); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(6) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(6) = '1') THEN statreg_int(6) <= wire_statreg_int_d(6); + END IF; + END IF; + END PROCESS; + PROCESS (clkin_wire, clr_rstat_wire) + BEGIN + IF (clr_rstat_wire = '1') THEN statreg_int(7) <= '0'; + ELSIF (clkin_wire = '0' AND clkin_wire'event) THEN + IF (wire_statreg_int_ena(7) = '1') THEN statreg_int(7) <= wire_statreg_int_d(7); + END IF; + END IF; + END PROCESS; + wire_statreg_int_d <= ( read_dout_reg(7 DOWNTO 0)); + loop34 : FOR i IN 0 TO 7 GENERATE + wire_statreg_int_ena(i) <= wire_w_lg_w_lg_end_operation381w382w(0); + END GENERATE loop34; + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN write_prot_reg <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_write_prot_reg_ena = '1') THEN write_prot_reg <= ((wire_w_lg_do_write56w(0) AND ((((((wire_addr_reg_w_lg_w_lg_w_lg_w500w501w502w503w(0) OR (wire_addr_reg_w_lg_w496w497w(0) AND wire_w_lg_bp0_wire473w(0))) OR wire_addr_reg_w_lg_w492w493w(0)) OR ((wire_addr_reg_w_lg_w_lg_w_lg_w_q_range308w479w484w485w(0) AND wire_w_lg_bp1_wire477w(0)) AND wire_w_lg_bp0_wire473w(0))) OR wire_addr_reg_w_lg_w_lg_w_lg_w_lg_w_q_range308w479w480w481w482w(0)) OR (wire_addr_reg_w_lg_w_lg_w_q_range308w474w475w(0) AND wire_w_lg_bp0_wire473w(0))) OR wire_w_lg_w_lg_bp2_wire471w472w(0))) OR be_write_prot); + END IF; + END IF; + END PROCESS; + wire_write_prot_reg_ena <= (((wire_w_lg_w_lg_do_sec_erase462w463w(0) AND (NOT wire_wrstage_cntr_q(1))) AND wire_wrstage_cntr_q(0)) AND end_ophdly); + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN write_reg <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN + IF (wire_write_reg_ena = '1') THEN write_reg <= write; + END IF; + END IF; + END PROCESS; + wire_write_reg_ena <= (wire_w_lg_busy_wire1w(0) AND wren_wire); + PROCESS (clkin_wire, clr_write_wire) + BEGIN + IF (clr_write_wire = '1') THEN write_rstat_reg <= '0'; + ELSIF (clkin_wire = '1' AND clkin_wire'event) THEN write_rstat_reg <= (wire_w_lg_w_lg_w_lg_do_write56w57w460w(0) AND (((NOT wire_wrstage_cntr_q(1)) AND wire_wrstage_cntr_w_lg_w_q_range453w454w(0)) OR wire_wrstage_cntr_w_lg_w_q_range455w456w(0))); + END IF; + END PROCESS; + wire_cmpr4_dataa <= ( page_size_wire(8 DOWNTO 0)); + wire_cmpr4_datab <= ( wire_pgwr_data_cntr_q(8 DOWNTO 0)); + cmpr4 : lpm_compare + GENERIC MAP ( + LPM_WIDTH => 9 + ) + PORT MAP ( + aeb => wire_cmpr4_aeb, + dataa => wire_cmpr4_dataa, + datab => wire_cmpr4_datab + ); + wire_cmpr5_dataa <= ( wire_pgwr_data_cntr_q(8 DOWNTO 0)); + wire_cmpr5_datab <= ( wire_pgwr_read_cntr_q(8 DOWNTO 0)); + cmpr5 : lpm_compare + GENERIC MAP ( + LPM_WIDTH => 9 + ) + PORT MAP ( + aeb => wire_cmpr5_aeb, + dataa => wire_cmpr5_dataa, + datab => wire_cmpr5_datab + ); + wire_pgwr_data_cntr_clk_en <= wire_w_lg_w_lg_w_lg_shift_bytes_wire395w411w412w(0); + wire_w_lg_w_lg_w_lg_shift_bytes_wire395w411w412w(0) <= ((shift_bytes_wire AND wren_wire) AND wire_w_lg_reach_max_cnt410w(0)) AND wire_w_lg_do_write394w(0); + wire_pgwr_data_cntr_w_q_range416w(0) <= wire_pgwr_data_cntr_q(1); + wire_pgwr_data_cntr_w_q_range419w(0) <= wire_pgwr_data_cntr_q(2); + wire_pgwr_data_cntr_w_q_range422w(0) <= wire_pgwr_data_cntr_q(3); + wire_pgwr_data_cntr_w_q_range425w(0) <= wire_pgwr_data_cntr_q(4); + wire_pgwr_data_cntr_w_q_range428w(0) <= wire_pgwr_data_cntr_q(5); + wire_pgwr_data_cntr_w_q_range431w(0) <= wire_pgwr_data_cntr_q(6); + wire_pgwr_data_cntr_w_q_range434w(0) <= wire_pgwr_data_cntr_q(7); + wire_pgwr_data_cntr_w_q_range437w(0) <= wire_pgwr_data_cntr_q(8); + pgwr_data_cntr : lpm_counter + GENERIC MAP ( + lpm_direction => "UP", + lpm_port_updown => "PORT_UNUSED", + lpm_width => 9 + ) + PORT MAP ( + aclr => clr_write_wire, + clk_en => wire_pgwr_data_cntr_clk_en, + clock => clkin_wire, + q => wire_pgwr_data_cntr_q + ); + pgwr_read_cntr : lpm_counter + GENERIC MAP ( + lpm_direction => "UP", + lpm_port_updown => "PORT_UNUSED", + lpm_width => 9 + ) + PORT MAP ( + aclr => clr_write_wire, + clk_en => read_buf, + clock => clkin_wire, + q => wire_pgwr_read_cntr_q + ); + wire_mux211_dataout <= end_add_cycle_mux_datab_wire WHEN do_fast_read = '1' ELSE wire_addbyte_cntr_w_lg_w_q_range119w124w(0); + wire_scfifo3_data <= ( datain(7 DOWNTO 0)); + wire_scfifo3_rdreq <= wire_w_lg_read_buf397w(0); + wire_w_lg_read_buf397w(0) <= read_buf OR dummy_read_buf; + wire_scfifo3_wrreq <= wire_w_lg_w_lg_shift_bytes_wire395w396w(0); + wire_w_lg_w_lg_shift_bytes_wire395w396w(0) <= (shift_bytes_wire AND wren_wire) AND wire_w_lg_do_write394w(0); + wire_scfifo3_w_q_range402w <= wire_scfifo3_q(7 DOWNTO 1); + wire_scfifo3_w_q_range407w(0) <= wire_scfifo3_q(0); + scfifo3 : scfifo + GENERIC MAP ( + LPM_NUMWORDS => 258, + LPM_WIDTH => 8, + LPM_WIDTHU => 9, + USE_EAB => "ON" + ) + PORT MAP ( + aclr => clr_write_wire, + clock => clkin_wire, + data => wire_scfifo3_data, + q => wire_scfifo3_q, + rdreq => wire_scfifo3_rdreq, + wrreq => wire_scfifo3_wrreq + ); + stratixii_asmiblock2 : stratixiv_asmiblock + PORT MAP ( + data0out => wire_stratixii_asmiblock2_data0out, + dclkin => clkin_wire, + oe => oe_wire, + scein => scein_wire, + sdoin => sdoin_wire + ); + + END RTL; --ip_stratixiv_asmi_parallel_altasmi_parallel_15a2 +--VALID FILE + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY ip_stratixiv_asmi_parallel IS + PORT + ( + addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + clkin : IN STD_LOGIC ; + datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rden : IN STD_LOGIC ; + read : IN STD_LOGIC ; + sector_erase : IN STD_LOGIC ; + shift_bytes : IN STD_LOGIC ; + wren : IN STD_LOGIC ; + write : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_valid : OUT STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + illegal_erase : OUT STD_LOGIC ; + illegal_write : OUT STD_LOGIC + ); +END ip_stratixiv_asmi_parallel; + + +ARCHITECTURE RTL OF ip_stratixiv_asmi_parallel IS + + ATTRIBUTE synthesis_clearbox: natural; + ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2; + ATTRIBUTE clearbox_macroname: string; + ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "ALTASMI_PARALLEL"; + ATTRIBUTE clearbox_defparam: string; + ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "data_width=STANDARD;epcs_type=EPCS128;intended_device_family=Stratix IV;lpm_hint=UNUSED;lpm_type=altasmi_parallel;page_size=256;port_bulk_erase=PORT_UNUSED;port_en4b_addr=PORT_UNUSED;port_fast_read=PORT_UNUSED;port_illegal_erase=PORT_USED;port_illegal_write=PORT_USED;port_rdid_out=PORT_UNUSED;port_read_address=PORT_UNUSED;port_read_rdid=PORT_UNUSED;port_read_sid=PORT_UNUSED;port_read_status=PORT_UNUSED;port_sector_erase=PORT_USED;port_sector_protect=PORT_UNUSED;port_shift_bytes=PORT_USED;port_wren=PORT_USED;port_write=PORT_USED;use_eab=ON;"; + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + + + + COMPONENT ip_stratixiv_asmi_parallel_altasmi_parallel_15a2 + PORT ( + illegal_write : OUT STD_LOGIC ; + read : IN STD_LOGIC ; + shift_bytes : IN STD_LOGIC ; + wren : IN STD_LOGIC ; + clkin : IN STD_LOGIC ; + data_valid : OUT STD_LOGIC ; + datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + illegal_erase : OUT STD_LOGIC ; + rden : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + busy : OUT STD_LOGIC ; + sector_erase : IN STD_LOGIC ; + write : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + illegal_write <= sub_wire0; + data_valid <= sub_wire1; + illegal_erase <= sub_wire2; + dataout <= sub_wire3(7 DOWNTO 0); + busy <= sub_wire4; + + ip_stratixiv_asmi_parallel_altasmi_parallel_15a2_component : ip_stratixiv_asmi_parallel_altasmi_parallel_15a2 + PORT MAP ( + read => read, + shift_bytes => shift_bytes, + wren => wren, + clkin => clkin, + datain => datain, + rden => rden, + addr => addr, + sector_erase => sector_erase, + write => write, + illegal_write => sub_wire0, + data_valid => sub_wire1, + illegal_erase => sub_wire2, + dataout => sub_wire3, + busy => sub_wire4 + ); + + + +END RTL; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" +-- Retrieval info: CONSTANT: DATA_WIDTH STRING "STANDARD" +-- Retrieval info: CONSTANT: EPCS_TYPE STRING "EPCS128" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" +-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altasmi_parallel" +-- Retrieval info: CONSTANT: PAGE_SIZE NUMERIC "256" +-- Retrieval info: CONSTANT: PORT_BULK_ERASE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_EN4B_ADDR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FAST_READ STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ILLEGAL_ERASE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_ILLEGAL_WRITE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_RDID_OUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_READ_ADDRESS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_READ_RDID STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_READ_SID STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_READ_STATUS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SECTOR_ERASE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SECTOR_PROTECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SHIFT_BYTES STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_WREN STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_WRITE STRING "PORT_USED" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: USED_PORT: addr 0 0 24 0 INPUT NODEFVAL "addr[23..0]" +-- Retrieval info: CONNECT: @addr 0 0 24 0 addr 0 0 24 0 +-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" +-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 +-- Retrieval info: USED_PORT: clkin 0 0 0 0 INPUT NODEFVAL "clkin" +-- Retrieval info: CONNECT: @clkin 0 0 0 0 clkin 0 0 0 0 +-- Retrieval info: USED_PORT: data_valid 0 0 0 0 OUTPUT NODEFVAL "data_valid" +-- Retrieval info: CONNECT: data_valid 0 0 0 0 @data_valid 0 0 0 0 +-- Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]" +-- Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0 +-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]" +-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0 +-- Retrieval info: USED_PORT: illegal_erase 0 0 0 0 OUTPUT NODEFVAL "illegal_erase" +-- Retrieval info: CONNECT: illegal_erase 0 0 0 0 @illegal_erase 0 0 0 0 +-- Retrieval info: USED_PORT: illegal_write 0 0 0 0 OUTPUT NODEFVAL "illegal_write" +-- Retrieval info: CONNECT: illegal_write 0 0 0 0 @illegal_write 0 0 0 0 +-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT NODEFVAL "rden" +-- Retrieval info: CONNECT: @rden 0 0 0 0 rden 0 0 0 0 +-- Retrieval info: USED_PORT: read 0 0 0 0 INPUT NODEFVAL "read" +-- Retrieval info: CONNECT: @read 0 0 0 0 read 0 0 0 0 +-- Retrieval info: USED_PORT: sector_erase 0 0 0 0 INPUT NODEFVAL "sector_erase" +-- Retrieval info: CONNECT: @sector_erase 0 0 0 0 sector_erase 0 0 0 0 +-- Retrieval info: USED_PORT: shift_bytes 0 0 0 0 INPUT NODEFVAL "shift_bytes" +-- Retrieval info: CONNECT: @shift_bytes 0 0 0 0 shift_bytes 0 0 0 0 +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +-- Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: USED_PORT: write 0 0 0 0 INPUT NODEFVAL "write" +-- Retrieval info: CONNECT: @write 0 0 0 0 write 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_asmi_parallel.vhd TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_asmi_parallel.qip TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_asmi_parallel.bsf FALSE TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_asmi_parallel_inst.vhd FALSE TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_asmi_parallel.inc FALSE TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_asmi_parallel.cmp FALSE TRUE diff --git a/libraries/technology/altera/stratixiv/ip_stratixiv_remote_update.vhd b/libraries/technology/altera/stratixiv/ip_stratixiv_remote_update.vhd new file mode 100644 index 0000000000000000000000000000000000000000..09e6cca7c56f200707dfe07a6397ff76db80e387 --- /dev/null +++ b/libraries/technology/altera/stratixiv/ip_stratixiv_remote_update.vhd @@ -0,0 +1,1024 @@ +-- megafunction wizard: %ALTREMOTE_UPDATE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altremote_update + +-- ============================================================ +-- File Name: ip_stratixiv_remote_update.vhd +-- Megafunction Name(s): +-- altremote_update +-- +-- Simulation Library Files(s): +-- lpm;stratixiv +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2011 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +--altremote_update CBX_AUTO_BLACKBOX="ALL" check_app_pof="false" DEVICE_FAMILY="Stratix IV" in_data_width=24 operation_mode="remote" out_data_width=24 busy clock data_in data_out param read_param reconfig reset reset_timer write_param +--VERSION_BEGIN 11.1SP2 cbx_altremote_update 2012:01:25:21:12:11:SJ cbx_cycloneii 2012:01:25:21:12:11:SJ cbx_lpm_add_sub 2012:01:25:21:12:11:SJ cbx_lpm_compare 2012:01:25:21:12:11:SJ cbx_lpm_counter 2012:01:25:21:12:11:SJ cbx_lpm_decode 2012:01:25:21:12:11:SJ cbx_lpm_shiftreg 2012:01:25:21:12:11:SJ cbx_mgl 2012:01:25:21:26:09:SJ cbx_stratix 2012:01:25:21:12:11:SJ cbx_stratixii 2012:01:25:21:12:11:SJ VERSION_END + + LIBRARY lpm; + USE lpm.all; + + LIBRARY stratixiv; + USE stratixiv.all; + +--synthesis_resources = lpm_counter 2 reg 42 stratixiv_rublock 1 + LIBRARY ieee; + USE ieee.std_logic_1164.all; + + ENTITY ip_stratixiv_remote_update_rmtupdt_jol IS + PORT + ( + busy : OUT STD_LOGIC; + clock : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (23 DOWNTO 0) := (OTHERS => '0'); + data_out : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + param : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0'); + read_param : IN STD_LOGIC := '0'; + reconfig : IN STD_LOGIC := '0'; + reset : IN STD_LOGIC; + reset_timer : IN STD_LOGIC := '0'; + write_param : IN STD_LOGIC := '0' + ); + END ip_stratixiv_remote_update_rmtupdt_jol; + + ARCHITECTURE RTL OF ip_stratixiv_remote_update_rmtupdt_jol IS + + ATTRIBUTE synthesis_clearbox : natural; + ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2; + ATTRIBUTE ALTERA_ATTRIBUTE : string; + ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "suppress_da_rule_internal=c104;suppress_da_rule_internal=C101;suppress_da_rule_internal=C103"; + + SIGNAL check_busy_dffe : STD_LOGIC_VECTOR(0 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL dffe4a : STD_LOGIC_VECTOR(23 DOWNTO 0) + -- synopsys translate_off + := "000000000000000000000000" + -- synopsys translate_on + ; + SIGNAL wire_dffe4a_clrn : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL wire_dffe4a_ena : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL dffe5 : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL dffe6a : STD_LOGIC_VECTOR(2 DOWNTO 0) + -- synopsys translate_off + := (OTHERS => '0') + -- synopsys translate_on + ; + SIGNAL wire_dffe6a_ena : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL idle_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL idle_write_wait : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL read_data_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL read_init_counter_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL read_init_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL read_post_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL read_pre_data_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL write_data_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL write_init_counter_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL write_init_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL write_load_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL write_post_data_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL write_pre_data_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL write_wait_state : STD_LOGIC + -- synopsys translate_off + := '0' + -- synopsys translate_on + ; + SIGNAL wire_cntr2_q : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL wire_cntr3_q : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL wire_sd1_regout : STD_LOGIC; + SIGNAL wire_w_lg_w297w300w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w297w309w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w303w304w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_idle344w345w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w312w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w307w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w74w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w110w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w114w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w118w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w122w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w126w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w130w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w134w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w138w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w142w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w146w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w78w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w150w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w154w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w158w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w162w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w82w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w86w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w90w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w94w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w98w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w102w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w106w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_load_enable69w70w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w297w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w303w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_idle344w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_data358w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_init_counter354w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_post364w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_pre_data353w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_rublock_regout_reg396w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable76w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable116w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable120w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable124w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable128w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable132w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable136w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable140w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable144w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable148w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable152w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable80w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable156w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable160w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable164w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable72w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable84w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable88w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable92w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable96w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable100w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable104w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable108w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable112w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_data373w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_init_counter370w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_post_data379w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_pre_data369w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_param_decoder_param_latch_range293w311w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_param_decoder_param_latch_range293w306w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_shift_reg_clear67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_bit_counter_all_done372w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_bit_counter_param_start_match352w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_idle327w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_data323w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_init326w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_init_counter325w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_param343w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_post322w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_read_pre_data324w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_select_shift_nloop395w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable69w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_width_counter_all_done356w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_width_counter_param_width_match357w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_data318w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_init321w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_init_counter320w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_load316w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_param342w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_post_data317w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_pre_data319w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_write_wait315w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_param_decoder_param_latch_range293w294w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_param_decoder_param_latch_range295w296w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_param_decoder_param_latch_range298w299w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_w_lg_w_lg_idle344w345w346w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_clear67w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_lg_shift_reg_load_enable66w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL bit_counter_all_done : STD_LOGIC; + SIGNAL bit_counter_clear : STD_LOGIC; + SIGNAL bit_counter_enable : STD_LOGIC; + SIGNAL bit_counter_param_start : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL bit_counter_param_start_match : STD_LOGIC; + SIGNAL idle : STD_LOGIC; + SIGNAL param_decoder_param_latch : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL param_decoder_select : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL power_up : STD_LOGIC; + SIGNAL read_data : STD_LOGIC; + SIGNAL read_init : STD_LOGIC; + SIGNAL read_init_counter : STD_LOGIC; + SIGNAL read_post : STD_LOGIC; + SIGNAL read_pre_data : STD_LOGIC; + SIGNAL rublock_captnupdt : STD_LOGIC; + SIGNAL rublock_clock : STD_LOGIC; + SIGNAL rublock_reconfig : STD_LOGIC; + SIGNAL rublock_reconfig_st : STD_LOGIC; + SIGNAL rublock_regin : STD_LOGIC; + SIGNAL rublock_regout : STD_LOGIC; + SIGNAL rublock_regout_reg : STD_LOGIC; + SIGNAL rublock_shiftnld : STD_LOGIC; + SIGNAL select_shift_nloop : STD_LOGIC; + SIGNAL shift_reg_clear : STD_LOGIC; + SIGNAL shift_reg_load_enable : STD_LOGIC; + SIGNAL shift_reg_serial_in : STD_LOGIC; + SIGNAL shift_reg_serial_out : STD_LOGIC; + SIGNAL shift_reg_shift_enable : STD_LOGIC; + SIGNAL start_bit_decoder_out : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL start_bit_decoder_param_select : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL w21w : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL w50w : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL width_counter_all_done : STD_LOGIC; + SIGNAL width_counter_clear : STD_LOGIC; + SIGNAL width_counter_enable : STD_LOGIC; + SIGNAL width_counter_param_width : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL width_counter_param_width_match : STD_LOGIC; + SIGNAL width_decoder_out : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL width_decoder_param_select : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL write_data : STD_LOGIC; + SIGNAL write_init : STD_LOGIC; + SIGNAL write_init_counter : STD_LOGIC; + SIGNAL write_load : STD_LOGIC; + SIGNAL write_post_data : STD_LOGIC; + SIGNAL write_pre_data : STD_LOGIC; + SIGNAL write_wait : STD_LOGIC; + SIGNAL wire_w_data_in_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range115w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range127w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range139w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range151w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range79w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range103w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_data_in_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_param_decoder_param_latch_range293w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_param_decoder_param_latch_range295w : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL wire_w_param_decoder_param_latch_range298w : STD_LOGIC_VECTOR (0 DOWNTO 0); + COMPONENT lpm_counter + GENERIC + ( + lpm_avalue : STRING := "0"; + lpm_direction : STRING := "DEFAULT"; + lpm_modulus : NATURAL := 0; + lpm_port_updown : STRING := "PORT_CONNECTIVITY"; + lpm_pvalue : STRING := "0"; + lpm_svalue : STRING := "0"; + lpm_width : NATURAL; + lpm_type : STRING := "lpm_counter" + ); + PORT + ( + aclr : IN STD_LOGIC := '0'; + aload : IN STD_LOGIC := '0'; + aset : IN STD_LOGIC := '0'; + cin : IN STD_LOGIC := '1'; + clk_en : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC; + cnt_en : IN STD_LOGIC := '1'; + cout : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); + sclr : IN STD_LOGIC := '0'; + sload : IN STD_LOGIC := '0'; + sset : IN STD_LOGIC := '0'; + updown : IN STD_LOGIC := '1' + ); + END COMPONENT; + COMPONENT stratixiv_rublock + PORT + ( + captnupdt : IN STD_LOGIC; + clk : IN STD_LOGIC; + rconfig : IN STD_LOGIC; + regin : IN STD_LOGIC; + regout : OUT STD_LOGIC; + rsttimer : IN STD_LOGIC; + shiftnld : IN STD_LOGIC + ); + END COMPONENT; + BEGIN + + wire_w_lg_w297w300w(0) <= wire_w297w(0) AND wire_w_lg_w_param_decoder_param_latch_range298w299w(0); + wire_w_lg_w297w309w(0) <= wire_w297w(0) AND wire_w_param_decoder_param_latch_range298w(0); + wire_w_lg_w303w304w(0) <= wire_w303w(0) AND wire_w_lg_w_param_decoder_param_latch_range298w299w(0); + wire_w_lg_w_lg_idle344w345w(0) <= wire_w_lg_idle344w(0) AND wire_w_lg_write_param342w(0); + wire_w312w(0) <= wire_w_lg_w_param_decoder_param_latch_range293w311w(0) AND wire_w_param_decoder_param_latch_range298w(0); + wire_w307w(0) <= wire_w_lg_w_param_decoder_param_latch_range293w306w(0) AND wire_w_lg_w_param_decoder_param_latch_range298w299w(0); + wire_w_lg_w_lg_shift_reg_load_enable69w74w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(1); + wire_w_lg_w_lg_shift_reg_load_enable69w110w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(10); + wire_w_lg_w_lg_shift_reg_load_enable69w114w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(11); + wire_w_lg_w_lg_shift_reg_load_enable69w118w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(12); + wire_w_lg_w_lg_shift_reg_load_enable69w122w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(13); + wire_w_lg_w_lg_shift_reg_load_enable69w126w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(14); + wire_w_lg_w_lg_shift_reg_load_enable69w130w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(15); + wire_w_lg_w_lg_shift_reg_load_enable69w134w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(16); + wire_w_lg_w_lg_shift_reg_load_enable69w138w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(17); + wire_w_lg_w_lg_shift_reg_load_enable69w142w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(18); + wire_w_lg_w_lg_shift_reg_load_enable69w146w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(19); + wire_w_lg_w_lg_shift_reg_load_enable69w78w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(2); + wire_w_lg_w_lg_shift_reg_load_enable69w150w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(20); + wire_w_lg_w_lg_shift_reg_load_enable69w154w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(21); + wire_w_lg_w_lg_shift_reg_load_enable69w158w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(22); + wire_w_lg_w_lg_shift_reg_load_enable69w162w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(23); + wire_w_lg_w_lg_shift_reg_load_enable69w82w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(3); + wire_w_lg_w_lg_shift_reg_load_enable69w86w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(4); + wire_w_lg_w_lg_shift_reg_load_enable69w90w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(5); + wire_w_lg_w_lg_shift_reg_load_enable69w94w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(6); + wire_w_lg_w_lg_shift_reg_load_enable69w98w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(7); + wire_w_lg_w_lg_shift_reg_load_enable69w102w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(8); + wire_w_lg_w_lg_shift_reg_load_enable69w106w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND dffe4a(9); + wire_w_lg_w_lg_shift_reg_load_enable69w70w(0) <= wire_w_lg_shift_reg_load_enable69w(0) AND shift_reg_serial_in; + wire_w297w(0) <= wire_w_lg_w_param_decoder_param_latch_range293w294w(0) AND wire_w_lg_w_param_decoder_param_latch_range295w296w(0); + wire_w303w(0) <= wire_w_lg_w_param_decoder_param_latch_range293w294w(0) AND wire_w_param_decoder_param_latch_range295w(0); + wire_w_lg_idle344w(0) <= idle AND wire_w_lg_read_param343w(0); + wire_w_lg_read_data358w(0) <= read_data AND wire_w_lg_width_counter_param_width_match357w(0); + wire_w_lg_read_init_counter354w(0) <= read_init_counter AND wire_w_lg_bit_counter_param_start_match352w(0); + wire_w_lg_read_post364w(0) <= read_post AND wire_w_lg_width_counter_all_done356w(0); + wire_w_lg_read_pre_data353w(0) <= read_pre_data AND wire_w_lg_bit_counter_param_start_match352w(0); + wire_w_lg_rublock_regout_reg396w(0) <= rublock_regout_reg AND wire_w_lg_select_shift_nloop395w(0); + wire_w_lg_shift_reg_load_enable76w(0) <= shift_reg_load_enable AND wire_w_data_in_range75w(0); + wire_w_lg_shift_reg_load_enable116w(0) <= shift_reg_load_enable AND wire_w_data_in_range115w(0); + wire_w_lg_shift_reg_load_enable120w(0) <= shift_reg_load_enable AND wire_w_data_in_range119w(0); + wire_w_lg_shift_reg_load_enable124w(0) <= shift_reg_load_enable AND wire_w_data_in_range123w(0); + wire_w_lg_shift_reg_load_enable128w(0) <= shift_reg_load_enable AND wire_w_data_in_range127w(0); + wire_w_lg_shift_reg_load_enable132w(0) <= shift_reg_load_enable AND wire_w_data_in_range131w(0); + wire_w_lg_shift_reg_load_enable136w(0) <= shift_reg_load_enable AND wire_w_data_in_range135w(0); + wire_w_lg_shift_reg_load_enable140w(0) <= shift_reg_load_enable AND wire_w_data_in_range139w(0); + wire_w_lg_shift_reg_load_enable144w(0) <= shift_reg_load_enable AND wire_w_data_in_range143w(0); + wire_w_lg_shift_reg_load_enable148w(0) <= shift_reg_load_enable AND wire_w_data_in_range147w(0); + wire_w_lg_shift_reg_load_enable152w(0) <= shift_reg_load_enable AND wire_w_data_in_range151w(0); + wire_w_lg_shift_reg_load_enable80w(0) <= shift_reg_load_enable AND wire_w_data_in_range79w(0); + wire_w_lg_shift_reg_load_enable156w(0) <= shift_reg_load_enable AND wire_w_data_in_range155w(0); + wire_w_lg_shift_reg_load_enable160w(0) <= shift_reg_load_enable AND wire_w_data_in_range159w(0); + wire_w_lg_shift_reg_load_enable164w(0) <= shift_reg_load_enable AND wire_w_data_in_range163w(0); + wire_w_lg_shift_reg_load_enable72w(0) <= shift_reg_load_enable AND wire_w_data_in_range71w(0); + wire_w_lg_shift_reg_load_enable84w(0) <= shift_reg_load_enable AND wire_w_data_in_range83w(0); + wire_w_lg_shift_reg_load_enable88w(0) <= shift_reg_load_enable AND wire_w_data_in_range87w(0); + wire_w_lg_shift_reg_load_enable92w(0) <= shift_reg_load_enable AND wire_w_data_in_range91w(0); + wire_w_lg_shift_reg_load_enable96w(0) <= shift_reg_load_enable AND wire_w_data_in_range95w(0); + wire_w_lg_shift_reg_load_enable100w(0) <= shift_reg_load_enable AND wire_w_data_in_range99w(0); + wire_w_lg_shift_reg_load_enable104w(0) <= shift_reg_load_enable AND wire_w_data_in_range103w(0); + wire_w_lg_shift_reg_load_enable108w(0) <= shift_reg_load_enable AND wire_w_data_in_range107w(0); + wire_w_lg_shift_reg_load_enable112w(0) <= shift_reg_load_enable AND wire_w_data_in_range111w(0); + wire_w_lg_write_data373w(0) <= write_data AND wire_w_lg_width_counter_param_width_match357w(0); + wire_w_lg_write_init_counter370w(0) <= write_init_counter AND wire_w_lg_bit_counter_param_start_match352w(0); + wire_w_lg_write_post_data379w(0) <= write_post_data AND wire_w_lg_bit_counter_all_done372w(0); + wire_w_lg_write_pre_data369w(0) <= write_pre_data AND wire_w_lg_bit_counter_param_start_match352w(0); + wire_w_lg_w_param_decoder_param_latch_range293w311w(0) <= wire_w_param_decoder_param_latch_range293w(0) AND wire_w_lg_w_param_decoder_param_latch_range295w296w(0); + wire_w_lg_w_param_decoder_param_latch_range293w306w(0) <= wire_w_param_decoder_param_latch_range293w(0) AND wire_w_param_decoder_param_latch_range295w(0); + wire_w_lg_w_lg_shift_reg_clear67w68w(0) <= NOT wire_w_lg_shift_reg_clear67w(0); + wire_w_lg_bit_counter_all_done372w(0) <= NOT bit_counter_all_done; + wire_w_lg_bit_counter_param_start_match352w(0) <= NOT bit_counter_param_start_match; + wire_w_lg_idle327w(0) <= NOT idle; + wire_w_lg_read_data323w(0) <= NOT read_data; + wire_w_lg_read_init326w(0) <= NOT read_init; + wire_w_lg_read_init_counter325w(0) <= NOT read_init_counter; + wire_w_lg_read_param343w(0) <= NOT read_param; + wire_w_lg_read_post322w(0) <= NOT read_post; + wire_w_lg_read_pre_data324w(0) <= NOT read_pre_data; + wire_w_lg_select_shift_nloop395w(0) <= NOT select_shift_nloop; + wire_w_lg_shift_reg_load_enable69w(0) <= NOT shift_reg_load_enable; + wire_w_lg_width_counter_all_done356w(0) <= NOT width_counter_all_done; + wire_w_lg_width_counter_param_width_match357w(0) <= NOT width_counter_param_width_match; + wire_w_lg_write_data318w(0) <= NOT write_data; + wire_w_lg_write_init321w(0) <= NOT write_init; + wire_w_lg_write_init_counter320w(0) <= NOT write_init_counter; + wire_w_lg_write_load316w(0) <= NOT write_load; + wire_w_lg_write_param342w(0) <= NOT write_param; + wire_w_lg_write_post_data317w(0) <= NOT write_post_data; + wire_w_lg_write_pre_data319w(0) <= NOT write_pre_data; + wire_w_lg_write_wait315w(0) <= NOT write_wait; + wire_w_lg_w_param_decoder_param_latch_range293w294w(0) <= NOT wire_w_param_decoder_param_latch_range293w(0); + wire_w_lg_w_param_decoder_param_latch_range295w296w(0) <= NOT wire_w_param_decoder_param_latch_range295w(0); + wire_w_lg_w_param_decoder_param_latch_range298w299w(0) <= NOT wire_w_param_decoder_param_latch_range298w(0); + wire_w_lg_w_lg_w_lg_idle344w345w346w(0) <= wire_w_lg_w_lg_idle344w345w(0) OR write_wait; + wire_w_lg_shift_reg_clear67w(0) <= shift_reg_clear OR reset; + wire_w_lg_shift_reg_load_enable66w(0) <= shift_reg_load_enable OR shift_reg_shift_enable; + bit_counter_all_done <= (((((wire_cntr2_q(0) AND wire_cntr2_q(1)) AND (NOT wire_cntr2_q(2))) AND wire_cntr2_q(3)) AND (NOT wire_cntr2_q(4))) AND wire_cntr2_q(5)); + bit_counter_clear <= (read_init OR write_init); + bit_counter_enable <= (((((((((read_init OR write_init) OR read_init_counter) OR write_init_counter) OR read_pre_data) OR write_pre_data) OR read_data) OR write_data) OR read_post) OR write_post_data); + bit_counter_param_start <= start_bit_decoder_out; + bit_counter_param_start_match <= ((((((NOT w21w(0)) AND (NOT w21w(1))) AND (NOT w21w(2))) AND (NOT w21w(3))) AND (NOT w21w(4))) AND (NOT w21w(5))); + busy <= wire_w_lg_idle327w(0); + data_out <= dffe4a; + idle <= idle_state; + param_decoder_param_latch <= dffe6a; + param_decoder_select <= ( wire_w312w & wire_w_lg_w297w309w & wire_w307w & wire_w_lg_w303w304w & wire_w_lg_w297w300w); + power_up <= ((((((((((((wire_w_lg_idle327w(0) AND wire_w_lg_read_init326w(0)) AND wire_w_lg_read_init_counter325w(0)) AND wire_w_lg_read_pre_data324w(0)) AND wire_w_lg_read_data323w(0)) AND wire_w_lg_read_post322w(0)) AND wire_w_lg_write_init321w(0)) AND wire_w_lg_write_init_counter320w(0)) AND wire_w_lg_write_pre_data319w(0)) AND wire_w_lg_write_data318w(0)) AND wire_w_lg_write_post_data317w(0)) AND wire_w_lg_write_load316w(0)) AND wire_w_lg_write_wait315w(0)); + read_data <= read_data_state; + read_init <= read_init_state; + read_init_counter <= read_init_counter_state; + read_post <= read_post_state; + read_pre_data <= read_pre_data_state; + rublock_captnupdt <= wire_w_lg_write_load316w(0); + rublock_clock <= (NOT (clock OR idle_write_wait)); + rublock_reconfig <= rublock_reconfig_st; + rublock_reconfig_st <= (idle AND reconfig); + rublock_regin <= (wire_w_lg_rublock_regout_reg396w(0) OR (shift_reg_serial_out AND select_shift_nloop)); + rublock_regout <= wire_sd1_regout; + rublock_regout_reg <= dffe5; + rublock_shiftnld <= (((((read_pre_data OR write_pre_data) OR read_data) OR write_data) OR read_post) OR write_post_data); + select_shift_nloop <= (wire_w_lg_read_data358w(0) OR wire_w_lg_write_data373w(0)); + shift_reg_clear <= read_init; + shift_reg_load_enable <= (idle AND write_param); + shift_reg_serial_in <= (rublock_regout_reg AND select_shift_nloop); + shift_reg_serial_out <= dffe4a(0); + shift_reg_shift_enable <= (((read_data OR write_data) OR read_post) OR write_post_data); + start_bit_decoder_out <= ((((( "0" & "0" & "0" & "0" & "0" & "0") OR ( "0" & start_bit_decoder_param_select(1) & start_bit_decoder_param_select(1) & start_bit_decoder_param_select(1) & start_bit_decoder_param_select(1) & start_bit_decoder_param_select(1))) OR ( "0" & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & "0")) OR ( "0" & "0" & "0" & start_bit_decoder_param_select(3) & start_bit_decoder_param_select(3) & "0")) OR ( "0" & "0" & "0" & start_bit_decoder_param_select(4) & "0" & start_bit_decoder_param_select(4))); + start_bit_decoder_param_select <= param_decoder_select; + w21w <= (wire_cntr2_q XOR bit_counter_param_start); + w50w <= (wire_cntr3_q XOR width_counter_param_width); + width_counter_all_done <= ((((wire_cntr3_q(0) AND wire_cntr3_q(1)) AND wire_cntr3_q(2)) AND (NOT wire_cntr3_q(3))) AND wire_cntr3_q(4)); + width_counter_clear <= (read_init OR write_init); + width_counter_enable <= ((read_data OR write_data) OR read_post); + width_counter_param_width <= width_decoder_out; + width_counter_param_width_match <= (((((NOT w50w(0)) AND (NOT w50w(1))) AND (NOT w50w(2))) AND (NOT w50w(3))) AND (NOT w50w(4))); + width_decoder_out <= ((((( "0" & "0" & width_decoder_param_select(0) & "0" & width_decoder_param_select(0)) OR ( "0" & width_decoder_param_select(1) & width_decoder_param_select(1) & "0" & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(2))) OR ( width_decoder_param_select(3) & width_decoder_param_select(3) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(4))); + width_decoder_param_select <= param_decoder_select; + write_data <= write_data_state; + write_init <= write_init_state; + write_init_counter <= write_init_counter_state; + write_load <= write_load_state; + write_post_data <= write_post_data_state; + write_pre_data <= write_pre_data_state; + write_wait <= write_wait_state; + wire_w_data_in_range75w(0) <= data_in(0); + wire_w_data_in_range115w(0) <= data_in(10); + wire_w_data_in_range119w(0) <= data_in(11); + wire_w_data_in_range123w(0) <= data_in(12); + wire_w_data_in_range127w(0) <= data_in(13); + wire_w_data_in_range131w(0) <= data_in(14); + wire_w_data_in_range135w(0) <= data_in(15); + wire_w_data_in_range139w(0) <= data_in(16); + wire_w_data_in_range143w(0) <= data_in(17); + wire_w_data_in_range147w(0) <= data_in(18); + wire_w_data_in_range151w(0) <= data_in(19); + wire_w_data_in_range79w(0) <= data_in(1); + wire_w_data_in_range155w(0) <= data_in(20); + wire_w_data_in_range159w(0) <= data_in(21); + wire_w_data_in_range163w(0) <= data_in(22); + wire_w_data_in_range71w(0) <= data_in(23); + wire_w_data_in_range83w(0) <= data_in(2); + wire_w_data_in_range87w(0) <= data_in(3); + wire_w_data_in_range91w(0) <= data_in(4); + wire_w_data_in_range95w(0) <= data_in(5); + wire_w_data_in_range99w(0) <= data_in(6); + wire_w_data_in_range103w(0) <= data_in(7); + wire_w_data_in_range107w(0) <= data_in(8); + wire_w_data_in_range111w(0) <= data_in(9); + wire_w_param_decoder_param_latch_range293w(0) <= param_decoder_param_latch(0); + wire_w_param_decoder_param_latch_range295w(0) <= param_decoder_param_latch(1); + wire_w_param_decoder_param_latch_range298w(0) <= param_decoder_param_latch(2); + check_busy_dffe <= (OTHERS => '0'); + PROCESS (clock, wire_dffe4a_clrn(0)) + BEGIN + IF (wire_dffe4a_clrn(0) = '0') THEN dffe4a(0) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(0) = '1') THEN dffe4a(0) <= (wire_w_lg_shift_reg_load_enable76w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w74w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(1)) + BEGIN + IF (wire_dffe4a_clrn(1) = '0') THEN dffe4a(1) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(1) = '1') THEN dffe4a(1) <= (wire_w_lg_shift_reg_load_enable80w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w78w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(2)) + BEGIN + IF (wire_dffe4a_clrn(2) = '0') THEN dffe4a(2) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(2) = '1') THEN dffe4a(2) <= (wire_w_lg_shift_reg_load_enable84w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w82w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(3)) + BEGIN + IF (wire_dffe4a_clrn(3) = '0') THEN dffe4a(3) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(3) = '1') THEN dffe4a(3) <= (wire_w_lg_shift_reg_load_enable88w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w86w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(4)) + BEGIN + IF (wire_dffe4a_clrn(4) = '0') THEN dffe4a(4) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(4) = '1') THEN dffe4a(4) <= (wire_w_lg_shift_reg_load_enable92w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w90w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(5)) + BEGIN + IF (wire_dffe4a_clrn(5) = '0') THEN dffe4a(5) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(5) = '1') THEN dffe4a(5) <= (wire_w_lg_shift_reg_load_enable96w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w94w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(6)) + BEGIN + IF (wire_dffe4a_clrn(6) = '0') THEN dffe4a(6) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(6) = '1') THEN dffe4a(6) <= (wire_w_lg_shift_reg_load_enable100w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w98w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(7)) + BEGIN + IF (wire_dffe4a_clrn(7) = '0') THEN dffe4a(7) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(7) = '1') THEN dffe4a(7) <= (wire_w_lg_shift_reg_load_enable104w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w102w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(8)) + BEGIN + IF (wire_dffe4a_clrn(8) = '0') THEN dffe4a(8) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(8) = '1') THEN dffe4a(8) <= (wire_w_lg_shift_reg_load_enable108w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w106w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(9)) + BEGIN + IF (wire_dffe4a_clrn(9) = '0') THEN dffe4a(9) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(9) = '1') THEN dffe4a(9) <= (wire_w_lg_shift_reg_load_enable112w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w110w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(10)) + BEGIN + IF (wire_dffe4a_clrn(10) = '0') THEN dffe4a(10) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(10) = '1') THEN dffe4a(10) <= (wire_w_lg_shift_reg_load_enable116w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w114w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(11)) + BEGIN + IF (wire_dffe4a_clrn(11) = '0') THEN dffe4a(11) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(11) = '1') THEN dffe4a(11) <= (wire_w_lg_shift_reg_load_enable120w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w118w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(12)) + BEGIN + IF (wire_dffe4a_clrn(12) = '0') THEN dffe4a(12) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(12) = '1') THEN dffe4a(12) <= (wire_w_lg_shift_reg_load_enable124w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w122w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(13)) + BEGIN + IF (wire_dffe4a_clrn(13) = '0') THEN dffe4a(13) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(13) = '1') THEN dffe4a(13) <= (wire_w_lg_shift_reg_load_enable128w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w126w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(14)) + BEGIN + IF (wire_dffe4a_clrn(14) = '0') THEN dffe4a(14) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(14) = '1') THEN dffe4a(14) <= (wire_w_lg_shift_reg_load_enable132w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w130w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(15)) + BEGIN + IF (wire_dffe4a_clrn(15) = '0') THEN dffe4a(15) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(15) = '1') THEN dffe4a(15) <= (wire_w_lg_shift_reg_load_enable136w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w134w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(16)) + BEGIN + IF (wire_dffe4a_clrn(16) = '0') THEN dffe4a(16) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(16) = '1') THEN dffe4a(16) <= (wire_w_lg_shift_reg_load_enable140w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w138w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(17)) + BEGIN + IF (wire_dffe4a_clrn(17) = '0') THEN dffe4a(17) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(17) = '1') THEN dffe4a(17) <= (wire_w_lg_shift_reg_load_enable144w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w142w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(18)) + BEGIN + IF (wire_dffe4a_clrn(18) = '0') THEN dffe4a(18) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(18) = '1') THEN dffe4a(18) <= (wire_w_lg_shift_reg_load_enable148w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w146w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(19)) + BEGIN + IF (wire_dffe4a_clrn(19) = '0') THEN dffe4a(19) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(19) = '1') THEN dffe4a(19) <= (wire_w_lg_shift_reg_load_enable152w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w150w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(20)) + BEGIN + IF (wire_dffe4a_clrn(20) = '0') THEN dffe4a(20) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(20) = '1') THEN dffe4a(20) <= (wire_w_lg_shift_reg_load_enable156w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w154w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(21)) + BEGIN + IF (wire_dffe4a_clrn(21) = '0') THEN dffe4a(21) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(21) = '1') THEN dffe4a(21) <= (wire_w_lg_shift_reg_load_enable160w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w158w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(22)) + BEGIN + IF (wire_dffe4a_clrn(22) = '0') THEN dffe4a(22) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(22) = '1') THEN dffe4a(22) <= (wire_w_lg_shift_reg_load_enable164w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w162w(0)); + END IF; + END IF; + END PROCESS; + PROCESS (clock, wire_dffe4a_clrn(23)) + BEGIN + IF (wire_dffe4a_clrn(23) = '0') THEN dffe4a(23) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe4a_ena(23) = '1') THEN dffe4a(23) <= (wire_w_lg_shift_reg_load_enable72w(0) OR wire_w_lg_w_lg_shift_reg_load_enable69w70w(0)); + END IF; + END IF; + END PROCESS; + loop0 : FOR i IN 0 TO 23 GENERATE + wire_dffe4a_clrn(i) <= wire_w_lg_w_lg_shift_reg_clear67w68w(0); + END GENERATE loop0; + loop1 : FOR i IN 0 TO 23 GENERATE + wire_dffe4a_ena(i) <= wire_w_lg_shift_reg_load_enable66w(0); + END GENERATE loop1; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN dffe5 <= '0'; + ELSIF (clock = '1' AND clock'event) THEN dffe5 <= rublock_regout; + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN dffe6a(0) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe6a_ena(0) = '1') THEN dffe6a(0) <= param(0); + END IF; + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN dffe6a(1) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe6a_ena(1) = '1') THEN dffe6a(1) <= param(1); + END IF; + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN dffe6a(2) <= '0'; + ELSIF (clock = '1' AND clock'event) THEN + IF (wire_dffe6a_ena(2) = '1') THEN dffe6a(2) <= param(2); + END IF; + END IF; + END PROCESS; + loop2 : FOR i IN 0 TO 2 GENERATE + wire_dffe6a_ena(i) <= (idle AND (write_param OR read_param)); + END GENERATE loop2; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN idle_state <= '1'; + ELSIF (clock = '1' AND clock'event) THEN idle_state <= (((wire_w_lg_w_lg_w_lg_idle344w345w346w(0) OR (read_data AND width_counter_all_done)) OR (read_post AND width_counter_all_done)) OR power_up); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN idle_write_wait <= '0'; + ELSIF (clock = '1' AND clock'event) THEN idle_write_wait <= ((((wire_w_lg_w_lg_w_lg_idle344w345w346w(0) OR (read_data AND width_counter_all_done)) OR (read_post AND width_counter_all_done)) OR power_up) AND write_load); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN read_data_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN read_data_state <= (((read_init_counter AND bit_counter_param_start_match) OR (read_pre_data AND bit_counter_param_start_match)) OR (wire_w_lg_read_data358w(0) AND wire_w_lg_width_counter_all_done356w(0))); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN read_init_counter_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN read_init_counter_state <= read_init; + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN read_init_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN read_init_state <= (idle AND read_param); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN read_post_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN read_post_state <= (((read_data AND width_counter_param_width_match) AND wire_w_lg_width_counter_all_done356w(0)) OR wire_w_lg_read_post364w(0)); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN read_pre_data_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN read_pre_data_state <= (wire_w_lg_read_init_counter354w(0) OR wire_w_lg_read_pre_data353w(0)); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN write_data_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN write_data_state <= (((write_init_counter AND bit_counter_param_start_match) OR (write_pre_data AND bit_counter_param_start_match)) OR (wire_w_lg_write_data373w(0) AND wire_w_lg_bit_counter_all_done372w(0))); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN write_init_counter_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN write_init_counter_state <= write_init; + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN write_init_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN write_init_state <= (idle AND write_param); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN write_load_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN write_load_state <= ((write_data AND bit_counter_all_done) OR (write_post_data AND bit_counter_all_done)); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN write_post_data_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN write_post_data_state <= (((write_data AND width_counter_param_width_match) AND wire_w_lg_bit_counter_all_done372w(0)) OR wire_w_lg_write_post_data379w(0)); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN write_pre_data_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN write_pre_data_state <= (wire_w_lg_write_init_counter370w(0) OR wire_w_lg_write_pre_data369w(0)); + END IF; + END PROCESS; + PROCESS (clock, reset) + BEGIN + IF (reset = '1') THEN write_wait_state <= '0'; + ELSIF (clock = '1' AND clock'event) THEN write_wait_state <= write_load; + END IF; + END PROCESS; + cntr2 : lpm_counter + GENERIC MAP ( + lpm_direction => "UP", + lpm_port_updown => "PORT_UNUSED", + lpm_width => 6 + ) + PORT MAP ( + clock => clock, + cnt_en => bit_counter_enable, + q => wire_cntr2_q, + sclr => bit_counter_clear + ); + cntr3 : lpm_counter + GENERIC MAP ( + lpm_direction => "UP", + lpm_port_updown => "PORT_UNUSED", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + cnt_en => width_counter_enable, + q => wire_cntr3_q, + sclr => width_counter_clear + ); + sd1 : stratixiv_rublock + PORT MAP ( + captnupdt => rublock_captnupdt, + clk => rublock_clock, + rconfig => rublock_reconfig, + regin => rublock_regin, + regout => wire_sd1_regout, + rsttimer => reset_timer, + shiftnld => rublock_shiftnld + ); + + END RTL; --ip_stratixiv_remote_update_rmtupdt_jol +--VALID FILE + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY ip_stratixiv_remote_update IS + PORT + ( + clock : IN STD_LOGIC ; + data_in : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + read_param : IN STD_LOGIC ; + reconfig : IN STD_LOGIC ; + reset : IN STD_LOGIC ; + reset_timer : IN STD_LOGIC ; + write_param : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_out : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END ip_stratixiv_remote_update; + + +ARCHITECTURE RTL OF ip_stratixiv_remote_update IS + + ATTRIBUTE synthesis_clearbox: natural; + ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2; + ATTRIBUTE clearbox_macroname: string; + ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "altremote_update"; + ATTRIBUTE clearbox_defparam: string; + ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "check_app_pof=false;intended_device_family=Stratix IV;in_data_width=24;operation_mode=REMOTE;out_data_width=24;"; + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0); + + + + COMPONENT ip_stratixiv_remote_update_rmtupdt_jol + PORT ( + clock : IN STD_LOGIC ; + data_in : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + read_param : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_out : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + reconfig : IN STD_LOGIC ; + reset : IN STD_LOGIC ; + reset_timer : IN STD_LOGIC ; + write_param : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + busy <= sub_wire0; + data_out <= sub_wire1(23 DOWNTO 0); + + ip_stratixiv_remote_update_rmtupdt_jol_component : ip_stratixiv_remote_update_rmtupdt_jol + PORT MAP ( + clock => clock, + data_in => data_in, + read_param => read_param, + param => param, + reconfig => reconfig, + reset => reset, + reset_timer => reset_timer, + write_param => write_param, + busy => sub_wire0, + data_out => sub_wire1 + ); + + + +END RTL; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" +-- Retrieval info: PRIVATE: SIM_INIT_CONFIG_COMBO STRING "FACTORY" +-- Retrieval info: PRIVATE: SIM_INIT_PAGE_SELECT_COMBO STRING "0" +-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT0_CHECK STRING "0" +-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT1_CHECK STRING "0" +-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT2_CHECK STRING "0" +-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT3_CHECK STRING "0" +-- Retrieval info: PRIVATE: SIM_INIT_STAT_BIT4_CHECK STRING "0" +-- Retrieval info: PRIVATE: SIM_INIT_WATCHDOG_VALUE_EDIT STRING "1" +-- Retrieval info: PRIVATE: SUPPORT_WRITE_CHECK STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WATCHDOG_ENABLE_CHECK STRING "0" +-- Retrieval info: CONSTANT: CHECK_APP_POF STRING "false" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" +-- Retrieval info: CONSTANT: IN_DATA_WIDTH NUMERIC "24" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "REMOTE" +-- Retrieval info: CONSTANT: OUT_DATA_WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: data_in 0 0 24 0 INPUT NODEFVAL "data_in[23..0]" +-- Retrieval info: USED_PORT: data_out 0 0 24 0 OUTPUT NODEFVAL "data_out[23..0]" +-- Retrieval info: USED_PORT: param 0 0 3 0 INPUT NODEFVAL "param[2..0]" +-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param" +-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig" +-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset" +-- Retrieval info: USED_PORT: reset_timer 0 0 0 0 INPUT NODEFVAL "reset_timer" +-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param" +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_in 0 0 24 0 data_in 0 0 24 0 +-- Retrieval info: CONNECT: @param 0 0 3 0 param 0 0 3 0 +-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0 +-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0 +-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0 +-- Retrieval info: CONNECT: @reset_timer 0 0 0 0 reset_timer 0 0 0 0 +-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0 +-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 +-- Retrieval info: CONNECT: data_out 0 0 24 0 @data_out 0 0 24 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_remote_update.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_remote_update.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_remote_update.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_remote_update.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_remote_update_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm +-- Retrieval info: LIB_FILE: stratixiv diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..2dd6f897eaebda575333cde016da69838491af4c --- /dev/null +++ b/libraries/technology/flash/hdllib.cfg @@ -0,0 +1,13 @@ +hdl_lib_name = tech_flash +hdl_library_clause_name = tech_flash_lib +hdl_lib_uses = technology ip_stratixiv + +build_sim_dir = $HDL_BUILD_DIR +build_synth_dir = + +synth_files = + tech_flash_component_pkg.vhd + tech_flash_asmi_parallel.vhd + tech_flash_remote_update.vhd + +test_bench_files = diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd new file mode 100644 index 0000000000000000000000000000000000000000..aa82934c6726ab713d3e920fbb3aa42f453aac61 --- /dev/null +++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose : Active Serial Memory Interface to flash device + +LIBRARY ieee, technology_lib; +USE ieee.std_logic_1164.all; +USE work.tech_flash_component_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; + +-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. +LIBRARY ip_stratixiv_lib; + +ENTITY tech_flash_asmi_parallel IS + GENERIC ( + g_technology : NATURAL := c_tech_select_default + ); + PORT ( + addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + clkin : IN STD_LOGIC ; + datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rden : IN STD_LOGIC ; + read : IN STD_LOGIC ; + sector_erase : IN STD_LOGIC ; + shift_bytes : IN STD_LOGIC ; + wren : IN STD_LOGIC ; + write : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_valid : OUT STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + illegal_erase : OUT STD_LOGIC ; + illegal_write : OUT STD_LOGIC + ); +END tech_flash_asmi_parallel; + + +ARCHITECTURE str OF tech_flash_asmi_parallel IS + +BEGIN + + gen_stratixiv : IF g_technology=c_tech_stratixiv GENERATE + u0 : ip_stratixiv_asmi_parallel + PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write) + END GENERATE; + +END ARCHITECTURE; \ No newline at end of file diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd new file mode 100644 index 0000000000000000000000000000000000000000..4e0d06d6357d7ef5d41d07087b5a1ca5c666989b --- /dev/null +++ b/libraries/technology/flash/tech_flash_component_pkg.vhd @@ -0,0 +1,66 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose: IP components declarations for various devices that get wrapped by the tech components + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +PACKAGE tech_flash_component_pkg IS + + ----------------------------------------------------------------------------- + -- stratixiv + ----------------------------------------------------------------------------- + + COMPONENT ip_stratixiv_asmi_parallel IS + PORT ( + addr : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + clkin : IN STD_LOGIC ; + datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rden : IN STD_LOGIC ; + read : IN STD_LOGIC ; + sector_erase : IN STD_LOGIC ; + shift_bytes : IN STD_LOGIC ; + wren : IN STD_LOGIC ; + write : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_valid : OUT STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + illegal_erase : OUT STD_LOGIC ; + illegal_write : OUT STD_LOGIC + ); + + COMPONENT ip_stratixiv_remote_update IS + PORT ( + clock : IN STD_LOGIC ; + data_in : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + read_param : IN STD_LOGIC ; + reconfig : IN STD_LOGIC ; + reset : IN STD_LOGIC ; + reset_timer : IN STD_LOGIC ; + write_param : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_out : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +END tech_flash_component_pkg; diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd new file mode 100644 index 0000000000000000000000000000000000000000..599c3afcb64bbea14b55369ea1535ee2f961b692 --- /dev/null +++ b/libraries/technology/flash/tech_flash_remote_update.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2014 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +-- Purpose : Remote update from flash device + +LIBRARY ieee, technology_lib; +USE ieee.std_logic_1164.all; +USE work.tech_flash_component_pkg.ALL; +USE technology_lib.technology_pkg.ALL; +USE technology_lib.technology_select_pkg.ALL; + +-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. +LIBRARY ip_stratixiv_lib; + +ENTITY tech_flash_remote_update IS + GENERIC ( + g_technology : NATURAL := c_tech_select_default + ); + PORT ( + clock : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + read_param : IN STD_LOGIC; + reconfig : IN STD_LOGIC; + reset : IN STD_LOGIC; + reset_timer : IN STD_LOGIC; + write_param : IN STD_LOGIC; + busy : OUT STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END tech_flash_remote_update; + + +ARCHITECTURE str OF tech_flash_remote_update IS + +BEGIN + + gen_stratixiv : IF g_technology=c_tech_stratixiv GENERATE + u0 : ip_stratixiv_remote_update + PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out); + END GENERATE; + +END ARCHITECTURE; \ No newline at end of file