diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
index f2e2c0667939a5a81e493dc9aaef0509a40bba71..dc699c30e1e63ce7f9c17784767630755085d637 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
@@ -11,10 +11,10 @@ peripherals:
# Factory / minimal (from ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
index 3484a89a9619badd82f33de1438c861369157974..4db069ba2e64d393aa2219ea1d057eaf70d7b30d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -38,10 +38,10 @@ peripherals:
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
index 0ec8ce1844442c27022f8f314fafaf9126f49cfe..8716458e4529a9552adc28d6858843996c111359 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
@@ -11,10 +11,10 @@ peripherals:
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index 497b912e0945496ebe83bfbaaa669c79a078b582..166db254179b429d95f53754422cea9b4f937c21 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -11,11 +11,11 @@ peripherals:
mm_ports:
# MM port for sdp_info.vhd
- mm_port_name: REG_SDP_INFO
+ mm_port_type: REG
mm_port_description: |
"The SDP info contains central SDP information. The station_id applies to the entire station.
The other info fields apply per antenna band (low band or high band). An FPGA node only
participates in one band."
- mm_port_type: REG
fields:
- - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x0 }
- - { field_name: antenna_band_index, mm_width: 1, access_mode: RO, address_offset: 0x4 }
@@ -41,6 +41,7 @@ peripherals:
mm_ports:
# MM port for sdp_subband_equalizer.vhd
- mm_port_name: RAM_EQUALIZER_GAINS
+ mm_port_type: RAM
mm_port_description: |
"The subband weigths are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
Q_fft * N_sub = 2 * 512 = 1024 complex coefficients as:
@@ -48,17 +49,16 @@ peripherals:
(cint16)subband_weights[S_pn/Q_fft]_[Q_fft][N_sub]
where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: coef
field_description: |
"Complex coefficient to calibrate the gain and phase per subband. Packed as imaginary in high part,
real in low part of mm_width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
+ number_of_fields: 1024 # = Q_fft * N_sub = 2 signal inputs * 512 subbands
+ address_offset: 0x0
mm_width: 32 # = N_complex * W_sub_weight
radix: cint16_ir
- address_offset: 0x0
- number_of_fields: 1024 # = Q_fft * N_sub = 2 signal inputs * 512 subbands
- peripheral_name: sdp_bf_weights # pi_sdp_bf_weights.py
@@ -70,6 +70,7 @@ peripherals:
mm_ports:
# MM port for sdp_beamformer_local.vhd / sdp_bf_weights.vhd / mms_dp_gain_serial_arr.vhd
- mm_port_name: RAM_BF_WEIGHTS
+ mm_port_type: RAM
mm_port_description: |
"The beamlet weigths are stored in g_nof_instances = N_pol_bf * P_pfb = 2 * 6 = 12, where
P_pfb = S_pn / Q_fft = 6. Per instance there is a block of Q_fft * S_sub_bf =
@@ -96,17 +97,16 @@ peripherals:
when index of N_pol_bf and index of N_pol are the same. The cross-polarization BF
weights (XY, YX) are set when index of N_pol_bf and index of N_pol are different. If
no cross-polarization weighting is needed, then these weights can be kept 0."
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: coef
field_description: |
"Complex weight per subband. Packed as imaginary in high part, real in low part
of mm_width = N_complex * W_bf_weight = 2 * 16 = 32 bit."
+ number_of_fields: g_nof_gains
+ address_offset: 0x0
mm_width: 32 # = N_complex * W_bf_weight
radix: cint16_ir
- address_offset: 0x0
- number_of_fields: g_nof_gains
- peripheral_name: sdp_bf_scale # pi_sdp_bf_scale.py
@@ -118,6 +118,7 @@ peripherals:
mm_ports:
# MM port for node_sdp_beamformer.vhd / mms_dp_scale.vhd / mms_dp_gain.vhd / mms_dp_gain_arr.vhd
- mm_port_name: REG_BF_SCALE
+ mm_port_type: REG
mm_port_description: |
"The beamlet scale function scales the beamlet sum with a real scale factor and then
requantizes the result to beamlet data output with less bits.
@@ -129,16 +130,15 @@ peripherals:
. 2**11 rounds the lowest 4 bits, selects the next 8 bits of the beamlet sum and clips
the highest 6 bits,
. 2**5 rounds the lowest 10 bits and selects the highest 8 bits of the beamlet sum."
- mm_port_type: REG
fields:
- - field_name: scale
field_description: ""
+ number_of_fields: 1
+ address_offset: 0x0
mm_width: g_gain_w
#user_width: g_gain_w # EK TODO check parameter passing to user_width
radix: uint32 # scale factor is unsigned value
resolution_w: 0 - g_lsb_w
- address_offset: 0x0
- number_of_fields: 1
- - field_name: unused
field_description: "Not used."
address_offset: 0x4
@@ -149,6 +149,7 @@ peripherals:
mm_ports:
# MM port for sdp_beamformer_output.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the beamlet data output offload UDP packets.
@@ -172,7 +173,6 @@ peripherals:
21 0x84 [31:0] = eth_dst_mac[31:0]
22 0x88 [15:0] = eth_dst_mac[47:32]
"
- mm_port_type: REG
fields:
# eth field group
- - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
@@ -226,6 +226,7 @@ peripherals:
mm_ports:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the SST offload UDP packets.
@@ -236,7 +237,6 @@ peripherals:
[1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
"
- mm_port_type: REG
fields:
# eth field group
- - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
@@ -297,6 +297,7 @@ peripherals:
mm_ports:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the BST offload UDP packets.
@@ -307,7 +308,6 @@ peripherals:
[1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
"
- mm_port_type: REG
fields:
# eth field group
- - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
@@ -368,6 +368,7 @@ peripherals:
mm_ports:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
+ mm_port_type: REG
mm_port_description: |
"The ETH/IP/UDP/application header fields for the XST offload UDP packets.
@@ -379,7 +380,6 @@ peripherals:
[1] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
"
- mm_port_type: REG
fields:
# eth field group
- - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
index b286945d85c58ed131fb78a2577c4cdf00aeff36..faf0c65fd9c6df00dbf7e479840f80d65697ac8d 100644
--- a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
+++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
@@ -44,81 +44,38 @@ peripherals:
# peripheral, unb1_board_wdi_reg
- peripheral_name: ctrl
-
+ peripheral_description: " "
mm_ports:
# actual hdl name: unb1_board_wdi_reg
- mm_port_name : pio_wdi
mm_port_type : REG
+ mm_port_description: "Reset register, for nios "
fields:
- - field_name : nios_reset
+ field_description: " Reset done by nios "
+ number_of_fields: 1
+ address_offset : 0x0
mm_width : 32
access_mode : WO
- address_offset : 0x0
- number_of_fields: 1
- field_description: " Reset done by nios "
- mm_port_description: "Reset register, for nios "
- peripheral_description: " "
-
# peripheral, unb1_board_wdi_reg
- peripheral_name: wdi
-
+ peripheral_description: " "
mm_ports:
# actual hdl name: unb1_board_wdi_reg
- mm_port_name : wdi
mm_port_type : REG
+ mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded "
fields:
- - field_name : reset_word
+ field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
access_mode : WO
address_offset: 0x0
- field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
-
- mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded "
- peripheral_description: " "
# periheral, unb1_board_sens
- peripheral_name: sens
-
- parameters:
- - { name: g_sim, value: FALSE }
- - { name: g_clk_freq, value: c_unb1_board_mm_clk_freq_125M }
- - { name: g_temp_high, value: 85 }
-
- mm_ports:
- # actual hdl name: reg_unb1_sens
- - mm_port_name : sens
- mm_port_type : REG
- fields:
- - - field_name : sens_data
- mm_width : 8
- access_mode : RO
- address_offset: 0x0
- number_of_fields: 4
- field_description: |
- " data array with sens data
- 0x0 = fpga temperature in degrees (two's complement)
- 0x1 = eth_temp temperature in degrees (two's complement)
- 0x2 = hot_swap_v_sens
- 0x3 = hot_swap_v_source"
-
- - - field_name : sens_err
- mm_width : 1
- access_mode : RO
- address_offset: 0x10
- radix : uint32
- field_description: ""
-
- - - field_name : temp_high
- mm_width : 7
- address_offset: 0x14
- reset_value : g_temp_high
- software_value: g_temp_high
- field_description: ""
-
- mm_port_description: " "
-
peripheral_description: |
"
+-----------------------------------------------------------------------------+
@@ -142,13 +99,13 @@ peripherals:
LTC4260_V_UNIT_SENSE = 0.0003 -- 0.3 mV over Rs for current sense
LTC4260_V_UNIT_SOURCE = 0.4 -- 400 mV supply voltage (e.g +48 V)
LTC4260_V_UNIT_ADIN = 0.01 -- 10 mV ADC
-
+
. From UniBoard unb_sensors.h:
SENS_HOT_SWAP_R_SENSE = 0.005 -- R sense on UniBoard is 5 mOhm (~= 10 mOhm // 10 mOhm)
SENS_HOT_SWAP_I_UNIT_SENSE = LTC4260_V_UNIT_SENSE / SENS_HOT_SWAP_R_SENSE
SENS_HOT_SWAP_V_UNIT_SOURCE = LTC4260_V_UNIT_SOURCE
-
- ==>
+
+ ==>
Via all FN and BN:
0 = FPGA temperature = TInt8(fpga_temp)
Only via BN3:
@@ -156,4 +113,39 @@ peripherals:
2 = UniBoard hot swap supply current = hot_swap_v_sense * SENS_HOT_SWAP_I_UNIT_SENSE
3 = UniBoard hot swap supply voltage = hot_swap_v_source * SENS_HOT_SWAP_V_UNIT_SOURCE
4 = I2C error status for BN3 sensors access only, 0 = ok"
+ parameters:
+ - { name: g_sim, value: FALSE }
+ - { name: g_clk_freq, value: c_unb1_board_mm_clk_freq_125M }
+ - { name: g_temp_high, value: 85 }
+ mm_ports:
+ # actual hdl name: reg_unb1_sens
+ - mm_port_name : sens
+ mm_port_type : REG
+ mm_port_description: " "
+ fields:
+ - - field_name : sens_data
+ field_description: |
+ " data array with sens data
+ 0x0 = fpga temperature in degrees (two's complement)
+ 0x1 = eth_temp temperature in degrees (two's complement)
+ 0x2 = hot_swap_v_sens
+ 0x3 = hot_swap_v_source"
+ number_of_fields: 4
+ address_offset: 0x0
+ mm_width : 8
+ access_mode : RO
+
+ - - field_name : sens_err
+ field_description: ""
+ address_offset: 0x10
+ mm_width : 1
+ access_mode : RO
+ radix : uint32
+
+ - - field_name : temp_high
+ field_description: ""
+ address_offset: 0x14
+ mm_width : 7
+ reset_value : g_temp_high
+
diff --git a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
index 678ac4ecf5d194ca2db33c22031bf92dd773ca73..40f9191902718876c4770eddae1437b8cc66f0fe 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
+++ b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
@@ -11,10 +11,10 @@ peripherals:
# Factory / minimal (from ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
index 3e40802728aacfc87c15cfc4f9008d76120bdadb..fc5f4ccbf3e156fe51d24ed3009ccc25029f53c2 100644
--- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
@@ -1,4 +1,3 @@
----
schema_name: args
schema_version: 1.0
schema_type: peripheral
@@ -17,9 +16,9 @@ peripherals:
fields:
- - field_name: rw_data
field_description: "Void data"
- access_mode: RW
- address_offset: 0x0
number_of_fields: 512
+ address_offset: 0x0
+ access_mode: RW
- peripheral_name: system_info # pi_system_info.py
peripheral_description: ""
@@ -32,12 +31,12 @@ peripherals:
fields:
- - field_name: ro_data
field_description: "FPGA info memory map data"
+ number_of_fields: 32768 # c_rom_addr_w in mms_unb2b_board_system_info
+ address_offset: 0x0
mm_width: 32
user_width: 8
radix: char8
access_mode: RO
- address_offset: 0x0
- number_of_fields: 32768 # c_rom_addr_w in mms_unb2b_board_system_info
# MM port for mms_unb2b_board_system_info.vhd / unb2b_board_system_info_reg.vhd
- mm_port_name: PIO_SYSTEM_INFO
@@ -54,66 +53,66 @@ peripherals:
# Each field specified
- - field_name: info
field_description: "Info"
- mm_width: 32
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 32
access_mode: RO
- address_offset: 0x0
- "info": # field_group
- field_name: gn_index
field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
- mm_width: 8
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 8
access_mode: RO
- address_offset: 0x0
- field_name: hw_version
field_description: "UniBoard2 hardware (HW) version."
- mm_width: 2
+ address_offset: 0x0
bit_offset: 8
+ mm_width: 2
access_mode: RO
- address_offset: 0x0
- field_name: cs_sim
field_description: "0 when running on HW, 1 when running in simulation."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 10
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- field_name: fw_version_major
field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
- mm_width: 4
+ address_offset: 0x0
bit_offset: 16
+ mm_width: 4
access_mode: RO
- address_offset: 0x0
- field_name: fw_version_minor
field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
- mm_width: 4
+ address_offset: 0x0
bit_offset: 20
+ mm_width: 4
access_mode: RO
- address_offset: 0x0
- field_name: rom_version
field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
- mm_width: 3
+ address_offset: 0x0
bit_offset: 24
+ mm_width: 3
access_mode: RO
- address_offset: 0x0
- field_name: technology
field_description: "FPGA technology"
- mm_width: 5
+ address_offset: 0x0
bit_offset: 27
+ mm_width: 5
access_mode: RO
- address_offset: 0x0
- - field_name: use_phy
field_description: "PHY interfaces that are active in the FPGA, not used."
+ address_offset: 0x4
mm_width: 8
access_mode: RO
- address_offset: 0x4
- - field_name: design_name
field_description: "FPGA FW design name string."
+ number_of_fields: 52
+ address_offset: 0x8
mm_width: 32
user_width: 8
radix: char8
access_mode: RO
- address_offset: 0x8
- number_of_fields: 52
- - field_name: stamp_date
field_description: "FPGA FW compile date string."
access_mode: RO
@@ -121,22 +120,22 @@ peripherals:
number_of_fields: 1
- - field_name: stamp_time
field_description: "FPGA FW compile time string."
- access_mode: RO
- address_offset: 0x40
number_of_fields: 1
+ address_offset: 0x40
+ access_mode: RO
- - field_name: stamp_commit
field_description: "FPGA FW commit hash string."
- access_mode: RO
- address_offset: 0x44
number_of_fields: 3
+ address_offset: 0x44
+ access_mode: RO
- - field_name: design_note
field_description: "FPGA FW design note string."
+ number_of_fields: 52
+ address_offset: 0x50
mm_width: 32
user_width: 8
radix: char8
access_mode: RO
- address_offset: 0x50
- number_of_fields: 52
- peripheral_name: wdi # pi_wdi.py
peripheral_description: ""
@@ -148,8 +147,8 @@ peripherals:
fields:
- - field_name: wdi_override
field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload."
- access_mode: WO
address_offset: 0x0
+ access_mode: WO
- peripheral_name: unb2_fpga_sens
peripheral_description: ""
@@ -163,9 +162,9 @@ peripherals:
fields:
- - field_name: temp
field_description: "Raw data"
- access_mode: RO
- address_offset: 0x0
number_of_fields: 1
+ address_offset: 0x0
+ access_mode: RO
- mm_port_name: REG_FPGA_VOLTAGE_SENS # pi_unb_fpga_voltagesens.py
mm_port_type: REG
@@ -173,7 +172,7 @@ peripherals:
fields:
- - field_name: voltages
field_description: "Not used"
- access_mode: RO
- address_offset: 0x0
number_of_fields: 6
-
+ address_offset: 0x0
+ access_mode: RO
+
diff --git a/libraries/base/common/common.peripheral.yaml b/libraries/base/common/common.peripheral.yaml
index e59577af29c67ebbd2b74a5090337502014ade1a..5d06bbdbda5d1d9331af904518ebbc63f6a51c9d 100644
--- a/libraries/base/common/common.peripheral.yaml
+++ b/libraries/base/common/common.peripheral.yaml
@@ -21,6 +21,6 @@ peripherals:
fields:
- - field_name: enable
field_description: "When 1 pass on delayed pulse to the output, else disable the output pulse."
+ address_offset: 0x0
mm_width: 1
access_mode: RW
- address_offset: 0x0
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index c5ed1b5fd9c9b168c7c93aad8e1a6fcefacd904e..ac86812ef1440c831599e5e484f71145a97cec63 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -14,15 +14,15 @@ peripherals:
mm_ports:
# MM port for diag_wg_wideband_reg.vhd
- mm_port_name: REG_DIAG_WG
- mm_port_description: "Waveform control."
mm_port_type: REG
+ mm_port_description: "Waveform control."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: nof_samples
field_description: "Number of samples in WG period."
- mm_width: 16
- bit_offset: 16
address_offset: 0x0
+ bit_offset: 16
+ mm_width: 16
- - field_name: mode
field_description: |
"WG mode:
@@ -30,35 +30,35 @@ peripherals:
1 = calc, uses WG buffer waveform to output sinus with ampl * sin(freq * t + phase
2 = repeat, outputs WG buffer waveform repeatedly
3 = single, outputs WG buffer waveform once"
- mm_width: 8
- bit_offset: 0
address_offset: 0x0
+ bit_offset: 0
+ mm_width: 8
- - field_name: phase
field_description: "Phase of WG sinus, phase = int('phase in degrees' * 2**width / 360)."
- mm_width: 16
- bit_offset: 0
address_offset: 0x4
+ bit_offset: 0
+ mm_width: 16
- - field_name: freq
field_description: "Frequency of WG sinus, freq = int('frequency in range 0 to 1' * f_adc * 2**width), where f_adc is sample frequency in Hz."
- mm_width: 31
- bit_offset: 0
address_offset: 0x8
+ bit_offset: 0
+ mm_width: 31
- - field_name: ampl
field_description: "Amplitude of WG sinus, ampl = int('amplitude in range 0 to 2' * 2**(width-1), where amplitude > 1 causes clipping."
- mm_width: 17
- bit_offset: 0
address_offset: 0xC
+ bit_offset: 0
+ mm_width: 17
# MM port for mms_diag_wg_wideband.vhd
- mm_port_name: RAM_DIAG_WG
- mm_port_description: "Waveform buffer."
mm_port_type: RAM
+ mm_port_description: "Waveform buffer."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: "Waveform default is one sinus period (diag_sin_1024x18.hex)."
- mm_width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
- address_offset: 0x0
number_of_fields: 1024 # = 2**c_wg_buf_addr_w in node_adc_input_and_timing.vhd
+ address_offset: 0x0
+ mm_width: 18 # = c_wg_buf_dat_w in node_adc_input_and_timing.vhd
- peripheral_name: diag_data_buffer # pi_diag_data_buffer.py
peripheral_description: "Data buffer (DB)"
@@ -71,27 +71,27 @@ peripherals:
mm_ports:
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: REG_DIAG_DB
- mm_port_description: "Data buffer status."
mm_port_type: REG
+ mm_port_description: "Data buffer status."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: sync_cnt
field_description: "Number of times the DB has been written."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- - field_name: word_cnt
field_description: "Number data words in the DB."
- access_mode: RO
address_offset: 0x4
+ access_mode: RO
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: RAM_DIAG_DB
- mm_port_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
mm_port_type: RAM
+ mm_port_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
number_of_mm_ports: g_nof_streams
fields:
- - field_name: data
field_description: ""
- mm_width: g_data_w
- address_offset: 0x0
number_of_fields: g_nof_data
+ address_offset: 0x0
+ mm_width: g_data_w
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 30e9d265e329a6830bef5d32a8af42a59177d16e..7a8008c0e8addecda2dee9e1579f39f0fd09c9d6 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -16,8 +16,8 @@ peripherals:
fields:
- - field_name: rd_usedw
field_description: "Number of words that can be read from the FIFO."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm.vhd
- mm_port_name: REG_DPMM_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_dpmm.py
mm_port_type: FIFO
@@ -25,8 +25,8 @@ peripherals:
fields:
- - field_name: rd_data
field_description: "Read data from the FIFO."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- peripheral_name: mmdp # pi_mmdp.py
@@ -39,13 +39,13 @@ peripherals:
fields:
- - field_name: wr_usedw
field_description: "Number of words that are in the write FIFO."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- - field_name: wr_availw
field_description: "Number of words that can be written to the write FIFO."
- access_mode: RO
address_offset: 0x4
+ access_mode: RO
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm.vhd
- mm_port_name: REG_MMDP_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_mmdp.py
mm_port_type: FIFO
@@ -53,8 +53,8 @@ peripherals:
fields:
- - field_name: data
field_description: "Write data to the FIFO."
- access_mode: WO
address_offset: 0x0
+ access_mode: WO
- peripheral_name: dp_xonoff # pi_dp_xonoff.py
@@ -73,10 +73,10 @@ peripherals:
field_description: |
"When enable_stream = 0 the data stream is stopped, else when 1 then the data stream is passed on.
Toggling the data stream on or off happens at block or packet boundaries."
+ number_of_fields: 1 #g_nof_streams #sel_a_b(g_combine_streams, 1, g_nof_streams)
+ address_offset: 0x0
mm_width: 1
access_mode: RW
- address_offset: 0x0
- number_of_fields: 1 #g_nof_streams #sel_a_b(g_combine_streams, 1, g_nof_streams)
- peripheral_name: dp_shiftram # pi_dp_shiftram.py
@@ -95,9 +95,9 @@ peripherals:
fields:
- - field_name: shift
field_description: "Fill level of the sample delay buffer in number of data samples."
+ address_offset: 0x0
mm_width: ceil_log2(g_nof_words)
access_mode: RW
- address_offset: 0x0
- peripheral_name: dp_bsn_source # pi_dp_bsn_source.py
@@ -116,33 +116,25 @@ peripherals:
"When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
+ address_offset: 0x0
mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: dp_on_pps
field_description: "When 1 and dp_on = 1 then enable BSN source at next PPS."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: nof_block_per_sync
field_description: "Number of blocks per sync interval."
- access_mode: RW
address_offset: 0x4
- #- - field_name: bsn_lo
- # field_description: "Initial BSN[31:0]"
- # access_mode: RW
- # address_offset: 0x8
- #- - field_name: bsn_hi
- # field_description: "Initial BSN[63:32]"
- # access_mode: RW
- # address_offset: 0xC
+ access_mode: RW
- - field_name: bsn
field_description: "Initial BSN"
+ address_offset: 0x8
user_width: 64
radix: uint64
access_mode: RW
- address_offset: 0x8
- peripheral_name: dp_bsn_source_v2 # pi_dp_bsn_source_v2.py
@@ -163,38 +155,30 @@ peripherals:
"When 1 then enable BSN source, else when 0 disable BSN source. If dp_on_pps is 0,
then dp_on = 1 enables the BSN source immediately. To enable the BSN source at
the next PPS, then first set dp_on_pps = 1. Clearing dp_on stops the BSN source."
+ address_offset: 0x0
mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: dp_on_pps
field_description: "When 1 and dp_on = 1, then enable BSN source at next PPS."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: nof_block_per_sync
field_description: "Number of clock cycles per sync interval."
- access_mode: RW
address_offset: 0x4
- #- - field_name: bsn_init_lo
- # field_description: "Initial BSN[31:0]"
- # access_mode: RW
- # address_offset: 0x8
- #- - field_name: bsn_init_hi
- # field_description: "Initial BSN[63:32]"
- # access_mode: RW
- # address_offset: 0xC
+ access_mode: RW
- - field_name: bsn_init
field_description: "Initial BSN"
+ address_offset: 0x8
user_width: 64
radix: uint64
access_mode: RW
- address_offset: 0x8
- - field_name: bsn_time_offset
field_description: "The BSN block time offset in number of clock cycles, with respect to the PPS."
+ address_offset: 0x10
mm_width: g_bsn_time_offset_w
access_mode: RW
- address_offset: 0x10
- peripheral_name: dp_bsn_scheduler # pi_dp_bsn_scheduler.py
@@ -205,20 +189,12 @@ peripherals:
mm_port_type: REG
mm_port_description: ""
fields:
- #- - field_name: scheduled_bsn_lo
- # field_description: "Write scheduled BSN lo, read current BSN lo. First access lo, then hi."
- # access_mode: RW
- # address_offset: 0x0
- #- - field_name: scheduled_bsn_hi
- # field_description: "Write scheduled BSN hi, read current BSN hi. First access lo, then hi."
- # access_mode: RW
- # address_offset: 0x4
- - field_name: scheduled_bsn
field_description: "Write scheduled BSN. First access lo, then hi."
+ address_offset: 0x0
user_width: 64
radix: uint64
access_mode: RW
- address_offset: 0x0
- peripheral_name: dp_bsn_monitor # pi_dp_bsn_monitor.py
@@ -235,66 +211,50 @@ peripherals:
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: ready_stable
field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: sync_timeout
field_description: "Data stream sync did not occur during last sync interval."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 2 # EK TODO: 2 is correct, but using 1 cause gen_doc.py to fail without clear error, because fields then overlap
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- #- - field_name: bsn_at_sync_lo
- # field_description: "Data stream BSN lo at sync."
- # access_mode: RO
- # address_offset: 0x4
- #- - field_name: bsn_at_sync_hi
- # field_description: "Data stream BSN hi at sync."
- # access_mode: RO
- # address_offset: 0x8
- - field_name: bsn_at_sync
field_description: "Data stream BSN at sync."
+ address_offset: 0x4
user_width: 64
radix: uint64
access_mode: RO
- address_offset: 0x4
- - field_name: nof_sop
field_description: "Number data blocks (sop = start of packet) during last sync interval."
- access_mode: RO
address_offset: 0xC
+ access_mode: RO
- - field_name: nof_valid
field_description: "Number valid samples of the data blocks during last sync interval (= nof_sop * block size)."
- access_mode: RO
address_offset: 0x10
+ access_mode: RO
- - field_name: nof_err
field_description: "Number data blocks with error indication during last sync interval."
- access_mode: RO
address_offset: 0x14
- #- - field_name: bsn_first_lo
- # field_description: "First data stream BSN lo ever."
- # access_mode: RO
- # address_offset: 0x18
- #- - field_name: bsn_first_hi
- # field_description: "First data stream BSN hi ever."
- # access_mode: RO
- # address_offset: 0x1C
+ access_mode: RO
- - field_name: bsn_first
field_description: "First data stream BSN ever."
+ address_offset: 0x18
user_width: 64
radix: uint64
access_mode: RO
- address_offset: 0x18
- - field_name: bsn_first_cycle_cnt
field_description: "Arrival latency of first data stream BSN ever, relative to local sync."
- access_mode: RO
address_offset: 0x20
+ access_mode: RO
- peripheral_name: dp_bsn_monitor_v2 # pi_dp_bsn_monitor_v2.py
@@ -311,52 +271,44 @@ peripherals:
fields:
- - field_name: xon_stable
field_description: "Data block flow control xon signal was active and stable during last sync interval."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: ready_stable
field_description: "Clock cycle flow control ready signal was active and stable during last sync interval."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- - field_name: sync_timeout
field_description: "Data stream sync did not occur during last sync interval."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 1
+ mm_width: 1
access_mode: RO
- address_offset: 0x0
- #- - field_name: bsn_at_sync_lo
- # field_description: "Data stream BSN lo at sync."
- # access_mode: RO
- # address_offset: 0x4
- #- - field_name: bsn_at_sync_hi
- # field_description: "Data stream BSN hi at sync."
- # access_mode: RO
- # address_offset: 0x8
- - field_name: bsn_at_sync
field_description: "Data stream BSN at sync."
+ address_offset: 0x4
user_width: 64
radix: uint64
access_mode: RO
- address_offset: 0x4
- - field_name: nof_sop
field_description: "Number data blocks (sop = start of packet) during last sync interval."
- access_mode: RO
address_offset: 0xC
+ access_mode: RO
- - field_name: nof_valid
field_description: "Number valid samples of the data blocks during last sync interval (= nof_sop * block size)."
- access_mode: RO
address_offset: 0x10
+ access_mode: RO
- - field_name: nof_err
field_description: "Number data blocks with error indication during last sync interval."
- access_mode: RO
address_offset: 0x14
+ access_mode: RO
- - field_name: latency
field_description: "Arrival latency of data stream BSN at sync, relative to local sync."
- access_mode: RO
address_offset: 0x20
+ access_mode: RO
- peripheral_name: dp_selector # pi_dp_selector.py
@@ -371,6 +323,6 @@ peripherals:
field_description: |
"When input_select = 0 select the reference data stream(s), else when 1 select the other data stream(s).
The input_select is synchronsized to the start of a sync interval."
+ address_offset: 0x0
mm_width: 1
access_mode: RW
- address_offset: 0x0
diff --git a/libraries/base/reorder/reorder.peripheral.yaml b/libraries/base/reorder/reorder.peripheral.yaml
index 30e5ecff51b449a4b2ccbf02aee3570f23c93c9d..fa238d51081386f0d1330737dc6f921421944d0a 100644
--- a/libraries/base/reorder/reorder.peripheral.yaml
+++ b/libraries/base/reorder/reorder.peripheral.yaml
@@ -22,13 +22,13 @@ peripherals:
mm_ports:
# MM port for reorder_col_wide.vhd / reorder_col.vhd
- mm_port_name: RAM_SS_SS_WIDE
- mm_port_description: ""
mm_port_type: RAM
+ mm_port_description: ""
number_of_mm_ports: g_wb_factor
fields:
- - field_name: index
field_description: ""
- mm_width: ceil_log2(g_nof_ch_in)
- address_offset: 0x0
number_of_fields: g_nof_ch_sel
+ address_offset: 0x0
+ mm_width: ceil_log2(g_nof_ch_in)
diff --git a/libraries/dsp/bf/bf.peripheral.yaml b/libraries/dsp/bf/bf.peripheral.yaml
index 547dc9a11ae7cb9fb5c29a64f63a0128d77ca811..0a2824614a9051f0822a1bc9153e0c4827711381 100644
--- a/libraries/dsp/bf/bf.peripheral.yaml
+++ b/libraries/dsp/bf/bf.peripheral.yaml
@@ -7,7 +7,9 @@ hdl_library_description: " This is the description for the bf package "
peripherals:
- peripheral_name: bf
-
+ peripheral_description: |
+ "This is the beamformer unit"
+
parameters:
- { name: g_bf.in_weights_w , value: 16 }
- { name: g_bf.nof_weights , value: 256 }
@@ -18,62 +20,59 @@ peripherals:
mm_ports:
# ram_bf_weights
- - mm_port_name : WEIGHTS
- number_of_mm_ports: g_bf.nof_weights
+ - mm_port_name: WEIGHTS
mm_port_type: RAM
+ mm_port_description: >
+ " "
+ number_of_mm_ports: g_bf.nof_weights
fields:
- - - field_name : bf_weights
- mm_width : g_bf.in_weights_w * c_nof_complex
-
- number_of_fields: g_bf.nof_signal_paths
+ - - field_name: bf_weights
field_description: |
- "Contains the weights.
+ "Contains the weights.
The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
- mm_port_description: >
- " "
+ number_of_fields: g_bf.nof_signal_paths
+ mm_width: g_bf.in_weights_w * c_nof_complex
+
# ram_ss_ss_wide
- - mm_port_name : SS_SS_WIDE
- number_of_mm_ports: g_bf.nof_weights
+ - mm_port_name: SS_SS_WIDE
mm_port_type: RAM
+ mm_port_description: >
+ " "
+ number_of_mm_ports: g_bf.nof_weights
fields:
- - - field_name : ss_ss_wide
- mm_width : 32
- number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
+ - - field_name: ss_ss_wide
field_description: |
"Contains the addresses to select from the stored subbands."
- mm_port_description: >
- " "
+ number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
+ mm_width: 32
# ram_st_sst_bf
- - mm_port_name : ST_SST
- number_of_mm_ports: g_bf.nof_weights
+ - mm_port_name: ST_SST
mm_port_type: RAM
+ mm_port_description: >
+ " "
+ number_of_mm_ports: g_bf.nof_weights
fields:
- - - field_name : st_sst_bf
- mm_width : 56
- number_of_fields: 512
- access_mode : RO
+ - - field_name: st_sst_bf
field_description: |
"Contains the weights.
The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
- mm_port_description: >
- " "
+ number_of_fields: 512
+ mm_width: 56
+ access_mode : RO
# reg_st_sst_bf
- mm_port_name : treshold
- number_of_mm_ports: 1
mm_port_type: REG
+ mm_port_description: >
+ " "
+ number_of_mm_ports: 1
fields:
- - - field_name : treshold
- address_offset: 0x0
- field_description : |
+ - - field_name: treshold
+ field_description: |
"When the treshold register is set to 0 the statistics will be auto-correlations.
In case the treshold register is set to a non-zero value, it allows to create a sample & hold function
for the a-input of the multiplier.
The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created."
- mm_port_description: >
- " "
-
- peripheral_description: |
- "This is the beamformer unit"
+ address_offset: 0x0
diff --git a/libraries/dsp/filter/filter.peripheral.yaml b/libraries/dsp/filter/filter.peripheral.yaml
index 22612d7ff683fcdb124225da2ade001dc1f1e0ef..0e13878acb86d6fbb3315e8cc5692b88869b4225 100644
--- a/libraries/dsp/filter/filter.peripheral.yaml
+++ b/libraries/dsp/filter/filter.peripheral.yaml
@@ -33,6 +33,7 @@ peripherals:
mm_ports:
# MM port for fil_ppf_wide.vhd / fil_ppf_single.vhd
- mm_port_name: RAM_FIL_COEFS
+ mm_port_type: RAM
mm_port_description: |
"The FIR filter coefficients are stored in blocks of g_fil_ppf.nof_bands/g_fil_ppf.wb_factor
real coefficients:
@@ -43,11 +44,10 @@ peripherals:
g_fil_ppf.nof_bands/g_fil_ppf.wb_factor coefficients:
(int16)coefs[g_fil_ppf.nof_taps][g_fil_ppf.nof_bands]"
- mm_port_type: RAM
number_of_mm_ports: g_fil_ppf.wb_factor * g_fil_ppf.nof_taps
fields:
- - field_name: coef
field_description: "Real FIR filter coefficient"
- mm_width: g_fil_ppf.coef_dat_w
- address_offset: 0x0
number_of_fields: g_fil_ppf.nof_bands / g_fil_ppf.wb_factor
+ address_offset: 0x0
+ mm_width: g_fil_ppf.coef_dat_w
diff --git a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
index 67772e418753ee5bfae3ee7530e80abd9be46167..514869711c507f52a70603d41165b33dfb609efa 100644
--- a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
+++ b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
@@ -7,85 +7,56 @@ hdl_library_description: " This is the description for the finge_stop library "
peripherals:
- peripheral_name: fringe_stop
-
- parameters:
- - { name: g_nof_channels, value: 256 }
- - { name: g_fs_offset_w , value: 10 }
- - { name: g_fs_step_w , value: 17 }
-
- mm_ports:
- # actual hdl name: ram_fringe_stop_step
- - mm_port_name : STEP
- mm_port_type : RAM
- fields:
- - - field_name : fringe_stop_step
- mm_width: g_fs_step_w
- number_of_fields: g_nof_channels
- field_description: |
- "Contains the step size for all nof_channels channels."
- mm_port_description: " "
-
- # actual hdl name: fringe_stop_offset
- - mm_port_name : STOP_OFFSET
- mm_port_type : RAM
- fields:
- - - field_name: fringe_stop_offset
- mm_width: g_fs_offset_w
- number_of_fields: g_nof_channels
- field_description: |
- "Contains the offset for all nof_channels channels."
- mm_port_description: " "
-
peripheral_description: |
"The fringe stopping peripheral is based on piecewise linear coefficients. The coefficients are indicated as offset and step.
The offset and step are used to calculate an index that is used to select a certain phase from a look-up table. The look-up
table contains a series of complex values that are based on a sinewave. The length of the look-up table is determined by the
width of the offset RAM (offset_w). If offset_w = 10 then the length of the look-up table is 2^offset_w=1024. In that case
the look-up table contains 1024 complex values that make one sine-wave period.
-
+
The index is determined as follows:
-
+
index(t) = (offset + step*t) MOD 2^offset_w
-
+
Where t ranges from 0 to Tmax-1. Tmax is the number of samples that fit in the control interval (the sync interval).
The fringe stop peripheral is capable to process 1 or more channels in series (nof_channels).
-
+
Accumulation Register
The accumulation register that maintains the accumulated step value is flushed by the sync pulse in the system.
The accumulation register in the Apertif case is 31 bit wide. For the additon of the offset and the accumulated step the
10 (offset_w) highest bit of the accumulated value are used --> offset(9:0) + step_accumulated(30:21).
-
+
RAMs
The fringe stop interface is facilitated by two RAMs:
-
+
-RAM_FRINGE_STOP_OFFSET
-RAM_FRINGE_STOP_STEP
-
+
Both RAMs are implemented as dual-page RAMs.The page swap is triggered by the sync-pulse. The VHDL is always accessing
the page that is NOT accessible for the software and vice-versa. This means that the values that are written to the RAMs
will only be actually used in the following sync-interval:
-
-
- A| _ T0 _ T1 _ T2
+
+
+ A| _ T0 _ T1 _ T2
A| sync __| |___________________________| |___________________________| |________________________
- A| | VHDL uses data T0 | VHDL uses data T1 | VHDL uses data T2
+ A| | VHDL uses data T0 | VHDL uses data T1 | VHDL uses data T2
A| | Software writes data T1 | Software writes data T2 | Software writes data T3
- A| | | |
- A| page_swap page_swap page_swap
-
-
+ A| | | |
+ A| page_swap page_swap page_swap
+
+
The software should be sure to write the next set of data before the sync_interval expires. Keeping track of the
synchronization with the sync-pulse can be done, using one of the BSN Monitors in the system. In the Apertif system
the BSN Monitor at the input of the beamformer can be used.
-
+
The number_of_fields of both RAMs is determined by the number of unique channels that ought to be processed.
-
+
RAM_FRINGE_STOP_OFFSET
This RAM contains the offset values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
defined by the offset_w.
-
+
+-----------------------------------------+
- | RAM_address | RAM_content |
+ | RAM_address | RAM_content |
|-----------------------------------------|
| 0x0 | Offset_Channel_0 |
| 0x1 | Offset_Channel_1 |
@@ -94,13 +65,13 @@ peripherals:
| .. | .. |
| .. | Offset_Channel_Max-1 |
+-----------------------------------------+
-
+
RAM_FRINGE_STOP_STEP
This RAM contains the step size values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
specified by the step_w.
-
+
+-----------------------------------------+
- | RAM_address | RAM_content |
+ | RAM_address | RAM_content |
|-----------------------------------------|
| 0x0 | Step_Channel_0 |
| 0x1 | Step_Channel_1 |
@@ -109,4 +80,30 @@ peripherals:
| .. | .. |
| .. | Step_Channel_Max-1 |
+-----------------------------------------+"
-
+ parameters:
+ - { name: g_nof_channels, value: 256 }
+ - { name: g_fs_offset_w , value: 10 }
+ - { name: g_fs_step_w , value: 17 }
+ mm_ports:
+ # actual hdl name: ram_fringe_stop_step
+ - mm_port_name : STEP
+ mm_port_type : RAM
+ mm_port_description: " "
+ fields:
+ - - field_name : fringe_stop_step
+ field_description: |
+ "Contains the step size for all nof_channels channels."
+ mm_width: g_fs_step_w
+ number_of_fields: g_nof_channels
+
+ # actual hdl name: fringe_stop_offset
+ - mm_port_name : STOP_OFFSET
+ mm_port_type : RAM
+ mm_port_description: " "
+ fields:
+ - - field_name: fringe_stop_offset
+ field_description: |
+ "Contains the offset for all nof_channels channels."
+ number_of_fields: g_nof_channels
+ mm_width: g_fs_offset_w
+
diff --git a/libraries/dsp/si/si.peripheral.yaml b/libraries/dsp/si/si.peripheral.yaml
index d738cebd2225f68bbb139bfa6e46ddea50622cb2..206534545d065f54e4b155f8ba1086225391e6c0 100644
--- a/libraries/dsp/si/si.peripheral.yaml
+++ b/libraries/dsp/si/si.peripheral.yaml
@@ -11,10 +11,10 @@ peripherals:
mm_ports:
# MM port for si_arr.vhd
- mm_port_name: REG_SI
- mm_port_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
mm_port_type: REG
+ mm_port_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
fields:
- - field_name: enable
field_description: "When 0 then pass on the array of input signals, when 1 then enable spectral inversion for all the input signals."
- mm_width: 1
address_offset: 0x0
+ mm_width: 1
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index 4dc16e87c486cf0435606d1e2de5e1acfa7a059c..13bbf592e2000dc1d0336ff519d3f8050e8cdef1 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -22,22 +22,22 @@ peripherals:
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
+ mm_port_type: RAM
mm_port_description: |
"The statistics are calculated for blocks of g_nof_stat time multiplexed data streams.
There are g_nof_instances parallel time multiplexed data streams.
The statistic power values have g_stat_data_w bits. The memory format is:
. g_xst_enable = False, for real powers : (uint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]
. g_xst_enable = True, for complex powers : (cuint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]"
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: power
field_description: ""
+ number_of_fields: g_nof_stat * g_stat_data_sz
+ address_offset: 0x0
mm_width: 32
user_width: g_stat_data_w
radix: uint64
- address_offset: 0x0
- number_of_fields: g_nof_stat * g_stat_data_sz
- peripheral_name: st_sst_for_sdp # pi_st_sst.py
@@ -53,6 +53,7 @@ peripherals:
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
+ mm_port_type: RAM
mm_port_description: |
"The subband statistics per PN are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
N_sub * Q_fft = 512 * 2 = 1024 real values as:
@@ -60,16 +61,15 @@ peripherals:
(uint64)SST[g_nof_instances]_[g_nof_stat] = (uint64)SST[S_pn/Q_fft]_[N_sub][Q_fft]
where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
- mm_port_type: RAM
number_of_mm_ports: g_nof_instances
fields:
- - field_name: power
field_description: ""
+ number_of_fields: g_nof_stat * g_stat_data_sz
+ address_offset: 0x0
mm_width: 32
user_width: g_stat_data_w
radix: uint64
- address_offset: 0x0
- number_of_fields: g_nof_stat * g_stat_data_sz
- peripheral_name: st_bst_for_sdp # pi_st_bst.py
@@ -85,19 +85,19 @@ peripherals:
mm_ports:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
+ mm_port_type: RAM
mm_port_description: |
"The beamlet statistics per PN are stored in 1 block of S_sub_bf * N_pol_bf = 488 * 2 = 976 real values as:
(uint64)BST[g_nof_stat] = (uint64)BST[S_sub_bf][N_pol_bf]
where N_pol_bf = 2 and S_sub_bf = 488 are defined in sdp_pkg.vhd."
- mm_port_type: RAM
number_of_mm_ports: 1
fields:
- - field_name: power
field_description: ""
+ number_of_fields: g_nof_stat * g_stat_data_sz
+ address_offset: 0x0
mm_width: 32
user_width: g_stat_data_w
radix: uint64
- address_offset: 0x0
- number_of_fields: g_nof_stat * g_stat_data_sz
diff --git a/libraries/io/aduh/aduh.peripheral.yaml b/libraries/io/aduh/aduh.peripheral.yaml
index 83c37cd7e7dbad3dd50b3c5dbf5b50aa29378f6e..5f19809c1d61f2637f413ce97ce5adae7f62935b 100644
--- a/libraries/io/aduh/aduh.peripheral.yaml
+++ b/libraries/io/aduh/aduh.peripheral.yaml
@@ -20,20 +20,20 @@ peripherals:
fields:
- - field_name: mean_sum_lo
field_description: "Mean sum[31:0] of samples during a sync interval."
- access_mode: RO
address_offset: 0x0
+ access_mode: RO
- - field_name: mean_sum_hi
field_description: "Mean sum[63:32] of samples during a sync interval."
- access_mode: RO
address_offset: 0x4
+ access_mode: RO
- - field_name: power_sum_lo
field_description: "Power sum[31:0] of sample powers during a sync interval."
- access_mode: RO
address_offset: 0x8
+ access_mode: RO
- - field_name: power_sum_hi
field_description: "Power sum[63:32] of sample powers during a sync interval."
- access_mode: RO
address_offset: 0xC
+ access_mode: RO
- peripheral_name: aduh_mon_data_buffer # pi_aduh_monitor.py
peripheral_description: "Data buffer to capture samples (= diag_data_buffer)"
@@ -53,7 +53,7 @@ peripherals:
fields:
- - field_name: data
field_description: ""
- mm_width: g_symbol_w * g_nof_symbols_per_data
- address_offset: 0x0
number_of_fields: g_buffer_nof_symbols / g_nof_symbols_per_data
+ address_offset: 0x0
+ mm_width: g_symbol_w * g_nof_symbols_per_data
diff --git a/libraries/io/epcs/epcs.peripheral.yaml b/libraries/io/epcs/epcs.peripheral.yaml
index a0cd36b980cbef177fd8c0b0f8a2176cd50768f4..8a0d28ba86093e3888bb6eb6a4b30921ea844c32 100644
--- a/libraries/io/epcs/epcs.peripheral.yaml
+++ b/libraries/io/epcs/epcs.peripheral.yaml
@@ -27,45 +27,45 @@ peripherals:
fields:
- - field_name: addr
field_description: "Address to write to or read from."
+ address_offset: 0x0
mm_width: 24
access_mode: WO
- address_offset: 0x0
- - field_name: rden
field_description: "Read enable bit."
+ address_offset: 0x4
mm_width: 1
access_mode: WO
- address_offset: 0x4
- - field_name: read_bit
field_description: "Read bit."
+ address_offset: 0x8
mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0x8
- - field_name: write_bit
field_description: "Write bit."
+ address_offset: 0xc
mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0xc
- - field_name: sector_erase
field_description: "Sector erase bit."
+ address_offset: 0x10
mm_width: 1
access_mode: WO
- address_offset: 0x10
- - field_name: busy
field_description: "Busy bit."
+ address_offset: 0x14
mm_width: 1
access_mode: RO
- address_offset: 0x14
- - field_name: unprotect
field_description: "Use 0xBEDA221E (= Bedazzle) as password to unprotect address range."
+ address_offset: 0x18
mm_width: 32
access_mode: WO
- address_offset: 0x18
diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
index 5593e60c884be463d06bf6bce75c1443c9f71e7c..e98da05be1818690181856cb6e972b9b8c50b64d 100644
--- a/libraries/io/eth/eth.peripheral.yaml
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -22,9 +22,9 @@ peripherals:
fields:
- - field_name: status
field_description: ""
- access_mode: RO
- address_offset: 0x0
number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
+ address_offset: 0x0
+ access_mode: RO
# MM port for registers in eth_mm_registers.vhd in the ETH module [2]
- mm_port_name: AVS_ETH_0_REG
@@ -33,9 +33,9 @@ peripherals:
fields:
- - field_name: status
field_description: ""
- access_mode: RO
- address_offset: 0x0
number_of_fields: 12 # = c_eth_reg_nof_words in eth_pkg.vhd
+ address_offset: 0x0
+ access_mode: RO
# MM port for ETH packet packet buffers in eth.vhd
- mm_port_name: AVS_ETH_0_RAM
diff --git a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
index 010d51c1dc6d263e6e0324c26fa75aa1275fd0e9..05a3c22d5427bee0324743a72f9ea6294afe1dfa 100644
--- a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
+++ b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
@@ -161,19 +161,19 @@ peripherals:
fields:
- - field_name: tx_snk_out_xon
field_description: ""
+ address_offset: 0x0
mm_width: 1
bit_offset: 0
access_mode: RO
- address_offset: 0x0
- - field_name: xgmii_tx_ready
field_description: ""
+ address_offset: 0x0
mm_width: 1
bit_offset: 1
access_mode: RO
- address_offset: 0x0
- - field_name: xgmii_link_status
field_description: ""
+ address_offset: 0x0
mm_width: 2
bit_offset: 2
access_mode: RO
- address_offset: 0x0
diff --git a/libraries/io/ppsh/ppsh.peripheral.yaml b/libraries/io/ppsh/ppsh.peripheral.yaml
index c04c8fffc46255c29e00d050d890f69558810f5a..4de7dd4254b41f1aa02e2f00609864b434c7277b 100644
--- a/libraries/io/ppsh/ppsh.peripheral.yaml
+++ b/libraries/io/ppsh/ppsh.peripheral.yaml
@@ -27,42 +27,41 @@ peripherals:
fields:
- - field_name: capture_cnt
field_description: "Measured number of clock cycles between captured PPS pulses."
+ address_offset: 0x0
mm_width: 30
bit_offset: 0
access_mode: RO
- address_offset: 0x0
- - field_name: stable
field_description: "PPS is stable (1) when capture_cnt = expected_cnt for all PPS periods since last time status was read, else PPS is not stable (0)."
+ address_offset: 0x0
mm_width: 1
bit_offset: 30
access_mode: RO
- address_offset: 0x0
- - field_name: toggle
field_description: "Level bit that toggles after every PPS."
+ address_offset: 0x0
mm_width: 1
bit_offset: 31
access_mode: RO
- address_offset: 0x0
- - field_name: expected_cnt
field_description: "Expected number of clock cycles between captured PPS pulses."
+ address_offset: 0x4
mm_width: ceil_log2(g_st_clk_freq)
bit_offset: 0
access_mode: RW
- address_offset: 0x4
- - field_name: edge
field_description: "When 0 then clock PPS in on rising edge of clock, else when 1 use falling edge of clock."
+ address_offset: 0x4
mm_width: 1
bit_offset: 31
access_mode: RW
- address_offset: 0x4
- - field_name: offset_cnt
field_description: "Number of clock cycles at read access, that has passed since last PPS."
address_offset: 0x8
mm_width: ceil_log2(g_st_clk_freq)
access_mode: RO
-
diff --git a/libraries/io/remu/remu.peripheral.yaml b/libraries/io/remu/remu.peripheral.yaml
index a2e8775b11d4f7c540ea6fd38a1215051e6c7e81..48608f72751dc1405b74e25861cfdb9b5659b78f 100644
--- a/libraries/io/remu/remu.peripheral.yaml
+++ b/libraries/io/remu/remu.peripheral.yaml
@@ -24,45 +24,44 @@ peripherals:
fields:
- - field_name: reconfigure
field_description: "Use 0xB007FAC7 (= boot factory) as password to reconfigure."
+ address_offset: 0x0
mm_width: c_word_w
access_mode: WO
- address_offset: 0x0
- - field_name: param
field_description: "param"
+ address_offset: 0x4
mm_width: 3
access_mode: WO
- address_offset: 0x4
- - field_name: read_param
field_description: "read_param"
+ address_offset: 0x8
mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0x8
- - field_name: write_param
field_description: "write_param"
+ address_offset: 0xc
mm_width: 1
access_mode: WO
side_effect: PW
- address_offset: 0xc
- - field_name: data_out
field_description: "data_out"
+ address_offset: 0x10
mm_width: g_data_w
access_mode: RO
- address_offset: 0x10
- - field_name: data_in
field_description: "data_in"
+ address_offset: 0x14
mm_width: g_data_w
access_mode: WO
- address_offset: 0x14
- - field_name: busy
field_description: "busy"
+ address_offset: 0x18
mm_width: 1
access_mode: RO
- address_offset: 0x18
-
diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
index 2fe119edf4f93399e7732af647922fc73ed66582..7fe5b2d604102e508778a46ad52f5545bb7ffa41 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
+++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
@@ -16,16 +16,16 @@ peripherals:
fields:
- - field_name: reset
field_description: "Write 1 to reset the full JESD interface for all JESD signal inputs."
- mm_width: 1
+ address_offset: 0x0
bit_offset: 31
+ mm_width: 1
access_mode: RW
- address_offset: 0x0
- - field_name: enable
field_description: "Enable JESD signal input i by setting bit i = 1, disable by clearing bit i = 0."
- mm_width: 31
+ address_offset: 0x0
bit_offset: 0
+ mm_width: 31
access_mode: RW
- address_offset: 0x0
- peripheral_name: jesd204b_arria10 # pi_jesd204b_unb2.py
peripheral_description: |