diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
index 14218e8d3d3e96e1716b2418c849465390c4b3ff..3c6ba74af6f99fb0380ed4b2f20af2faf5a6c63e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -84,6 +84,14 @@ peripherals:
mm_port_names:
- REG_REMU
+ #############################################################################
+ # SDP Info
+ #############################################################################
+
+ - peripheral_name: sdp/sdp_info
+ mm_port_names:
+ - REG_SDP_INFO
+
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
@@ -207,10 +215,6 @@ peripherals:
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
- - peripheral_name: sdp/sdp_info
- mm_port_names:
- - REG_SDP_INFO
-
- peripheral_name: reorder/reorder_col_wide
number_of_peripherals: c_N_beamsets # lofar2_unb2b_beamformer.vhd
parameter_overrides:
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
index c92f08599cc8e1bc8974564f4843ca59843095d4..80806efb43bcce15c07ffad7edb9687ba4f0cc64 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
@@ -1,5 +1,5 @@
fpga_name = lofar2_unb2b_beamformer
-number_of_columns = 11
+number_of_columns = 13
# There can be multiple lines with a single key. The host should ignore unknown keys.
# The lines with columns follow after the number_of_columns keys. The host should ignore
# the extra columns in case the mmap contains more columns than the host expects.
@@ -15,460 +15,458 @@ number_of_columns = 11
# col 9: field radix, if - then it is part of previous field_name.
# col 10: field mm_mask
# col 11: field user_mask, if - then it is same as mm_mask
+# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
+# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
-# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11
-# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ----------
- ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0]
- PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] -
- - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] -
- - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] -
- - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] -
- - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] -
- - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] -
- - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] -
- - - - - info_technology 0x00008000 1 RO uint32 b[31:27] -
- - - - - use_phy 0x00008001 1 RO uint32 b[7:0] -
- - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0]
- - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] -
- - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] -
- - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] -
- - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0]
- PIO_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] -
- RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] -
- AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] -
- AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] -
- AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] -
- PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] -
- - - - - stable 0x00012000 1 RO uint32 b[30:30] -
- - - - - toggle 0x00012000 1 RO uint32 b[31:31] -
- - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] -
- - - - - edge 0x00012001 1 RW uint32 b[31:31] -
- - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] -
- REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] -
- - - - - rden 0x00014001 1 WO uint32 b[0:0] -
- - - - - read_bit 0x00014002 1 WO uint32 b[0:0] -
- - - - - write_bit 0x00014003 1 WO uint32 b[0:0] -
- - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] -
- - - - - busy 0x00014005 1 RO uint32 b[0:0] -
- - - - - unprotect 0x00014006 1 WO uint32 b[31:0] -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] -
- REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] -
- - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] -
- REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] -
- REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] -
- - - - - param 0x0001a001 1 WO uint32 b[2:0] -
- - - - - read_param 0x0001a002 1 WO uint32 b[0:0] -
- - - - - write_param 0x0001a003 1 WO uint32 b[0:0] -
- - - - - data_out 0x0001a004 1 RO uint32 b[23:0] -
- - - - - data_in 0x0001a005 1 WO uint32 b[23:0] -
- - - - - busy 0x0001a006 1 RO uint32 b[0:0] -
- PIO_JESD_CTRL 1 1 REG enable 0x0001c000 1 RW uint32 b[30:0] -
- - - - - reset 0x0001c000 1 RW uint32 b[31:31] -
- JESD204B 1 1 REG rx_dll_ctrl 0x0001e014 1 RW uint32 b[16:0] -
- - - - - rx_syncn_sysref_ctrl 0x0001e015 1 RW uint32 b[24:0] -
- - - - - rx_csr_sysref_always_on 0x0001e015 1 RW uint32 b[1:1] -
- - - - - rx_csr_rbd_offset 0x0001e015 1 RW uint32 b[10:3] -
- - - - - rx_csr_lmfc_offset 0x0001e015 1 RW uint32 b[19:12] -
- - - - - rx_err0 0x0001e018 1 RW uint32 b[8:0] -
- - - - - rx_err1 0x0001e019 1 RW uint32 b[9:0] -
- - - - - csr_dev_syncn 0x0001e020 1 RO uint32 b[0:0] -
- - - - - csr_rbd_count 0x0001e020 1 RO uint32 b[10:3] -
- - - - - rx_status1 0x0001e021 1 RW uint32 b[23:0] -
- - - - - rx_status2 0x0001e022 1 RW uint32 b[23:0] -
- - - - - rx_status3 0x0001e023 1 RW uint32 b[7:0] -
- - - - - rx_ilas_csr_l 0x0001e025 1 RW uint32 b[4:0] -
- - - - - rx_ilas_csr_f 0x0001e025 1 RW uint32 b[15:8] -
- - - - - rx_ilas_csr_k 0x0001e025 1 RW uint32 b[20:16] -
- - - - - rx_ilas_csr_m 0x0001e025 1 RW uint32 b[31:24] -
- - - - - rx_ilas_csr_n 0x0001e026 1 RW uint32 b[4:0] -
- - - - - rx_ilas_csr_cs 0x0001e026 1 RW uint32 b[7:6] -
- - - - - rx_ilas_csr_np 0x0001e026 1 RW uint32 b[12:8] -
- - - - - rx_ilas_csr_subclassv 0x0001e026 1 RW uint32 b[15:13] -
- - - - - rx_ilas_csr_s 0x0001e026 1 RW uint32 b[20:16] -
- - - - - rx_ilas_csr_jesdv 0x0001e026 1 RW uint32 b[23:21] -
- - - - - rx_ilas_csr_cf 0x0001e026 1 RW uint32 b[28:24] -
- - - - - rx_ilas_csr_hd 0x0001e026 1 RW uint32 b[31:31] -
- - - - - rx_status4 0x0001e03c 1 RW uint32 b[15:0] -
- - - - - rx_status5 0x0001e03d 1 RW uint32 b[15:0] -
- - - - - rx_status6 0x0001e03e 1 RW uint32 b[23:0] -
- - - - - rx_status7 0x0001e03f 1 RO uint32 b[31:0] -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00020000 1 RW uint32 b[11:0] -
- REG_BSN_SOURCE 1 1 REG dp_on 0x00022000 1 RW uint32 b[0:0] -
- - - - - dp_on_pps 0x00022000 1 RW uint32 b[1:1] -
- - - - - nof_block_per_sync 0x00022001 1 RW uint32 b[31:0] -
- - - - - bsn 0x00022002 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x00022003 - - - b[31:0] b[63:32]
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00024000 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x00024001 - - - b[31:0] b[63:32]
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00026000 1 RO uint32 b[0:0] -
- - - - - ready_stable 0x00026000 1 RO uint32 b[1:1] -
- - - - - sync_timeout 0x00026000 1 RO uint32 b[2:2] -
- - - - - bsn_at_sync 0x00026001 1 RO uint64 b[31:0] b[31:0]
- - - - - - 0x00026002 - - - b[31:0] b[63:32]
- - - - - nof_sop 0x00026003 1 RO uint32 b[31:0] -
- - - - - nof_valid 0x00026004 1 RO uint32 b[31:0] -
- - - - - nof_err 0x00026005 1 RO uint32 b[31:0] -
- - - - - bsn_first 0x00026006 1 RO uint64 b[31:0] b[31:0]
- - - - - - 0x00026007 - - - b[31:0] b[63:32]
- - - - - bsn_first_cycle_cnt 0x00026008 1 RO uint32 b[31:0] -
- REG_DIAG_WG 1 12 REG mode 0x00028000 1 RW uint32 b[7:0] -
- - - - - nof_samples 0x00028000 1 RW uint32 b[31:16] -
- - - - - phase 0x00028001 1 RW uint32 b[15:0] -
- - - - - freq 0x00028002 1 RW uint32 b[30:0] -
- - - - - ampl 0x00028003 1 RW uint32 b[16:0] -
- RAM_DIAG_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] -
- REG_ADUH_MON 1 12 REG mean_sum_lo 0x00030000 1 RO uint32 b[31:0] -
- - - - - mean_sum_hi 0x00030001 1 RO uint32 b[31:0] -
- - - - - power_sum_lo 0x00030002 1 RO uint32 b[31:0] -
- - - - - power_sum_hi 0x00030003 1 RO uint32 b[31:0] -
- REG_DIAG_DATA_BUF_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] -
- - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] -
- RAM_DIAG_DATA_BUF_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] -
- REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] -
- RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] -
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] -
- REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] -
- RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0]
- - - - - - 0x00042001 - - - b[21:0] b[53:32]
- REG_STAT_ENABLE 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] -
- REG_STAT_HDR_INFO 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x0004a001 - - - b[31:0] b[63:32]
- - - - - block_period 0x0004a002 1 RW uint32 b[15:0] -
- - - - - nof_statistics_per_packet 0x0004a003 1 RW uint32 b[15:0] -
- - - - - nof_bytes_per_statistic 0x0004a004 1 RW uint32 b[7:0] -
- - - - - nof_signal_inputs 0x0004a005 1 RW uint32 b[7:0] -
- - - - - data_id 0x0004a006 1 RW uint32 b[31:0] -
- - - - - data_id_sst_signal_input_index 0x0004a006 1 RW uint32 b[7:0] -
- - - - - data_id_sst_reserved 0x0004a006 1 RW uint32 b[31:8] -
- - - - - integration_interval 0x0004a007 1 RW uint32 b[23:0] -
- - - - - reserved 0x0004a008 1 RW uint32 b[7:0] -
- - - - - source_info 0x0004a009 1 RW uint32 b[15:0] -
- - - - - source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] -
- - - - - source_info_reserved 0x0004a009 1 RW uint32 b[7:5] -
- - - - - source_info_subband_calibrated_flag 0x0004a009 1 RW uint32 b[8:8] -
- - - - - source_info_beam_repositioning_flag 0x0004a009 1 RW uint32 b[9:9] -
- - - - - source_info_payload_error 0x0004a009 1 RW uint32 b[10:10] -
- - - - - source_info_fsub_type 0x0004a009 1 RW uint32 b[11:11] -
- - - - - source_info_f_adc 0x0004a009 1 RW uint32 b[12:12] -
- - - - - source_info_nyquist_zone_index 0x0004a009 1 RW uint32 b[14:13] -
- - - - - source_info_antenna_band_index 0x0004a009 1 RW uint32 b[15:15] -
- - - - - station_id 0x0004a00a 1 RW uint32 b[15:0] -
- - - - - observation_id 0x0004a00b 1 RW uint32 b[31:0] -
- - - - - version_id 0x0004a00c 1 RO uint32 b[7:0] -
- - - - - marker 0x0004a00d 1 RO uint32 b[7:0] -
- - - - - udp_checksum 0x0004a00e 1 RW uint32 b[15:0] -
- - - - - udp_length 0x0004a00f 1 RW uint32 b[15:0] -
- - - - - udp_destination_port 0x0004a010 1 RW uint32 b[15:0] -
- - - - - udp_source_port 0x0004a011 1 RW uint32 b[15:0] -
- - - - - ip_destination_address 0x0004a012 1 RW uint32 b[31:0] -
- - - - - ip_source_address 0x0004a013 1 RW uint32 b[31:0] -
- - - - - ip_header_checksum 0x0004a014 1 RW uint32 b[15:0] -
- - - - - ip_protocol 0x0004a015 1 RW uint32 b[7:0] -
- - - - - ip_time_to_live 0x0004a016 1 RW uint32 b[7:0] -
- - - - - ip_fragment_offset 0x0004a017 1 RW uint32 b[12:0] -
- - - - - ip_flags 0x0004a018 1 RW uint32 b[2:0] -
- - - - - ip_identification 0x0004a019 1 RW uint32 b[15:0] -
- - - - - ip_total_length 0x0004a01a 1 RW uint32 b[15:0] -
- - - - - ip_services 0x0004a01b 1 RW uint32 b[7:0] -
- - - - - ip_header_length 0x0004a01c 1 RW uint32 b[3:0] -
- - - - - ip_version 0x0004a01d 1 RW uint32 b[3:0] -
- - - - - eth_type 0x0004a01e 1 RO uint32 b[15:0] -
- - - - - eth_source_mac 0x0004a01f 1 RO uint64 b[31:0] b[31:0]
- - - - - - 0x0004a020 - - - b[15:0] b[47:32]
- - - - - eth_destination_mac 0x0004a021 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x0004a022 - - - b[15:0] b[47:32]
- - - - - word_align 0x0004a023 1 RW uint32 b[15:0] -
- REG_SDP_INFO 1 1 REG station_id 0x0004c000 1 RW uint32 b[15:0] -
- - - - - antenna_band_index 0x0004c001 1 RO uint32 b[0:0] -
- - - - - observation_id 0x0004c002 1 RW uint32 b[31:0] -
- - - - - nyquist_zone_index 0x0004c003 1 RW uint32 b[1:0] -
- - - - - f_adc 0x0004c004 1 RO uint32 b[0:0] -
- - - - - fsub_type 0x0004c005 1 RO uint32 b[0:0] -
- - - - - beam_repositioning_flag 0x0004c006 1 RW uint32 b[0:0] -
- - - - - subband_calibrated_flag 0x0004c007 1 RW uint32 b[0:0] -
- - - - - o_si 0x0004c008 1 RW uint32 b[7:0] -
- - - - - n_si 0x0004c009 1 RW uint32 b[7:0] -
- - - - - o_rn 0x0004c00a 1 RW uint32 b[7:0] -
- - - - - n_rn 0x0004c00b 1 RW uint32 b[7:0] -
- - - - - block_period 0x0004c00c 1 RO uint32 b[15:0] -
- - - - - beamlet_scale 0x0004c00d 1 RW uint32 b[15:0] -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0004e000 976 RW uint32 b[9:0] -
- RAM_BF_WEIGHTS 2 12 RAM data 0x00054000 976 RW cint16_ir b[31:0] -
- REG_BF_SCALE 2 1 REG scale 0x0005c000 1 RW uint32 b[15:0] -
- - - - - unused 0x0005c001 1 RW uint32 b[31:0] -
- REG_HDR_DAT 2 1 REG bsn 0x0005e000 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x0005e001 - - - b[31:0] b[63:32]
- - - - - block_period 0x0005e002 1 RW uint32 b[15:0] -
- - - - - nof_beamlets_per_block 0x0005e003 1 RW uint32 b[15:0] -
- - - - - nof_blocks_per_packet 0x0005e004 1 RW uint32 b[7:0] -
- - - - - beamlet_index 0x0005e005 1 RW uint32 b[15:0] -
- - - - - beamlet_scale 0x0005e006 1 RW uint32 b[15:0] -
- - - - - reserved 0x0005e007 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x0005e008 - - - b[7:0] b[39:32]
- - - - - source_info 0x0005e009 1 RW uint32 b[15:0] -
- - - - - source_info_gn_index 0x0005e009 1 RW uint32 b[4:0] -
- - - - - source_info_beamlet_width 0x0005e009 1 RW uint32 b[7:5] -
- - - - - source_info_repositioning_flag 0x0005e009 1 RW uint32 b[9:9] -
- - - - - source_info_payload_error 0x0005e009 1 RW uint32 b[10:10] -
- - - - - source_info_fsub_type 0x0005e009 1 RW uint32 b[11:11] -
- - - - - source_info_f_adc 0x0005e009 1 RW uint32 b[12:12] -
- - - - - source_info_nyquist_zone_index 0x0005e009 1 RW uint32 b[14:13] -
- - - - - source_info_antenna_band_index 0x0005e009 1 RW uint32 b[15:15] -
- - - - - station_id 0x0005e00a 1 RW uint32 b[15:0] -
- - - - - observation_id 0x0005e00b 1 RW uint32 b[31:0] -
- - - - - version_id 0x0005e00c 1 RO uint32 b[7:0] -
- - - - - marker 0x0005e00d 1 RO uint32 b[7:0] -
- - - - - udp_checksum 0x0005e00e 1 RW uint32 b[15:0] -
- - - - - udp_length 0x0005e00f 1 RW uint32 b[15:0] -
- - - - - udp_destination_port 0x0005e010 1 RW uint32 b[15:0] -
- - - - - udp_source_port 0x0005e011 1 RW uint32 b[15:0] -
- - - - - ip_destination_address 0x0005e012 1 RW uint32 b[31:0] -
- - - - - ip_source_address 0x0005e013 1 RW uint32 b[31:0] -
- - - - - ip_header_checksum 0x0005e014 1 RW uint32 b[15:0] -
- - - - - ip_protocol 0x0005e015 1 RW uint32 b[7:0] -
- - - - - ip_time_to_live 0x0005e016 1 RW uint32 b[7:0] -
- - - - - ip_fragment_offset 0x0005e017 1 RW uint32 b[12:0] -
- - - - - ip_flags 0x0005e018 1 RW uint32 b[2:0] -
- - - - - ip_identification 0x0005e019 1 RW uint32 b[15:0] -
- - - - - ip_total_length 0x0005e01a 1 RW uint32 b[15:0] -
- - - - - ip_services 0x0005e01b 1 RW uint32 b[7:0] -
- - - - - ip_header_length 0x0005e01c 1 RW uint32 b[3:0] -
- - - - - ip_version 0x0005e01d 1 RW uint32 b[3:0] -
- - - - - eth_type 0x0005e01e 1 RO uint32 b[15:0] -
- - - - - eth_source_mac 0x0005e01f 1 RO uint64 b[31:0] b[31:0]
- - - - - - 0x0005e020 - - - b[15:0] b[47:32]
- - - - - eth_destination_mac 0x0005e021 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x0005e022 - - - b[15:0] b[47:32]
- REG_DP_XONOFF 2 1 REG enable_stream 0x00060000 1 RW uint32 b[0:0] -
- RAM_ST_BST 2 1 RAM data 0x00062000 1952 RW uint64 b[31:0] b[31:0]
- - - - - - 0x00060001 - - - b[21:0] b[53:32]
- REG_STAT_ENABLE_BST 1 1 REG enable 0x00064000 1 RW uint32 b[0:0] -
- REG_STAT_HDR_INFO_BST 1 1 REG bsn 0x00066000 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x00066001 - - - b[31:0] b[63:32]
- - - - - block_period 0x00066002 1 RW uint32 b[15:0] -
- - - - - nof_statistics_per_packet 0x00066003 1 RW uint32 b[15:0] -
- - - - - nof_bytes_per_statistic 0x00066004 1 RW uint32 b[7:0] -
- - - - - nof_signal_inputs 0x00066005 1 RW uint32 b[7:0] -
- - - - - data_id 0x00066006 1 RW uint32 b[31:0] -
- - - - - data_id_bst_beamlet_index 0x00066006 1 RW uint32 b[15:0] -
- - - - - data_id_bst_reserved 0x00066006 1 RW uint32 b[31:16] -
- - - - - integration_interval 0x00066007 1 RW uint32 b[23:0] -
- - - - - reserved 0x00066008 1 RW uint32 b[7:0] -
- - - - - source_info 0x00066009 1 RW uint32 b[15:0] -
- - - - - source_info_gn_index 0x00066009 1 RW uint32 b[4:0] -
- - - - - source_info_reserved 0x00066009 1 RW uint32 b[7:5] -
- - - - - source_info_subband_calibrated_flag 0x00066009 1 RW uint32 b[8:8] -
- - - - - source_info_beam_repositioning_flag 0x00066009 1 RW uint32 b[9:9] -
- - - - - source_info_payload_error 0x00066009 1 RW uint32 b[10:10] -
- - - - - source_info_fsub_type 0x00066009 1 RW uint32 b[11:11] -
- - - - - source_info_f_adc 0x00066009 1 RW uint32 b[12:12] -
- - - - - source_info_nyquist_zone_index 0x00066009 1 RW uint32 b[14:13] -
- - - - - source_info_antenna_band_index 0x00066009 1 RW uint32 b[15:15] -
- - - - - station_id 0x0006600a 1 RW uint32 b[15:0] -
- - - - - observation_id 0x0006600b 1 RW uint32 b[31:0] -
- - - - - version_id 0x0006600c 1 RO uint32 b[7:0] -
- - - - - marker 0x0006600d 1 RO uint32 b[7:0] -
- - - - - udp_checksum 0x0006600e 1 RW uint32 b[15:0] -
- - - - - udp_length 0x0006600f 1 RW uint32 b[15:0] -
- - - - - udp_destination_port 0x00066010 1 RW uint32 b[15:0] -
- - - - - udp_source_port 0x00066011 1 RW uint32 b[15:0] -
- - - - - ip_destination_address 0x00066012 1 RW uint32 b[31:0] -
- - - - - ip_source_address 0x00066013 1 RW uint32 b[31:0] -
- - - - - ip_header_checksum 0x00066014 1 RW uint32 b[15:0] -
- - - - - ip_protocol 0x00066015 1 RW uint32 b[7:0] -
- - - - - ip_time_to_live 0x00066016 1 RW uint32 b[7:0] -
- - - - - ip_fragment_offset 0x00066017 1 RW uint32 b[12:0] -
- - - - - ip_flags 0x00066018 1 RW uint32 b[2:0] -
- - - - - ip_identification 0x00066019 1 RW uint32 b[15:0] -
- - - - - ip_total_length 0x0006601a 1 RW uint32 b[15:0] -
- - - - - ip_services 0x0006601b 1 RW uint32 b[7:0] -
- - - - - ip_header_length 0x0006601c 1 RW uint32 b[3:0] -
- - - - - ip_version 0x0006601d 1 RW uint32 b[3:0] -
- - - - - eth_type 0x0006601e 1 RO uint32 b[15:0] -
- - - - - eth_source_mac 0x0006601f 1 RO uint64 b[31:0] b[31:0]
- - - - - - 0x00066020 - - - b[15:0] b[47:32]
- - - - - eth_destination_mac 0x00066021 1 RW uint64 b[31:0] b[31:0]
- - - - - - 0x00066022 - - - b[15:0] b[47:32]
- - - - - word_align 0x00066023 1 RW uint32 b[15:0] -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00068000 1 RW uint32 b[0:0] -
- - - - - rx_transfer_status 0x00068001 1 RO uint32 b[0:0] -
- - - - - tx_transfer_control 0x00068002 1 RW uint32 b[0:0] -
- - - - - rx_padcrc_control 0x00068040 1 RW uint32 b[1:0] -
- - - - - rx_crccheck_control 0x00068080 1 RW uint32 b[1:0] -
- - - - - rx_pktovrflow_error 0x000680c0 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x000680c1 - - - b[31:0] b[31:0]
- - - - - rx_pktovrflow_etherstatsdropevents 0x000680c2 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x000680c3 - - - b[31:0] b[31:0]
- - - - - rx_lane_decoder_preamble_control 0x00068100 1 RW uint32 b[0:0] -
- - - - - rx_preamble_inserter_control 0x00068140 1 RW uint32 b[0:0] -
- - - - - rx_frame_control 0x00068800 1 RW uint32 b[19:0] -
- - - - - rx_frame_maxlength 0x00068801 1 RW uint32 b[15:0] -
- - - - - rx_frame_addr0 0x00068802 1 RW uint32 b[15:0] -
- - - - - rx_frame_addr1 0x00068803 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr0_0 0x00068804 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr0_1 0x00068805 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr1_0 0x00068806 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr1_1 0x00068807 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr2_0 0x00068808 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr2_1 0x00068809 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr3_0 0x0006880a 1 RW uint32 b[15:0] -
- - - - - rx_frame_spaddr3_1 0x0006880b 1 RW uint32 b[15:0] -
- - - - - rx_pfc_control 0x00068818 1 RW uint32 b[16:0] -
- - - - - rx_stats_clr 0x00068c00 1 RW uint32 b[0:0] -
- - - - - rx_stats_framesok 0x00068c02 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c03 - - - b[31:0] b[31:0]
- - - - - rx_stats_frameserr 0x00068c04 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c05 - - - b[31:0] b[31:0]
- - - - - rx_stats_framescrcerr 0x00068c06 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c07 - - - b[31:0] b[31:0]
- - - - - rx_stats_octetsok 0x00068c08 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c09 - - - b[31:0] b[31:0]
- - - - - rx_stats_pausemacctrl_frames 0x00068c0a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c0b - - - b[31:0] b[31:0]
- - - - - rx_stats_iferrors 0x00068c0c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c0d - - - b[31:0] b[31:0]
- - - - - rx_stats_unicast_framesok 0x00068c0e 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c0f - - - b[31:0] b[31:0]
- - - - - rx_stats_unicast_frameserr 0x00068c10 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c11 - - - b[31:0] b[31:0]
- - - - - rx_stats_multicastframesok 0x00068c12 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c13 - - - b[31:0] b[31:0]
- - - - - rx_stats_multicast_frameserr 0x00068c14 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c15 - - - b[31:0] b[31:0]
- - - - - rx_stats_broadcastframesok 0x00068c16 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c17 - - - b[31:0] b[31:0]
- - - - - rx_stats_broadcast_frameserr 0x00068c18 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c19 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstatsoctets 0x00068c1a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c1b - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstatspkts 0x00068c1c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c1d - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_undersizepkts 0x00068c1e 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c1f - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_oversizepkts 0x00068c20 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c21 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_pkts64octets 0x00068c22 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c23 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_pkts65to127octets 0x00068c24 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c25 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_pkts128to255octets 0x00068c26 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c27 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_pkts256to511octets 0x00068c28 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c29 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00068c2a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c2b - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00068c2c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c2d - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00068c2e 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c2f - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_fragments 0x00068c30 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c31 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstats_jabbers 0x00068c32 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c33 - - - b[31:0] b[31:0]
- - - - - rx_stats_etherstatscrcerr 0x00068c34 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c35 - - - b[31:0] b[31:0]
- - - - - rx_stats_unicastmacctrlframes 0x00068c36 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c37 - - - b[31:0] b[31:0]
- - - - - rx_stats_multicastmac_ctrlframes 0x00068c38 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c39 - - - b[31:0] b[31:0]
- - - - - rx_stats_broadcastmac_ctrlframes 0x00068c3a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c3b - - - b[31:0] b[31:0]
- - - - - rx_stats_pfcmacctrlframes 0x00068c3c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00068c3d - - - b[31:0] b[31:0]
- - - - - tx_transfer_status 0x00069001 1 RO uint32 b[0:0] -
- - - - - tx_padins_control 0x00069040 1 RW uint32 b[0:0] -
- - - - - tx_crcins_control 0x00069080 1 RW uint32 b[1:0] -
- - - - - tx_pktunderflow_error 0x000690c0 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x000690c1 - - - b[31:0] b[31:0]
- - - - - tx_preamble_control 0x00069100 1 RW uint32 b[0:0] -
- - - - - tx_pauseframe_control 0x00069140 1 RW uint32 b[1:0] -
- - - - - tx_pauseframe_quanta 0x00069141 1 RW uint32 b[15:0] -
- - - - - tx_pauseframe_enable 0x00069142 1 RW uint32 b[0:0] -
- - - - - pfc_pause_quanta_0 0x00069180 1 RW uint32 b[31:0] -
- - - - - pfc_pause_quanta_1 0x00069181 1 RW uint32 b[31:0] -
- - - - - pfc_pause_quanta_2 0x00069182 1 RW uint32 b[31:0] -
- - - - - pfc_pause_quanta_3 0x00069183 1 RW uint32 b[31:0] -
- - - - - pfc_pause_quanta_4 0x00069184 1 RW uint32 b[31:0] -
- - - - - pfc_pause_quanta_5 0x00069185 1 RW uint32 b[31:0] -
- - - - - pfc_pause_quanta_6 0x00069186 1 RW uint32 b[31:0] -
- - - - - pfc_pause_quanta_7 0x00069187 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_0 0x00069190 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_1 0x00069191 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_2 0x00069192 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_3 0x00069193 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_4 0x00069194 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_5 0x00069195 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_6 0x00069196 1 RW uint32 b[31:0] -
- - - - - pfc_holdoff_quanta_7 0x00069197 1 RW uint32 b[31:0] -
- - - - - tx_pfc_priority_enable 0x000691a0 1 RW uint32 b[7:0] -
- - - - - tx_addrins_control 0x00069200 1 RW uint32 b[0:0] -
- - - - - tx_addrins_macaddr0 0x00069201 1 RW uint32 b[31:0] -
- - - - - tx_addrins_macaddr1 0x00069202 1 RW uint32 b[15:0] -
- - - - - tx_frame_maxlength 0x00069801 1 RW uint32 b[15:0] -
- - - - - tx_stats_clr 0x00069c00 1 RW uint32 b[0:0] -
- - - - - tx_stats_framesok 0x00069c02 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c03 - - - b[31:0] b[31:0]
- - - - - tx_stats_frameserr 0x00069c04 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c05 - - - b[31:0] b[31:0]
- - - - - tx_stats_framescrcerr 0x00069c06 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c07 - - - b[31:0] b[31:0]
- - - - - tx_stats_octetsok 0x00069c08 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c09 - - - b[31:0] b[31:0]
- - - - - tx_stats_pausemacctrl_frames 0x00069c0a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c0b - - - b[31:0] b[31:0]
- - - - - tx_stats_iferrors 0x00069c0c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c0d - - - b[31:0] b[31:0]
- - - - - tx_stats_unicast_framesok 0x00069c0e 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c0f - - - b[31:0] b[31:0]
- - - - - tx_stats_unicast_frameserr 0x00069c10 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c11 - - - b[31:0] b[31:0]
- - - - - tx_stats_multicastframesok 0x00069c12 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c13 - - - b[31:0] b[31:0]
- - - - - tx_stats_multicast_frameserr 0x00069c14 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c15 - - - b[31:0] b[31:0]
- - - - - tx_stats_broadcastframesok 0x00069c16 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c17 - - - b[31:0] b[31:0]
- - - - - tx_stats_broadcast_frameserr 0x00069c18 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c19 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstatsoctets 0x00069c1a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c1b - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstatspkts 0x00069c1c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c1d - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_undersizepkts 0x00069c1e 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c1f - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_oversizepkts 0x00069c20 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c21 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_pkts64octets 0x00069c22 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c23 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_pkts65to127octets 0x00069c24 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c25 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_pkts128to255octets 0x00069c26 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c27 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_pkts256to511octets 0x00069c28 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c29 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00069c2a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c2b - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00069c2c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c2d - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00069c2e 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c2f - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_fragments 0x00069c30 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c31 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstats_jabbers 0x00069c32 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c33 - - - b[31:0] b[31:0]
- - - - - tx_stats_etherstatscrcerr 0x00069c34 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c35 - - - b[31:0] b[31:0]
- - - - - tx_stats_unicastmacctrlframes 0x00069c36 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c37 - - - b[31:0] b[31:0]
- - - - - tx_stats_multicastmac_ctrlframes 0x00069c38 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c39 - - - b[31:0] b[31:0]
- - - - - tx_stats_broadcastmac_ctrlframes 0x00069c3a 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c3b - - - b[31:0] b[31:0]
- - - - - tx_stats_pfcmacctrlframes 0x00069c3c 1 RO uint64 b[3:0] b[35:32]
- - - - - - 0x00069c3d - - - b[31:0] b[31:0]
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0006a000 1 RO uint32 b[0:0] -
- - - - - xgmii_tx_ready 0x0006a000 1 RO uint32 b[1:1] -
- - - - - xgmii_link_status 0x0006a000 1 RO uint32 b[3:2] -
\ No newline at end of file
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG beamlet_scale 0x0001c000 1 RW uint32 b[15:0] - - -
+ - - - - block_period 0x0001c001 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0001c002 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0001c003 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0001c004 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0001c005 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0001c006 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0001c007 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0001c008 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0001c009 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0001c00a 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0001c00b 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0001c00c 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
+ JESD204B 1 1 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - 12 1
+ REG_BSN_SOURCE 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
+ - - - - nof_block_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
+ - - - - bsn 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
+ REG_DIAG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - 48 4
+ - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
+ RAM_DIAG_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - 16384 1024
+ REG_ADUH_MON 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] 48 4
+ - - - - - 0x00030001 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00030002 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00030003 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUF_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - 24 2
+ - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUF_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - 16384 1024
+ REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - 16384 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - 8192 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] 16384 2048
+ - - - - - 0x00042001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_INFO 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0004a002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x0004a003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x0004a004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x0004a005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0004a006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x0004a006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x0004a006 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x0004a007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0004a008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0004a00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0004a00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004a00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004a00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004a00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004a010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0004a011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0004a012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0004a013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0004a014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0004a015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0004a016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0004a017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0004a018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0004a019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004a01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004a01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004a01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004a01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004a01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004a01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004a020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0004a021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0004a022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0004a023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0004a024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0004a025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0004a026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0004a027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0004a029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0004a02b 1 RW uint32 b[15:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0004c000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00050000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00058000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00058001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x0005a000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0005a001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0005a002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x0005a003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x0005a004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x0005a005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x0005a006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x0005a007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x0005a009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0005a00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0005a00b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0005a00c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0005a00d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0005a00e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0005a00f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0005a010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0005a011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0005a012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0005a013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0005a014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0005a015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0005a016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0005a017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0005a018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0005a019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0005a01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0005a01b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0005a01c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0005a01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0005a01e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0005a01f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0005a020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0005a021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0005a022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0005a023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0005a024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0005a025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0005a026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0005a028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005a029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0005c000 1 RW uint32 b[0:0] - 1 1
+ RAM_ST_BST 1 1 RAM data 0x0005e000 1952 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0005c001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 1 1 REG enable 0x00060000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_INFO_BST 1 1 REG bsn 0x00062000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00062002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00062003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00062004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00062005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00062006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00062006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00062006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00062007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00062008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00062009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0006200a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0006200b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0006200c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0006200d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0006200e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0006200f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00062010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00062011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00062012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00062013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00062014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00062015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00062016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00062017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00062018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00062019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0006201a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0006201b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0006201c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0006201d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0006201e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0006201f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00062020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00062021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00062022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00062023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00062024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00062025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00062026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00062027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00062029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006202a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0006202b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00064000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00064001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00064002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00064040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00064080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000640c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000640c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000640c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000640c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00064100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00064140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00064800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00064801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00064802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00064803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00064804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00064805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00064806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00064807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00064808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00064809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0006480a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0006480b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00064818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00064c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00064c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00064c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00064c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00064c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00064c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00064c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00064c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00064c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00064c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00064c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00064c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00064c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00064c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00064c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00064c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00064c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00064c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00064c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00064c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00064c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00064c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00064c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00064c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00064c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00064c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00064c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00064c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00064c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00064c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00064c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00064c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00065001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00065040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00065080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000650c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000650c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00065100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00065140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00065141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00065142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00065180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00065181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00065182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00065183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00065184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00065185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00065186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00065187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00065190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00065191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00065192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00065193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00065194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00065195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00065196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00065197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000651a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00065200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00065201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00065202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00065801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00065c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00065c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00065c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00065c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00065c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00065c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00065c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00065c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00065c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00065c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00065c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00065c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00065c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00065c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00065c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00065c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00065c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00065c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00065c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00065c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00065c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00065c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00065c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00065c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00065c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00065c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00065c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00065c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00065c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00065c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00065c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00065c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00066000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00066000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00066000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 5bb941d05775856b5417be5bc07050ff9ee45607..80766f3196f427ce134a766ca36eeccbb897c65e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -28,20 +28,20 @@ parameters:
- { name: c_W_sub_weight, value: 16 }
- { name: c_W_bf_weight, value: 16 }
- { name: c_W_beamlet_scale, value: 16 }
- - { name: c_W_beamlet_resolution, value: 0 - 15 } # EK: FIXME support passing on negative values, workaround use 0 - positive
+ - { name: c_W_beamlet_resolution, value: 0 - 15 } # EK: FIXME: support passing on negative values, workaround use 0 - positive
- { name: c_W_beamlet, value: 8 }
+ - { name: c_stat_data_sz, value: 2 }
- { name: c_nof_clk_per_pps, value: c_f_adc_MHz * 10**6 } # = 200000000
- - { name: c_nof_block_per_sync, value: 195313 } # TBD temporarily use 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval, TODO: remove when REG_BSN_SOURCE_V2 is used
peripherals:
#############################################################################
# Factory / minimal (see ctrl_unb2b_board.vhd)
#############################################################################
- peripheral_name: unb2b_board/system_info
+ lock_base_address: 0x10000
mm_port_names:
- ROM_SYSTEM_INFO
- PIO_SYSTEM_INFO
- lock_base_address: 0x10000
- peripheral_name: unb2b_board/wdi
mm_port_names:
@@ -84,6 +84,14 @@ peripherals:
mm_port_names:
- REG_REMU
+ #############################################################################
+ # SDP Info
+ #############################################################################
+
+ - peripheral_name: sdp/sdp_info
+ mm_port_names:
+ - REG_SDP_INFO
+
#############################################################################
# AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
#############################################################################
@@ -165,9 +173,12 @@ peripherals:
- peripheral_name: filter/fil_ppf_w
parameter_overrides:
- - { name: g_nof_taps, value: c_N_taps }
- - { name: g_nof_bands, value: c_N_fft }
- - { name: g_coef_dat_w, value: c_W_fir_coef }
+ - { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate (so no parallel wideband factor)
+ - { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate (so no serial time multiplexing)
+ - { name: g_fil_ppf.nof_bands, value: c_N_fft }
+ - { name: g_fil_ppf.nof_taps, value: c_N_taps }
+ - { name: g_fil_ppf.nof_streams, value: 1 }
+ - { name: g_fil_ppf.coef_dat_w, value: c_W_fir_coef }
mm_port_names:
- RAM_FIL_COEFS
@@ -192,17 +203,35 @@ peripherals:
peripheral_group: sst
mm_port_names:
- REG_STAT_HDR_DAT_SST
-
+
#############################################################################
- # BF = Beamformer (from node_sdp_beamformer.vhd)
+ # Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
- - peripheral_name: sdp/sdp_info
+ - peripheral_name: dp/dp_bsn_scheduler
+ peripheral_group: xsub
mm_port_names:
- - REG_SDP_INFO
+ - REG_BSN_SCHEDULER_XSUB
+
+ - peripheral_name: dp/dp_sync_insert_v2
+ mm_port_names:
+ - REG_DP_SYNC_INSERT_V2
+ - peripheral_name: st/st_xst_for_sdp
+ mm_port_names:
+ - RAM_ST_XSQ
+
+ - peripheral_name: sdp/sdp_crosslets_subband_select
+ mm_port_names:
+ - REG_CROSSLETS_INFO
+
+ #############################################################################
+ # BF = Beamformer (from node_sdp_beamformer.vhd)
+ #############################################################################
+
- peripheral_name: reorder/reorder_col_wide
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: ceil_pow2(c_P_pfb) * ceil_pow2(c_S_sub_bf * c_Q_fft) * MM_BUS_SIZE # number_of_ports = c_P_pfb, mm_port_span = ceil_pow2(c_S_sub_bf * c_Q_fft) words
parameter_overrides:
- { name: g_wb_factor, value: c_P_pfb }
- { name: g_nof_ch_in, value: c_N_sub * c_Q_fft }
@@ -211,15 +240,14 @@ peripherals:
- RAM_SS_SS_WIDE
- peripheral_name: sdp/sdp_bf_weights
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
- parameter_overrides:
- - { name: g_nof_instances, value: c_N_pol_bf * c_A_pn } # A_pn = P_pfb = 6
- - { name: g_nof_gains, value: c_N_pol * c_S_sub_bf } # N_pol = Q_fft = 2
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: ceil_pow2(c_N_pol_bf * c_P_pfb) * ceil_pow2(c_Q_fft * c_S_sub_bf) * MM_BUS_SIZE # number_of_ports = c_N_pol_bf * c_P_pfb, mm_port_span = ceil_pow2(c_Q_fft * c_S_sub_bf) words
mm_port_names:
- RAM_BF_WEIGHTS
- peripheral_name: sdp/sdp_bf_scale
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
parameter_overrides:
- { name: g_gain_w, value: c_W_beamlet_scale }
- { name: g_lsb_w, value: 0 - c_W_beamlet_resolution}
@@ -227,12 +255,14 @@ peripherals:
- REG_BF_SCALE
- peripheral_name: sdp/sdp_beamformer_output_hdr_dat
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
mm_port_names:
- REG_HDR_DAT
- peripheral_name: dp/dp_xonoff
- number_of_peripherals: c_N_beamsets # lofar2_unb2b_sdp_station.vhd
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
parameter_overrides:
- { name: g_nof_streams, value: 1 }
- { name: g_combine_streams, value: False }
@@ -240,28 +270,24 @@ peripherals:
- REG_DP_XONOFF
- peripheral_name: st/st_bst_for_sdp
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) words
mm_port_names:
- RAM_ST_BST
-
- - peripheral_name: common/common_variable_delay
- peripheral_group: bst
- mm_port_names:
- - REG_STAT_ENABLE_BST_0
- - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
- peripheral_group: bst
- mm_port_names:
- - REG_STAT_HDR_DAT_BST_0
-
- peripheral_name: common/common_variable_delay
peripheral_group: bst
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
mm_port_names:
- - REG_STAT_ENABLE_BST_1
+ - REG_STAT_ENABLE_BST
- peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
peripheral_group: bst
+ number_of_peripherals: c_N_beamsets
+ peripheral_span: 64 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 64 words
mm_port_names:
- - REG_STAT_HDR_DAT_BST_1
+ - REG_STAT_HDR_DAT_BST
- peripheral_name: nw_10GbE/nw_10GbE_unb2legacy
peripheral_group: beamlet_output
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
new file mode 100644
index 0000000000000000000000000000000000000000..9615fdd98905e0d2be37c9f346534d828adbd8bf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -0,0 +1,480 @@
+fpga_name = lofar2_unb2b_sdp_station
+number_of_columns = 13
+# There can be multiple lines with a single key. The host should ignore unknown keys.
+# The lines with columns follow after the number_of_columns keys. The host should ignore
+# the extra columns in case the mmap contains more columns than the host expects.
+#
+# col 1: mm_port_name, if - then it is part of previous MM port.
+# col 2: number of peripherals, if - then it is part of previous peripheral.
+# col 3: number of mm_ports, if - then it is part of previous MM port.
+# col 4: mm_port_type, if - then it is part of previous MM port.
+# col 5: field_name
+# col 6: field start address (in MM words)
+# col 7: number of fields, if - then it is part of previous field_name.
+# col 8: field access_mode, if - then it is part of previous field_name.
+# col 9: field radix, if - then it is part of previous field_name.
+# col 10: field mm_mask
+# col 11: field user_mask, if - then it is same as mm_mask
+# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
+# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
+#
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG beamlet_scale 0x0001c000 1 RW uint32 b[15:0] - - -
+ - - - - block_period 0x0001c001 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x0001c002 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x0001c003 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x0001c004 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x0001c005 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x0001c006 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x0001c007 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x0001c008 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x0001c009 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x0001c00a 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x0001c00b 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x0001c00c 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
+ JESD204B 1 1 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
+ - - - - nof_block_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00030000 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x00030001 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00030002 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00030003 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00032000 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00032001 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00034000 1024 RW uint32 b[15:0] - - 1024
+ REG_SI 1 1 REG enable 0x00038000 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x0003c000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x00042000 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00044000 2048 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x00042001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x00048000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004a000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x0004a002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x0004a003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x0004a004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x0004a005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0004a006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x0004a006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x0004a006 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x0004a007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0004a008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0004a00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0004a00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004a00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004a00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004a00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004a010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0004a011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0004a012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0004a013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0004a014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0004a015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0004a016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0004a017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0004a018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0004a019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004a01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004a01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004a01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004a01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004a01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004a01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004a020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0004a021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0004a022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0004a023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0004a024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0004a025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0004a026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0004a027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0004a029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004a02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0004a02b 1 RW uint32 b[15:0] - - -
+ REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x0004c000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004c001 - - - b[31:0] b[63:32] - -
+ REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0004e000 1 RW uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 1 RAM data 0x00050000 576 RW cint64_ir b[31:0] b[31:0] - -
+ - - - - - 0x0004e001 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00052000 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0005200f 1 RW uint32 b[31:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00054000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00058000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x00060000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00060001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00062000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00062001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00062002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00062003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00062004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00062005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00062006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00062007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00062009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0006200a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0006200b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0006200c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0006200d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0006200e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0006200f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00062010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00062011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00062012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00062013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00062014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00062015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00062016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00062017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00062018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00062019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0006201a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0006201b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0006201c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0006201d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0006201e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0006201f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00062020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00062021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00062022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00062023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00062024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00062025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00062026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00062028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00062029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00064000 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00066000 1952 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x00064001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x00068000 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x0006a000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x0006a001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x0006a002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x0006a003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x0006a004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x0006a005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x0006a006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x0006a006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x0006a006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x0006a007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x0006a008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x0006a009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0006a00a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0006a00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0006a00c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0006a00d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0006a00e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0006a00f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0006a010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x0006a011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x0006a012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x0006a013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x0006a014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x0006a015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x0006a016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x0006a017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x0006a018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x0006a019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0006a01a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0006a01b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0006a01c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0006a01d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0006a01e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0006a01f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0006a020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x0006a021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x0006a022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x0006a023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x0006a024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x0006a025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x0006a026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x0006a027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006a028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x0006a029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0006a02a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0006a02b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x0006c000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x0006c001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x0006c002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x0006c040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x0006c080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x0006c0c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006c0c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x0006c0c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006c0c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x0006c100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x0006c140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x0006c800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x0006c801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x0006c802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x0006c803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x0006c804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x0006c805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x0006c806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x0006c807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x0006c808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x0006c809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0006c80a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0006c80b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x0006c818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x0006cc00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x0006cc02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x0006cc04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x0006cc06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x0006cc08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x0006cc0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x0006cc0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x0006cc0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x0006cc10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x0006cc12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x0006cc14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x0006cc16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x0006cc18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x0006cc1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x0006cc1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x0006cc1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x0006cc20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x0006cc22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x0006cc24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x0006cc26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x0006cc28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x0006cc2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x0006cc2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x0006cc2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x0006cc30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x0006cc32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x0006cc34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x0006cc36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x0006cc38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x0006cc3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x0006cc3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006cc3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x0006d001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x0006d040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x0006d080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x0006d0c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006d0c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x0006d100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x0006d140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x0006d141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x0006d142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x0006d180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x0006d181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x0006d182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x0006d183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x0006d184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x0006d185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x0006d186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x0006d187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x0006d190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x0006d191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x0006d192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x0006d193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x0006d194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x0006d195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x0006d196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x0006d197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x0006d1a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x0006d200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x0006d201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x0006d202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x0006d801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x0006dc00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x0006dc02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x0006dc04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x0006dc06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x0006dc08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x0006dc0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x0006dc0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x0006dc0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x0006dc10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x0006dc12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x0006dc14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x0006dc16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x0006dc18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x0006dc1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x0006dc1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x0006dc1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x0006dc20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x0006dc22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x0006dc24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x0006dc26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x0006dc28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x0006dc2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x0006dc2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x0006dc2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x0006dc30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x0006dc32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x0006dc34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x0006dc36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x0006dc38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x0006dc3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x0006dc3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x0006dc3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0006e000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0006e000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0006e000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
new file mode 100644
index 0000000000000000000000000000000000000000..ec553e87fc363cd5b37dd708a67d88a44b632c15
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -0,0 +1,480 @@
+fpga_name = lofar2_unb2b_sdp_station
+number_of_columns = 13
+# There can be multiple lines with a single key. The host should ignore unknown keys.
+# The lines with columns follow after the number_of_columns keys. The host should ignore
+# the extra columns in case the mmap contains more columns than the host expects.
+#
+# col 1: mm_port_name, if - then it is part of previous MM port.
+# col 2: number of peripherals, if - then it is part of previous peripheral.
+# col 3: number of mm_ports, if - then it is part of previous MM port.
+# col 4: mm_port_type, if - then it is part of previous MM port.
+# col 5: field_name
+# col 6: field start address (in MM words)
+# col 7: number of fields, if - then it is part of previous field_name.
+# col 8: field access_mode, if - then it is part of previous field_name.
+# col 9: field radix, if - then it is part of previous field_name.
+# col 10: field mm_mask
+# col 11: field user_mask, if - then it is same as mm_mask
+# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
+# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
+#
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00000df8 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00000de0 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x0002d032 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x0002d032 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x0002d032 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x0002d033 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x0002d033 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0002d034 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x0002d000 1 WO uint32 b[23:0] - - -
+ - - - - rden 0x0002d001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x0002d002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x0002d003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x0002d004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x0002d005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x0002d006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002d030 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x0002d02e 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002d02c 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0002d02d 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x0002d02a 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x0002d008 1 WO uint32 b[31:0] - - -
+ - - - - param 0x0002d009 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0002d00a 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0002d00b 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0002d00c 1 RO uint32 b[23:0] - - -
+ - - - - data_in 0x0002d00d 1 WO uint32 b[23:0] - - -
+ - - - - busy 0x0002d00e 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG beamlet_scale 0x00000dd0 1 RW uint32 b[15:0] - - -
+ - - - - block_period 0x00000dd1 1 RO uint32 b[15:0] - - -
+ - - - - n_rn 0x00000dd2 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x00000dd3 1 RW uint32 b[7:0] - - -
+ - - - - n_si 0x00000dd4 1 RW uint32 b[7:0] - - -
+ - - - - o_si 0x00000dd5 1 RW uint32 b[7:0] - - -
+ - - - - beam_repositioning_flag 0x00000dd6 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x00000dd7 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x00000dd8 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x00000dd9 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x00000dda 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x00000ddb 1 RO uint32 b[0:0] - - -
+ - - - - station_id 0x00000ddc 1 RW uint32 b[15:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x0002d020 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x0002d020 1 RW uint32 b[31:31] - - -
+ JESD204B 1 1 REG rx_dll_ctrl 0x0002c014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x0002c015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x0002c015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x0002c015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x0002c015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x0002c018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x0002c019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x0002c020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x0002c020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x0002c021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x0002c022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x0002c023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x0002c025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x0002c025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x0002c025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x0002c025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x0002c026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x0002c026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x0002c026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x0002c026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x0002c026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x0002c026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x0002c026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x0002c026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0002c03c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0002c03d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0002c03e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0002c03f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00000df0 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00000df0 1 RW uint32 b[1:1] - - -
+ - - - - nof_block_per_sync 0x00000df1 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00000df2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000df3 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00000df4 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0002d026 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0002d027 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00000cc0 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00000cc0 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00000cc1 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00000cc2 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00000cc3 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d00 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x00000d01 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x00000d02 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d03 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024
+ REG_SI 1 1 REG enable 0x0002d028 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x0002d024 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x00028000 2048 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x0002d025 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x0002d01e 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x00000c83 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x00000c84 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x00000c85 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000c86 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x00000c86 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x00000c86 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x00000c87 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000c88 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000c8a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x00000c8b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000c8c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c8d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c8e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c8f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c90 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c91 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c92 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c93 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c94 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c95 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c96 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c97 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c98 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c99 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c9a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c9b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c9c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c9d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c9e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c9f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000ca0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000ca1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000ca2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000ca3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000ca4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000ca5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000ca6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000ca7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000ca8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000ca9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000caa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000cab 1 RW uint32 b[15:0] - - -
+ REG_BSN_SCHEDULER_XSUB 1 1 REG scheduled_bsn 0x00000c02 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c03 - - - b[31:0] b[63:32] - -
+ REG_DP_SYNC_INSERT_V2 1 1 REG nof_blk_per_sync 0x0002d018 1 RW uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 1 RAM data 0x00018000 576 RW cint64_ir b[31:0] b[31:0] - -
+ - - - - - 0x0002d019 - - - b[31:0] b[63:32] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00000dc0 15 RW uint32 b[31:0] - - -
+ - - - - step 0x00000dcf 1 RW uint32 b[31:0] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BF_SCALE 2 1 REG scale 0x0002d014 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x0002d015 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000081 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000082 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00000083 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00000084 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00000085 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00000086 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00000087 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000088 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0000008a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0000008b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000008c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000008d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000008e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0000008f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000090 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000091 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000092 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000093 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000094 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000095 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000096 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000097 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000098 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000099 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000009a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000009b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000009c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000009d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000009e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0000009f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x000000a0 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x000000a1 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x000000a2 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x000000a3 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x000000a4 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x000000a5 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x000000a6 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000a7 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x000000a8 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000000a9 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x0002d010 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00001000 1952 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x0002d011 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x00000000 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00000001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00000006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00000006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00000007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0000000a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_subband_calibrated_flag 0x0000000b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0000000c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000000d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000000e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000000f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0000001a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000001b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000001c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000001d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000001e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000001f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0000002a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0000002b 1 RW uint32 b[15:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00002000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00002001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00002002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00002040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00002080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000020c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000020c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000020c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000020c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00002100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00002140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00002800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00002801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00002802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00002803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00002804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00002805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00002806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00002807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00002808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00002809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0000280a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0000280b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00002818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00002c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00002c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00002c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00002c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00002c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00002c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00002c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00002c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00002c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00002c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00002c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00002c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00002c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00002c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00002c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00002c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00002c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00002c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00002c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00002c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00002c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00002c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00002c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00002c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00002c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00002c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00002c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00002c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00002c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00002c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00002c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00002c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00003001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00003040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00003080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000030c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000030c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00003100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00003140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00003141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00003142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00003180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00003181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00003182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00003183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00003184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00003185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00003186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00003187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00003190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00003191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00003192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00003193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00003194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00003195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00003196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00003197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000031a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00003200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00003201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00003202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00003801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00003c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00003c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00003c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00003c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00003c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00003c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00003c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00003c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00003c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00003c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00003c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00003c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00003c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00003c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00003c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00003c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00003c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00003c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00003c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00003c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00003c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00003c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00003c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00003c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00003c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00003c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00003c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00003c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00003c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00003c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00003c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00003c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0002d022 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x0002d022 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x0002d022 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index 2f2d234af3b3a8f02f91aaa5284df16304c44af1..ccf19dc700d6b0443560acab6dcff061536e5ff8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3780' end='0x37A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37A0' end='0x37C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_remu.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='jesd204b.mem' start='0xA0000' end='0xA4000' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xA4000' end='0xA4010' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xA4010' end='0xA4020' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xA4020' end='0xA4028' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xA4028' end='0xA4030' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xA4030' end='0xA4038' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xA4038' end='0xA4040' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xA4040' end='0xA4048' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xA4048' end='0xA4050' datawidth='32' /><slave name='reg_si.mem' start='0xA4050' end='0xA4058' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xA4058' end='0xA4060' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xA4060' end='0xA4068' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xA4068' end='0xA4070' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xA4070' end='0xA4078' datawidth='32' /><slave name='pio_pps.mem' start='0xA4078' end='0xA4080' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xA4080' end='0xA4088' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_wg.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4060' end='0xB4070' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3780' end='0x37A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37A0' end='0x37C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_remu.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='jesd204b.mem' start='0xA0000' end='0xA4000' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xA4000' end='0xA4010' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xA4010' end='0xA4020' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xA4020' end='0xA4028' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xA4028' end='0xA4030' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xA4030' end='0xA4038' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xA4038' end='0xA4040' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xA4040' end='0xA4048' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xA4048' end='0xA4050' datawidth='32' /><slave name='reg_si.mem' start='0xA4050' end='0xA4058' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xA4058' end='0xA4060' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xA4060' end='0xA4068' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xA4068' end='0xA4070' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xA4070' end='0xA4078' datawidth='32' /><slave name='pio_pps.mem' start='0xA4078' end='0xA4080' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xA4080' end='0xA4088' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_wg.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4060' end='0xB4070' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
new file mode 100644
index 0000000000000000000000000000000000000000..058e6e8b5e0d547b5ee4c124f36c45a1c76b2ec4
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">65536</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>13</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>13</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">14</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>65536</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_st_xsq.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
index e4500ca3d683d29adeabee6a1c298cbe7dc02383..e41248d531721555270335dfb2bf93e7bbd6817e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1398,38 +1398,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
index 1ae732e8c725b6782daeb2b0a1acfcde59de303e..1201aca1e0e24a18beed2bba3fd0ab72e27613e4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>5</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>5</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
index abb238885cd706c366bbca1919d260f0faba6816..a523d8af9523229c23c36c2005b7d4231b7e137d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -766,7 +766,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1398,38 +1398,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
new file mode 100644
index 0000000000000000000000000000000000000000..fb9f5c754e3740aed2d8f04e23ab366138cf0d91
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>1</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>1</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>4</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
index 3c0b3d0ae7ad54913a0b8a1316b603eb0226ed9a..0ab37b533e312fae84402ed698a2ed2a6582bce6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>5</spirit:right>
+ <spirit:right>6</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>5</spirit:right>
+ <spirit:right>6</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">7</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
index a041aae6d83c1972821b3e27f333568006a8c93e..82c0df011c95f6503ba618f2fbe419b37c5765ab 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
@@ -97,8 +97,8 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
-# false paths added for the jesd test design
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
-set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
-set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+# false paths added for the jesd interface as these clocks are independent.
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
+set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
+set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index 81ce21efced6447469d0a125380059080ca9d8d3..a232a48c9af432d45e11f91a8b2a5eee4af73132 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "655360";
+ value = "720896";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "671872";
+ value = "737488";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "671792";
+ value = "737408";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "671864";
+ value = "737480";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "589824";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "393216";
+ value = "458752";
type = "String";
}
}
@@ -330,7 +330,23 @@
{
datum baseAddress
{
- value = "589824";
+ value = "655360";
+ type = "String";
+ }
+ }
+ element ram_st_xsq
+ {
+ datum _sortIndex
+ {
+ value = "54";
+ type = "int";
+ }
+ }
+ element ram_st_xsq.mem
+ {
+ datum baseAddress
+ {
+ value = "393216";
type = "String";
}
}
@@ -346,7 +362,7 @@
{
datum baseAddress
{
- value = "458752";
+ value = "524288";
type = "String";
}
}
@@ -378,7 +394,7 @@
{
datum baseAddress
{
- value = "671760";
+ value = "737376";
type = "String";
}
}
@@ -410,7 +426,23 @@
{
datum baseAddress
{
- value = "671816";
+ value = "737432";
+ type = "String";
+ }
+ }
+ element reg_bsn_scheduler_xsub
+ {
+ datum _sortIndex
+ {
+ value = "53";
+ type = "int";
+ }
+ }
+ element reg_bsn_scheduler_xsub.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
type = "String";
}
}
@@ -426,7 +458,23 @@
{
datum baseAddress
{
- value = "14208";
+ value = "14272";
+ type = "String";
+ }
+ }
+ element reg_crosslets_info
+ {
+ datum _sortIndex
+ {
+ value = "52";
+ type = "int";
+ }
+ }
+ element reg_crosslets_info.mem
+ {
+ datum baseAddress
+ {
+ value = "14080";
type = "String";
}
}
@@ -458,7 +506,7 @@
{
datum baseAddress
{
- value = "671808";
+ value = "737424";
type = "String";
}
}
@@ -478,6 +526,22 @@
type = "String";
}
}
+ element reg_dp_sync_insert_v2
+ {
+ datum _sortIndex
+ {
+ value = "51";
+ type = "int";
+ }
+ }
+ element reg_dp_sync_insert_v2.mem
+ {
+ datum baseAddress
+ {
+ value = "737392";
+ type = "String";
+ }
+ }
element reg_dp_xonoff
{
datum _sortIndex
@@ -490,7 +554,7 @@
{
datum baseAddress
{
- value = "671744";
+ value = "737360";
type = "String";
}
}
@@ -511,7 +575,7 @@
{
datum baseAddress
{
- value = "671856";
+ value = "737472";
type = "String";
}
}
@@ -532,7 +596,7 @@
{
datum baseAddress
{
- value = "671848";
+ value = "737464";
type = "String";
}
}
@@ -553,7 +617,7 @@
{
datum baseAddress
{
- value = "14272";
+ value = "737280";
type = "String";
}
}
@@ -569,7 +633,7 @@
{
datum baseAddress
{
- value = "14240";
+ value = "14304";
type = "String";
}
}
@@ -590,7 +654,7 @@
{
datum baseAddress
{
- value = "14144";
+ value = "14208";
type = "String";
}
}
@@ -606,7 +670,7 @@
{
datum baseAddress
{
- value = "512";
+ value = "12800";
type = "String";
}
}
@@ -627,7 +691,7 @@
{
datum baseAddress
{
- value = "671840";
+ value = "737456";
type = "String";
}
}
@@ -648,7 +712,7 @@
{
datum baseAddress
{
- value = "671832";
+ value = "737448";
type = "String";
}
}
@@ -664,7 +728,7 @@
{
datum baseAddress
{
- value = "671800";
+ value = "737416";
type = "String";
}
}
@@ -701,7 +765,7 @@
{
datum baseAddress
{
- value = "14304";
+ value = "737312";
type = "String";
}
}
@@ -717,7 +781,7 @@
{
datum baseAddress
{
- value = "14080";
+ value = "14144";
type = "String";
}
}
@@ -733,11 +797,11 @@
{
datum baseAddress
{
- value = "671824";
+ value = "737440";
type = "String";
}
}
- element reg_stat_enable_bst_0
+ element reg_stat_enable_bst
{
datum _sortIndex
{
@@ -745,27 +809,11 @@
type = "int";
}
}
- element reg_stat_enable_bst_0.mem
- {
- datum baseAddress
- {
- value = "671776";
- type = "String";
- }
- }
- element reg_stat_enable_bst_1
- {
- datum _sortIndex
- {
- value = "51";
- type = "int";
- }
- }
- element reg_stat_enable_bst_1.mem
+ element reg_stat_enable_bst.mem
{
datum baseAddress
{
- value = "12296";
+ value = "737344";
type = "String";
}
}
@@ -781,11 +829,11 @@
{
datum baseAddress
{
- value = "671784";
+ value = "737400";
type = "String";
}
}
- element reg_stat_hdr_dat_bst_0
+ element reg_stat_hdr_dat_bst
{
datum _sortIndex
{
@@ -793,27 +841,11 @@
type = "int";
}
}
- element reg_stat_hdr_dat_bst_0.mem
+ element reg_stat_hdr_dat_bst.mem
{
datum baseAddress
{
- value = "256";
- type = "String";
- }
- }
- element reg_stat_hdr_dat_bst_1
- {
- datum _sortIndex
- {
- value = "52";
- type = "int";
- }
- }
- element reg_stat_hdr_dat_bst_1.mem
- {
- datum baseAddress
- {
- value = "12544";
+ value = "512";
type = "String";
}
}
@@ -829,7 +861,7 @@
{
datum baseAddress
{
- value = "12800";
+ value = "256";
type = "String";
}
}
@@ -903,7 +935,7 @@
{
datum baseAddress
{
- value = "13056";
+ value = "12544";
type = "String";
}
}
@@ -1507,6 +1539,41 @@
internal="ram_st_sst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="ram_st_xsq_address"
+ internal="ram_st_xsq.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_xsq_clk"
+ internal="ram_st_xsq.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_xsq_read"
+ internal="ram_st_xsq.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_xsq_readdata"
+ internal="ram_st_xsq.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_xsq_reset"
+ internal="ram_st_xsq.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_xsq_write"
+ internal="ram_st_xsq.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_st_xsq_writedata"
+ internal="ram_st_xsq.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="ram_wg_address"
internal="ram_wg.address"
@@ -1666,6 +1733,41 @@
internal="reg_bsn_scheduler.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_scheduler_xsub_address"
+ internal="reg_bsn_scheduler_xsub.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_scheduler_xsub_clk"
+ internal="reg_bsn_scheduler_xsub.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_scheduler_xsub_read"
+ internal="reg_bsn_scheduler_xsub.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_scheduler_xsub_readdata"
+ internal="reg_bsn_scheduler_xsub.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_scheduler_xsub_reset"
+ internal="reg_bsn_scheduler_xsub.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_scheduler_xsub_write"
+ internal="reg_bsn_scheduler_xsub.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_scheduler_xsub_writedata"
+ internal="reg_bsn_scheduler_xsub.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_source_v2_address"
internal="reg_bsn_source_v2.address"
@@ -1701,6 +1803,41 @@
internal="reg_bsn_source_v2.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_crosslets_info_address"
+ internal="reg_crosslets_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_crosslets_info_clk"
+ internal="reg_crosslets_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_crosslets_info_read"
+ internal="reg_crosslets_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_crosslets_info_readdata"
+ internal="reg_crosslets_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_crosslets_info_reset"
+ internal="reg_crosslets_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_crosslets_info_write"
+ internal="reg_crosslets_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_crosslets_info_writedata"
+ internal="reg_crosslets_info.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_diag_data_buffer_bsn_address"
internal="reg_diag_data_buffer_bsn.address"
@@ -1806,6 +1943,41 @@
internal="reg_dp_shiftram.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_dp_sync_insert_v2_address"
+ internal="reg_dp_sync_insert_v2.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_sync_insert_v2_clk"
+ internal="reg_dp_sync_insert_v2.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_sync_insert_v2_read"
+ internal="reg_dp_sync_insert_v2.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_sync_insert_v2_readdata"
+ internal="reg_dp_sync_insert_v2.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_sync_insert_v2_reset"
+ internal="reg_dp_sync_insert_v2.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_sync_insert_v2_write"
+ internal="reg_dp_sync_insert_v2.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_sync_insert_v2_writedata"
+ internal="reg_dp_sync_insert_v2.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dp_xonoff_address"
internal="reg_dp_xonoff.address"
@@ -2273,73 +2445,38 @@
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_0_address"
- internal="reg_stat_enable_bst_0.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_clk"
- internal="reg_stat_enable_bst_0.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_read"
- internal="reg_stat_enable_bst_0.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_readdata"
- internal="reg_stat_enable_bst_0.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_reset"
- internal="reg_stat_enable_bst_0.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_0_write"
- internal="reg_stat_enable_bst_0.write"
+ name="reg_stat_enable_bst_address"
+ internal="reg_stat_enable_bst.address"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_0_writedata"
- internal="reg_stat_enable_bst_0.writedata"
+ name="reg_stat_enable_bst_clk"
+ internal="reg_stat_enable_bst.clk"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_address"
- internal="reg_stat_enable_bst_1.address"
+ name="reg_stat_enable_bst_read"
+ internal="reg_stat_enable_bst.read"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_clk"
- internal="reg_stat_enable_bst_1.clk"
+ name="reg_stat_enable_bst_readdata"
+ internal="reg_stat_enable_bst.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_read"
- internal="reg_stat_enable_bst_1.read"
+ name="reg_stat_enable_bst_reset"
+ internal="reg_stat_enable_bst.reset"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_readdata"
- internal="reg_stat_enable_bst_1.readdata"
+ name="reg_stat_enable_bst_write"
+ internal="reg_stat_enable_bst.write"
type="conduit"
dir="end" />
<interface
- name="reg_stat_enable_bst_1_reset"
- internal="reg_stat_enable_bst_1.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_1_write"
- internal="reg_stat_enable_bst_1.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_enable_bst_1_writedata"
- internal="reg_stat_enable_bst_1.writedata"
+ name="reg_stat_enable_bst_writedata"
+ internal="reg_stat_enable_bst.writedata"
type="conduit"
dir="end" />
<interface
@@ -2378,73 +2515,38 @@
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_0_address"
- internal="reg_stat_hdr_dat_bst_0.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_clk"
- internal="reg_stat_hdr_dat_bst_0.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_read"
- internal="reg_stat_hdr_dat_bst_0.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_readdata"
- internal="reg_stat_hdr_dat_bst_0.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_0_reset"
- internal="reg_stat_hdr_dat_bst_0.reset"
+ name="reg_stat_hdr_dat_bst_address"
+ internal="reg_stat_hdr_dat_bst.address"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_0_write"
- internal="reg_stat_hdr_dat_bst_0.write"
+ name="reg_stat_hdr_dat_bst_clk"
+ internal="reg_stat_hdr_dat_bst.clk"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_0_writedata"
- internal="reg_stat_hdr_dat_bst_0.writedata"
+ name="reg_stat_hdr_dat_bst_read"
+ internal="reg_stat_hdr_dat_bst.read"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_address"
- internal="reg_stat_hdr_dat_bst_1.address"
+ name="reg_stat_hdr_dat_bst_readdata"
+ internal="reg_stat_hdr_dat_bst.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_clk"
- internal="reg_stat_hdr_dat_bst_1.clk"
+ name="reg_stat_hdr_dat_bst_reset"
+ internal="reg_stat_hdr_dat_bst.reset"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_read"
- internal="reg_stat_hdr_dat_bst_1.read"
+ name="reg_stat_hdr_dat_bst_write"
+ internal="reg_stat_hdr_dat_bst.write"
type="conduit"
dir="end" />
<interface
- name="reg_stat_hdr_dat_bst_1_readdata"
- internal="reg_stat_hdr_dat_bst_1.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_1_reset"
- internal="reg_stat_hdr_dat_bst_1.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_1_write"
- internal="reg_stat_hdr_dat_bst_1.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_stat_hdr_dat_bst_1_writedata"
- internal="reg_stat_hdr_dat_bst_1.writedata"
+ name="reg_stat_hdr_dat_bst_writedata"
+ internal="reg_stat_hdr_dat_bst.writedata"
type="conduit"
dir="end" />
<interface
@@ -5601,7 +5703,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3780' end='0x37A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37A0' end='0x37C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_remu.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='jesd204b.mem' start='0xA0000' end='0xA4000' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xA4000' end='0xA4010' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xA4010' end='0xA4020' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xA4020' end='0xA4028' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xA4028' end='0xA4030' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xA4030' end='0xA4038' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xA4038' end='0xA4040' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xA4040' end='0xA4048' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xA4048' end='0xA4050' datawidth='32' /><slave name='reg_si.mem' start='0xA4050' end='0xA4058' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xA4058' end='0xA4060' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xA4060' end='0xA4068' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xA4068' end='0xA4070' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xA4070' end='0xA4078' datawidth='32' /><slave name='pio_pps.mem' start='0xA4078' end='0xA4080' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xA4080' end='0xA4088' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_wg.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3780' end='0x37C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4000' end='0xB4020' datawidth='32' /><slave name='reg_remu.mem' start='0xB4020' end='0xB4040' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4040' end='0xB4050' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4050' end='0xB4060' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4060' end='0xB4070' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4070' end='0xB4078' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4078' end='0xB4080' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4080' end='0xB4088' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4088' end='0xB4090' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4090' end='0xB4098' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB4098' end='0xB40A0' datawidth='32' /><slave name='reg_si.mem' start='0xB40A0' end='0xB40A8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB40A8' end='0xB40B0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB40B0' end='0xB40B8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB40B8' end='0xB40C0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB40C0' end='0xB40C8' datawidth='32' /><slave name='pio_pps.mem' start='0xB40C8' end='0xB40D0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB40D0' end='0xB40D8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -15016,7 +15118,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="ram_st_xsq"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15602,37 +15704,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_xsq</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="ram_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15648,7 +15750,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15712,7 +15814,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15781,7 +15883,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16187,11 +16289,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16218,37 +16320,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16264,7 +16366,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16328,7 +16430,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16397,7 +16499,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16803,11 +16905,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16834,37 +16936,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16880,7 +16982,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16944,7 +17046,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17013,7 +17115,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17419,11 +17521,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17450,37 +17552,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17496,7 +17598,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17560,7 +17662,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17629,7 +17731,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18035,11 +18137,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18066,37 +18168,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source_v2"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18112,7 +18214,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18176,7 +18278,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18245,7 +18347,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18651,11 +18753,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18682,37 +18784,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_bsn_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18728,7 +18830,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18792,7 +18894,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18861,7 +18963,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19267,11 +19369,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19298,37 +19400,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19344,7 +19446,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19408,7 +19510,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19477,7 +19579,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19883,11 +19985,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19914,37 +20016,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19960,7 +20062,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20024,7 +20126,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20093,7 +20195,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20499,11 +20601,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20530,37 +20632,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20576,7 +20678,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20640,7 +20742,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20709,7 +20811,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21115,11 +21217,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21146,37 +21248,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21762,37 +21864,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21808,7 +21910,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21872,7 +21974,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21941,7 +22043,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22347,11 +22449,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22378,37 +22480,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dp_sync_insert_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22424,7 +22526,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22488,7 +22590,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22557,7 +22659,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22963,11 +23065,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22994,37 +23096,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_dp_xonoff"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23040,7 +23142,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23104,7 +23206,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23173,7 +23275,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23579,11 +23681,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23610,37 +23712,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23656,7 +23758,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23720,7 +23822,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23789,7 +23891,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24195,11 +24297,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24226,37 +24328,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_hdr_dat"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24272,7 +24374,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24336,7 +24438,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24405,7 +24507,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24811,11 +24913,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24842,37 +24944,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24888,7 +24990,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24952,7 +25054,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25021,7 +25123,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25427,11 +25529,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25458,37 +25560,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25504,7 +25606,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25568,7 +25670,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25637,7 +25739,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26043,11 +26145,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26074,37 +26176,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26120,7 +26222,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26184,7 +26286,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26253,7 +26355,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26659,11 +26761,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26690,37 +26792,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26736,7 +26838,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26800,7 +26902,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26869,7 +26971,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27275,11 +27377,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27306,37 +27408,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27352,7 +27454,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27416,7 +27518,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27485,7 +27587,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27891,11 +27993,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27922,37 +28024,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27968,7 +28070,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28032,7 +28134,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28101,7 +28203,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28507,11 +28609,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28538,37 +28640,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29154,37 +29256,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst_0"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29200,7 +29302,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29264,7 +29366,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29333,7 +29435,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29739,11 +29841,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29770,37 +29872,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst_1"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29816,7 +29918,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29880,7 +29982,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29949,7 +30051,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30355,11 +30457,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30386,37 +30488,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_sst"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30432,7 +30534,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30496,7 +30598,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30565,7 +30667,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30971,11 +31073,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31002,37 +31104,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst_0"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31048,7 +31150,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31112,7 +31214,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31181,7 +31283,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31587,11 +31689,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31618,37 +31720,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst_1"
+ name="reg_stat_enable_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31664,7 +31766,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31728,7 +31830,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31797,7 +31899,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32203,11 +32305,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32234,37 +32336,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_sst"
+ name="reg_stat_enable_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32280,7 +32382,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32344,7 +32446,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32413,7 +32515,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32819,11 +32921,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32850,37 +32952,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_pmbus"
+ name="reg_stat_hdr_dat_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32896,7 +32998,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32960,7 +33062,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33029,7 +33131,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33435,11 +33537,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33466,37 +33568,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_sens"
+ name="reg_stat_hdr_dat_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34082,37 +34184,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="reg_unb_pmbus"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34128,7 +34230,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34192,7 +34294,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34261,7 +34363,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34667,11 +34769,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34698,37 +34800,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wg"
+ name="reg_unb_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35314,37 +35416,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="reg_wdi"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35360,7 +35462,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35424,7 +35526,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35493,7 +35595,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35899,11 +36001,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35930,37 +36032,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="timer_0"
+ name="reg_wg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35968,17 +36070,17 @@
<boundary>
<interfaces>
<interface>
- <name>clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -35987,27 +36089,26 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>irq</name>
- <type>interrupt</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>irq</name>
- <role>irq</role>
+ <name>coe_clk_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -36019,106 +36120,63 @@
</assignments>
<parameters>
<parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>timer_0.s1</value>
- </entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
</entry>
<entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>s1</name>
+ <name>mem</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>address</name>
+ <name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>writedata</name>
- <role>writedata</role>
+ <name>avs_mem_write</name>
+ <role>write</role>
<direction>Input</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>16</width>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -36139,17 +36197,13 @@
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
- <entry>
- <key>embeddedsw.configuration.isTimerDevice</key>
- <value>1</value>
- </entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>NATIVE</value>
+ <value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -36157,7 +36211,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36169,11 +36223,1291 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
+ <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="rom_system_info"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32768</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="timer_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>timer_0.s1</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isTimerDevice</key>
+ <value>1</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>NATIVE</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -36688,7 +38022,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000a4080" />
+ <parameter name="baseAddress" value="0x000b40d0" />
</connection>
<connection
kind="avalon"
@@ -36723,7 +38057,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000a4078" />
+ <parameter name="baseAddress" value="0x000b40c8" />
</connection>
<connection
kind="avalon"
@@ -36737,49 +38071,49 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x37e0" />
+ <parameter name="baseAddress" value="0x000b4020" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x37c0" />
+ <parameter name="baseAddress" value="0x000b4000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000a4070" />
+ <parameter name="baseAddress" value="0x000b40c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000a4068" />
+ <parameter name="baseAddress" value="0x000b40b8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000a4060" />
+ <parameter name="baseAddress" value="0x000b40b0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000a4058" />
+ <parameter name="baseAddress" value="0x000b40a8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x37a0" />
+ <parameter name="baseAddress" value="0x37e0" />
</connection>
<connection
kind="avalon"
@@ -36793,28 +38127,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x3740" />
+ <parameter name="baseAddress" value="0x3780" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_st_sst.mem">
- <parameter name="baseAddress" value="0x00090000" />
+ <parameter name="baseAddress" value="0x000a0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000a4050" />
+ <parameter name="baseAddress" value="0x000b40a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x00090000" />
</connection>
<connection
kind="avalon"
@@ -36835,7 +38169,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_wg.mem">
- <parameter name="baseAddress" value="0x00070000" />
+ <parameter name="baseAddress" value="0x00080000" />
</connection>
<connection
kind="avalon"
@@ -36849,21 +38183,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000a4048" />
+ <parameter name="baseAddress" value="0x000b4098" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x3780" />
+ <parameter name="baseAddress" value="0x37c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x3300" />
+ <parameter name="baseAddress" value="0x3100" />
</connection>
<connection
kind="avalon"
@@ -36877,14 +38211,14 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x000a0000" />
+ <parameter name="baseAddress" value="0x000b0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000a4040" />
+ <parameter name="baseAddress" value="0x000b4090" />
</connection>
<connection
kind="avalon"
@@ -36898,7 +38232,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
- <parameter name="baseAddress" value="0x00060000" />
+ <parameter name="baseAddress" value="0x00070000" />
</connection>
<connection
kind="avalon"
@@ -36912,21 +38246,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x000a4010" />
+ <parameter name="baseAddress" value="0x000b4060" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x3200" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x000a4000" />
+ <parameter name="baseAddress" value="0x000b4050" />
</connection>
<connection
kind="avalon"
@@ -36940,14 +38274,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x3700" />
+ <parameter name="baseAddress" value="0x3740" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000a4038" />
+ <parameter name="baseAddress" value="0x000b4088" />
</connection>
<connection
kind="avalon"
@@ -36975,49 +38309,63 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000a4030" />
+ <parameter name="baseAddress" value="0x000b4080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000a4028" />
+ <parameter name="baseAddress" value="0x000b4078" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_hdr_dat_sst.mem">
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x0100" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_enable_bst_0.mem">
- <parameter name="baseAddress" value="0x000a4020" />
+ end="reg_stat_enable_bst.mem">
+ <parameter name="baseAddress" value="0x000b4040" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_enable_bst_1.mem">
- <parameter name="baseAddress" value="0x3008" />
+ end="reg_stat_hdr_dat_bst.mem">
+ <parameter name="baseAddress" value="0x0200" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_hdr_dat_bst_1.mem">
- <parameter name="baseAddress" value="0x3100" />
+ end="reg_dp_sync_insert_v2.mem">
+ <parameter name="baseAddress" value="0x000b4070" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_stat_hdr_dat_bst_0.mem">
- <parameter name="baseAddress" value="0x0100" />
+ end="reg_crosslets_info.mem">
+ <parameter name="baseAddress" value="0x3700" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_scheduler_xsub.mem">
+ <parameter name="baseAddress" value="0x3008" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="ram_st_xsq.mem">
+ <parameter name="baseAddress" value="0x00060000" />
</connection>
<connection
kind="avalon"
@@ -37255,22 +38603,28 @@
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_enable_bst_0.system" />
+ end="reg_stat_enable_bst.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_hdr_dat_bst.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_enable_bst_1.system" />
+ end="reg_dp_sync_insert_v2.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_hdr_dat_bst_1.system" />
+ end="reg_crosslets_info.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_stat_hdr_dat_bst_0.system" />
+ end="reg_bsn_scheduler_xsub.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_st_xsq.system" />
<connection
kind="interrupt"
version="18.0"
@@ -37526,22 +38880,32 @@
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_enable_bst_0.system_reset" />
+ end="reg_stat_enable_bst.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_hdr_dat_bst.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_dp_sync_insert_v2.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_enable_bst_1.system_reset" />
+ end="reg_crosslets_info.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_hdr_dat_bst_1.system_reset" />
+ end="reg_bsn_scheduler_xsub.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_stat_hdr_dat_bst_0.system_reset" />
+ end="ram_st_xsq.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 44b7d53cf3daa2937c82387c8ccba3579e6fa3c0..54408a457fb2d17d8a359c4e95890d4d72f6d51b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -60,17 +60,21 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
@@ -83,11 +87,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 492a2f066bd4feb838d465a7b0d3125cd56c3124..e709996fce50621190bf266a6776dc66f99b7a13 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -68,17 +68,21 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
@@ -91,11 +95,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
index 429a7d3eab609b1160a8bbbba877c8945ea193c0..6d2fd81124120d6d77ff2bb6b55a8f1efa55d1e9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
@@ -76,8 +76,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf_bst_offload IS
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
-- MM
- CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
- CONSTANT c_mm_file_reg_stat_enable_bst_0 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_BST_0";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_stat_enable_bst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_BST";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
@@ -217,7 +217,7 @@ BEGIN
----------------------------------------------------------------------------
-- Offload enable
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_stat_enable_bst_0, 0, 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable_bst, 0, 1, tb_clk);
-- wait for udp offload is done
proc_common_wait_until_high(ext_clk, eth_done);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index 79c5c8a6cac59b00baafa79ba5fa55e52d5c7754..7f5f8378210120d01b2a41274af18f087dccb0b2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -67,17 +67,21 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
@@ -90,11 +94,9 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index 44f22b5dbe0e4c6e6190adda0914f29621adfb2d..ef1bd83f987c514f911651c6752052c0fb215fe6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -78,7 +78,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
CONSTANT c_nof_block_per_sync : NATURAL := 16;
- CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft - (c_sdp_N_fft/2); --15.5 block per sync
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
index ac3bffbe3e31ee2d4815f4d42c2d7bb2279103ec..725e9cc20df2788c6b317c0a017871e203e12187 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
@@ -77,7 +77,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub_sst_offload IS
-- MM
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
- CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+ CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_SST";
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d91b50b60553e8fcb6630b1763cd2e314a833f78
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -0,0 +1,106 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_xsub_one
+hdl_library_clause_name = lofar2_unb2b_sdp_station_xsub_one_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_xsub_one.vhd
+
+test_bench_files =
+ tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+
+regression_test_vhdl =
+ tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_one/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..260e3eba61fa9c481ca3e7302206ec3866d5f8e3
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station subband correlator design
+-- Description:
+-- Unb2b version for lab testing
+-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_sdp_station_xsub_one IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_xsub_one";
+ g_design_note : STRING := "Lofar2 SDP station subband correlator design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers (note only 6 are used in unb2b)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (2 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ );
+END lofar2_unb2b_sdp_station_xsub_one;
+
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_xsub_one IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+ JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+ JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+ JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+ JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+ JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+ JESD204B_SERIAL_DATA(6) <= '0';
+ JESD204B_SERIAL_DATA(7) <= '0';
+ JESD204B_SERIAL_DATA(8) <= '0';
+ JESD204B_SERIAL_DATA(9) <= '0';
+ JESD204B_SERIAL_DATA(10) <= '0';
+ JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a8e0635b63a96c82458a3f1efcd46c679643a3af
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -0,0 +1,371 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_xsub_one using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- freq = 19.921875MHz = subband index 102
+-- ampl = 0.5 * 2**13, full scale amplitude is 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Read crosslets statistics (XST) via ram_st_xsq and verify that the values
+-- are as expected. This is done by comparing the values in the outgoing square
+-- correlation matrix.
+--
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_xsub_one IS
+END tb_lofar2_unb2b_sdp_station_xsub_one;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 32;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
+ CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
+ CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
+
+ -- WG
+ CONSTANT c_FS_adc : REAL := REAL(c_sdp_FS_adc); -- = full scale of WG
+ CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_FS_adc; -- amplitude in number of LSbit resolution steps
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
+
+ -- WPFB
+ CONSTANT c_nof_pfb : NATURAL := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ CONSTANT c_wb_leakage_bin : NATURAL := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ CONSTANT c_exp_sp_subband_power_ratio : REAL := 1.0/8.0; -- depends on internal WPFB quantization and FIR coefficients
+ CONSTANT c_exp_sp_subband_power_sum_ratio : REAL := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ CONSTANT c_exp_subband_power_sp_0 : REAL := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
+
+ TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+ CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
+ CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
+ CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+
+ -- WG
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- WPFB
+ SIGNAL xsub_stats_arr : t_slv_64_arr(0 TO c_nof_complex * c_sdp_X_sq -1);
+
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_xsub_one : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => NATURAL(c_subband_sp_0)
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even : NATURAL; -- array indicies
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ -- wait for pps
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ ----------------------------------------------------------------------------
+ -- Enable BSN
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+
+ ----------------------------------------------------------------------------
+ -- Crosslets Info
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, INTEGER(c_subband_sp_0), tb_clk); -- offset
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk); -- stepsize
+
+ ----------------------------------------------------------------------------
+ -- Enable WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+ END LOOP;
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- bsn_scheduler_xsub
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ -- Wait for enough WG data and start of sync interval
+
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ ---------------------------------------------------------------------------
+ -- Read crosslet statistics
+ ---------------------------------------------------------------------------
+ FOR I IN 0 TO c_nof_complex * c_sdp_X_sq * (c_longword_sz/c_word_sz) -1 LOOP
+ v_W := I MOD 2;
+ v_B := I / 2;
+ IF v_W=0 THEN
+ -- low part
+ mmf_mm_bus_rd(c_mm_file_ram_st_xsq, I, rd_data, tb_clk);
+ xsub_stats_arr(v_B)(31 DOWNTO 0) <= rd_data;
+ ELSE
+ -- high part
+ mmf_mm_bus_rd(c_mm_file_ram_st_xsq, I, rd_data, tb_clk);
+ xsub_stats_arr(v_B)(63 DOWNTO 32) <= rd_data;
+ END IF;
+ END LOOP;
+
+
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ ---------------------------------------------------------------------------
+ -- Verify crosslet statistics
+ ---------------------------------------------------------------------------
+ -- With all WGs having the same input all crosslets should be identical. Due to quantization cross talk
+ -- between the two real inputs of the filterbank the two signals in the output pairs per P_pfb differ
+ -- slightly, therefore 3 slightly different correlation values are expected. 1 for each correlation
+ -- between even indexed signals, 1 for odd indexed signals and 1 for correlations between even and odd
+ -- indexed signals. This is verified by checking if these values are the same.
+ FOR I IN 0 TO c_nof_complex * c_sdp_X_sq -1 LOOP
+ v_C := I MOD 2;
+ v_X := I /c_nof_complex;
+ v_A := v_X MOD c_sdp_S_pn;
+ v_B := v_X / c_sdp_S_pn;
+ v_A_even := v_A MOD 2;
+ v_B_even := v_B MOD 2;
+
+ -- Check real values of even indices
+ IF v_C=0 AND v_A_even=0 AND v_B_even=0 THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr(0)) REPORT "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check real values of odd indices
+ IF v_C=0 AND v_A_even=1 AND v_B_even=1 THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) REPORT "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check real values of even correlated with odd indices
+ IF v_C=0 AND (v_A_even=0 XOR v_B_even=0) THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr(1 * c_nof_complex)) REPORT "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
+ -- Check im values of even indices
+ IF v_C=1 AND v_A_even=0 AND v_B_even=0 THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr(1))) REPORT "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check im values of odd indices
+ IF v_C=1 AND v_A_even=1 AND v_B_even=1 THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) REPORT "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check im values of even correlated with odd indices
+ IF v_C=1 AND (v_A_even=0 XOR v_B_even=0) THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr(1 * c_nof_complex + 1))) REPORT "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check if values are > 0
+ IF v_C=0 THEN ASSERT (SIGNED(xsub_stats_arr(I)) > TO_SIGNED(0, c_longword_w)) REPORT "correlation is 0 which is unexpected! at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+ END LOOP;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 1793c7e65cbf4ca8dd410329816b608b2f1e520f..d79ab32df21746a83d0753413e441f987c16aec1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -266,7 +266,7 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------
- -- FUSB
+ -- FSUB
----------------------------------------------
-- Subband statistics
SIGNAL ram_st_sst_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -294,6 +294,25 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_sdp_info_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_sdp_info_miso : t_mem_miso := c_mem_miso_rst;
+ ----------------------------------------------
+ -- XSUB
+ ----------------------------------------------
+ -- dp_sync_insert_v2
+ SIGNAL reg_dp_sync_insert_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dp_sync_insert_v2_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- crosslets_info
+ SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- bsn_scheduler_xsub
+ SIGNAL reg_bsn_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_bsn_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- st_xsq
+ SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+
----------------------------------------------
-- BF
----------------------------------------------
@@ -347,10 +366,14 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- BST
----------------------------------------------
-- Statistics Enable
+ SIGNAL reg_stat_enable_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_stat_enable_bst_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
- -- Statistics header info
+ -- Statistics header info
+ SIGNAL reg_stat_hdr_dat_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_stat_hdr_dat_bst_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -374,11 +397,15 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+
+ SIGNAL dp_bsn_source_restart : STD_LOGIC;
SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
+
-- 10GbE
SIGNAL tr_ref_clk_312 : STD_LOGIC;
SIGNAL tr_ref_clk_156 : STD_LOGIC;
@@ -668,14 +695,18 @@ BEGIN
reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
- reg_stat_enable_bst_0_mosi => reg_stat_enable_bst_mosi_arr(0),
- reg_stat_enable_bst_0_miso => reg_stat_enable_bst_miso_arr(0),
- reg_stat_hdr_dat_bst_0_mosi => reg_stat_hdr_dat_bst_mosi_arr(0),
- reg_stat_hdr_dat_bst_0_miso => reg_stat_hdr_dat_bst_miso_arr(0),
- reg_stat_enable_bst_1_mosi => reg_stat_enable_bst_mosi_arr(1),
- reg_stat_enable_bst_1_miso => reg_stat_enable_bst_miso_arr(1),
- reg_stat_hdr_dat_bst_1_mosi => reg_stat_hdr_dat_bst_mosi_arr(1),
- reg_stat_hdr_dat_bst_1_miso => reg_stat_hdr_dat_bst_miso_arr(1)
+ reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
+ reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
+ reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
+ reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso
);
-----------------------------------------------------------------------------
@@ -763,7 +794,8 @@ BEGIN
jesd204b_sync_n => JESD204B_SYNC_N,
-- Streaming data output
- out_sosi_arr => ait_sosi_arr
+ out_sosi_arr => ait_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart
);
-----------------------------------------------------------------------------
@@ -777,40 +809,74 @@ BEGIN
g_scope_selected_subband => g_scope_selected_subband
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_sst_mosi,
+ reg_enable_miso => reg_stat_enable_sst_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
+ END GENERATE;
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+
+ -----------------------------------------------------------------------------
+ -- node_sdp_correlator (XSUB)
+ -----------------------------------------------------------------------------
+ gen_use_xsub : IF c_revision_select.use_xsub GENERATE
+ u_xsub : ENTITY lofar2_sdp_lib.node_sdp_correlator
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_P_sq => c_revision_select.P_sq
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_sst_mosi,
- reg_enable_miso => reg_stat_enable_sst_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ out_crosslets_info => out_crosslets_info
+
);
END GENERATE;
@@ -943,7 +1009,31 @@ BEGIN
mosi_arr => ram_st_bst_mosi_arr,
miso_arr => ram_st_bst_miso_arr
);
-
+
+ u_mem_mux_reg_stat_enable_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
+ )
+ PORT MAP (
+ mosi => reg_stat_enable_bst_mosi,
+ miso => reg_stat_enable_bst_miso,
+ mosi_arr => reg_stat_enable_bst_mosi_arr,
+ miso_arr => reg_stat_enable_bst_miso_arr
+ );
+
+ u_mem_mux_reg_stat_hdr_dat_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
+ )
+ PORT MAP (
+ mosi => reg_stat_hdr_dat_bst_mosi,
+ miso => reg_stat_hdr_dat_bst_miso,
+ mosi_arr => reg_stat_hdr_dat_bst_mosi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_miso_arr
+ );
+
-----------------------------------------------------------------------------
-- DP MUX
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index 339ec50a03a9f8a7ce3fb4089d80ed6e44971fa1..a51d1ab304fcdd594f6938950980950ec68e180c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -35,12 +35,15 @@ PACKAGE lofar2_unb2b_sdp_station_pkg IS
no_jesd : BOOLEAN;
use_fsub : BOOLEAN;
use_bf : BOOLEAN;
+ use_xsub : BOOLEAN;
+ P_sq : NATURAL;
END RECORD;
- CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE);
- CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE);
- CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE);
- CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE);
+ CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, 0);
+ CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, 0);
+ CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, 0);
+ CONSTANT c_xsub_one : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, 1);
+ CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, 1);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config;
@@ -53,9 +56,10 @@ PACKAGE BODY lofar2_unb2b_sdp_station_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config IS
BEGIN
- IF g_design_name = "lofar2_unb2b_sdp_station_adc" THEN RETURN c_ait;
- ELSIF g_design_name = "lofar2_unb2b_sdp_station_fsub" THEN RETURN c_fsub;
- ELSIF g_design_name = "lofar2_unb2b_sdp_station_bf" THEN RETURN c_bf;
+ IF g_design_name = "lofar2_unb2b_sdp_station_adc" THEN RETURN c_ait;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_fsub" THEN RETURN c_fsub;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_bf" THEN RETURN c_bf;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_xsub_one" THEN RETURN c_xsub_one;
ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 1021899a027b7b34c3f577bc7a70f2c46a1db693..7e1bbd362023e50017798aeb2dc505e072bf2977 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -190,21 +190,29 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_stat_hdr_dat_sst_mosi : OUT t_mem_mosi;
reg_stat_hdr_dat_sst_miso : IN t_mem_miso;
- -- Beamlet Statistics offload BS 0
- reg_stat_enable_bst_0_mosi : OUT t_mem_mosi;
- reg_stat_enable_bst_0_miso : IN t_mem_miso;
+ -- Beamlet Statistics offload
+ reg_stat_enable_bst_mosi : OUT t_mem_mosi;
+ reg_stat_enable_bst_miso : IN t_mem_miso;
- -- Statistics header info
- reg_stat_hdr_dat_bst_0_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_bst_0_miso : IN t_mem_miso;
+ -- Beamlet Statistics header info
+ reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
+ reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
- -- Beamlet Statistics offload BS 1
- reg_stat_enable_bst_1_mosi : OUT t_mem_mosi;
- reg_stat_enable_bst_1_miso : IN t_mem_miso;
+ -- dp_sync_insert_v2
+ reg_dp_sync_insert_v2_mosi : OUT t_mem_mosi;
+ reg_dp_sync_insert_v2_miso : IN t_mem_miso;
- -- Statistics header info
- reg_stat_hdr_dat_bst_1_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_bst_1_miso : IN t_mem_miso;
+ -- crosslets_info
+ reg_crosslets_info_mosi : OUT t_mem_mosi;
+ reg_crosslets_info_miso : IN t_mem_miso;
+
+ -- bsn_scheduler_xsub
+ reg_bsn_scheduler_xsub_mosi : OUT t_mem_mosi;
+ reg_bsn_scheduler_xsub_miso : IN t_mem_miso;
+
+ -- st_xsq (XST)
+ ram_st_xsq_mosi : OUT t_mem_mosi;
+ ram_st_xsq_miso : IN t_mem_miso;
-- 10 GbE mac
reg_nw_10GbE_mac_mosi : OUT t_mem_mosi;
@@ -337,17 +345,23 @@ BEGIN
u_mm_file_reg_stat_hdr_info_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
- u_mm_file_reg_stat_enable_bst_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST_0")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_0_mosi, reg_stat_enable_bst_0_miso );
+ u_mm_file_reg_stat_enable_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_mosi, reg_stat_enable_bst_miso );
+
+ u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
+
+ u_mm_file_reg_dp_sync_insert_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SYNC_INSERT_V2")
+ PORT MAP(mm_rst, mm_clk, reg_dp_sync_insert_v2_mosi, reg_dp_sync_insert_v2_miso);
- u_mm_file_reg_stat_hdr_info_bst_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST_0")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_0_mosi, reg_stat_hdr_dat_bst_0_miso);
+ u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
- u_mm_file_reg_stat_enable_bst_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST_1")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_1_mosi, reg_stat_enable_bst_1_miso );
+ u_mm_file_reg_bsn_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_xsub_mosi, reg_bsn_scheduler_xsub_miso);
- u_mm_file_reg_stat_hdr_info_bst_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST_1")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_1_mosi, reg_stat_hdr_dat_bst_1_miso);
+ u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
+ PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
@@ -717,37 +731,53 @@ BEGIN
reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_mosi.rd,
reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_bst_0_clk_export => OPEN,
- reg_stat_enable_bst_0_reset_export => OPEN,
- reg_stat_enable_bst_0_address_export => reg_stat_enable_bst_0_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_bst_0_write_export => reg_stat_enable_bst_0_mosi.wr,
- reg_stat_enable_bst_0_writedata_export => reg_stat_enable_bst_0_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_bst_0_read_export => reg_stat_enable_bst_0_mosi.rd,
- reg_stat_enable_bst_0_readdata_export => reg_stat_enable_bst_0_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_stat_hdr_dat_bst_0_clk_export => OPEN,
- reg_stat_hdr_dat_bst_0_reset_export => OPEN,
- reg_stat_hdr_dat_bst_0_address_export => reg_stat_hdr_dat_bst_0_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_0_write_export => reg_stat_hdr_dat_bst_0_mosi.wr,
- reg_stat_hdr_dat_bst_0_writedata_export => reg_stat_hdr_dat_bst_0_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_0_read_export => reg_stat_hdr_dat_bst_0_mosi.rd,
- reg_stat_hdr_dat_bst_0_readdata_export => reg_stat_hdr_dat_bst_0_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_stat_enable_bst_1_clk_export => OPEN,
- reg_stat_enable_bst_1_reset_export => OPEN,
- reg_stat_enable_bst_1_address_export => reg_stat_enable_bst_1_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_bst_1_write_export => reg_stat_enable_bst_1_mosi.wr,
- reg_stat_enable_bst_1_writedata_export => reg_stat_enable_bst_1_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_bst_1_read_export => reg_stat_enable_bst_1_mosi.rd,
- reg_stat_enable_bst_1_readdata_export => reg_stat_enable_bst_1_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_stat_hdr_dat_bst_1_clk_export => OPEN,
- reg_stat_hdr_dat_bst_1_reset_export => OPEN,
- reg_stat_hdr_dat_bst_1_address_export => reg_stat_hdr_dat_bst_1_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_1_write_export => reg_stat_hdr_dat_bst_1_mosi.wr,
- reg_stat_hdr_dat_bst_1_writedata_export => reg_stat_hdr_dat_bst_1_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_1_read_export => reg_stat_hdr_dat_bst_1_mosi.rd,
- reg_stat_hdr_dat_bst_1_readdata_export => reg_stat_hdr_dat_bst_1_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_clk_export => OPEN,
+ reg_stat_enable_bst_reset_export => OPEN,
+ reg_stat_enable_bst_address_export => reg_stat_enable_bst_mosi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
+ reg_stat_enable_bst_write_export => reg_stat_enable_bst_mosi.wr,
+ reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_read_export => reg_stat_enable_bst_mosi.rd,
+ reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_hdr_dat_bst_clk_export => OPEN,
+ reg_stat_hdr_dat_bst_reset_export => OPEN,
+ reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_mosi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_mosi.wr,
+ reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
+ reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_sync_insert_v2_clk_export => OPEN,
+ reg_dp_sync_insert_v2_reset_export => OPEN,
+ reg_dp_sync_insert_v2_address_export => reg_dp_sync_insert_v2_mosi.address(c_sdp_reg_dp_sync_insert_v2_addr_w-1 DOWNTO 0),
+ reg_dp_sync_insert_v2_write_export => reg_dp_sync_insert_v2_mosi.wr,
+ reg_dp_sync_insert_v2_writedata_export => reg_dp_sync_insert_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_sync_insert_v2_read_export => reg_dp_sync_insert_v2_mosi.rd,
+ reg_dp_sync_insert_v2_readdata_export => reg_dp_sync_insert_v2_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_crosslets_info_clk_export => OPEN,
+ reg_crosslets_info_reset_export => OPEN,
+ reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_mosi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_scheduler_xsub_clk_export => OPEN,
+ reg_bsn_scheduler_xsub_reset_export => OPEN,
+ reg_bsn_scheduler_xsub_address_export => reg_bsn_scheduler_xsub_mosi.address(c_sdp_reg_bsn_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_scheduler_xsub_write_export => reg_bsn_scheduler_xsub_mosi.wr,
+ reg_bsn_scheduler_xsub_writedata_export => reg_bsn_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_xsub_read_export => reg_bsn_scheduler_xsub_mosi.rd,
+ reg_bsn_scheduler_xsub_readdata_export => reg_bsn_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_st_xsq_clk_export => OPEN,
+ ram_st_xsq_reset_export => OPEN,
+ ram_st_xsq_address_export => ram_st_xsq_mosi.address(c_sdp_ram_st_xsq_addr_w-1 DOWNTO 0),
+ ram_st_xsq_write_export => ram_st_xsq_mosi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_read_export => ram_st_xsq_mosi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_miso.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_mac_clk_export => OPEN,
reg_nw_10GbE_mac_reset_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index f4f915592f2f5676e97b63d237e533e52fab2c98..dfdc3433e9f2452a9452cb3a8c66e1189076159c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -301,34 +301,48 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_0_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_bst_0_clk_export : out std_logic; -- export
- reg_stat_enable_bst_0_read_export : out std_logic; -- export
- reg_stat_enable_bst_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_0_reset_export : out std_logic; -- export
- reg_stat_enable_bst_0_write_export : out std_logic; -- export
- reg_stat_enable_bst_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_bst_0_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_0_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_0_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_0_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_1_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_bst_1_clk_export : out std_logic; -- export
- reg_stat_enable_bst_1_read_export : out std_logic; -- export
- reg_stat_enable_bst_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_1_reset_export : out std_logic; -- export
- reg_stat_enable_bst_1_write_export : out std_logic; -- export
- reg_stat_enable_bst_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_bst_1_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_1_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_1_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_1_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_sync_insert_v2_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_sync_insert_v2_clk_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_read_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_sync_insert_v2_reset_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_write_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_xsub_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_si_address_export : out std_logic_vector(0 downto 0); -- export
reg_si_clk_export : out std_logic; -- export
reg_si_read_export : out std_logic; -- export
diff --git a/applications/lofar2/images/images.txt b/applications/lofar2/images/images.txt
index a80f153a04742cd1c6e9448b0047d683a1d0689c..29135b8ae552db29d9b56d622121a6c8b0bbe813 100644
--- a/applications/lofar2/images/images.txt
+++ b/applications/lofar2/images/images.txt
@@ -3,6 +3,9 @@ Image name | Date | Author
unb2b_minimal-r03350b9b9 | 2021-03-19 | |
lofar2_unb2b_filterbank_full-r8a75c955b | 2021-03-01 | R vd Walle | Deprecated, better use lofar2_unb2b_sdp_station_fsub-rc125dfd6d
lofar2_unb2b_sdp_station_adc-rc125dfd6d | 2021-04-21 | J. Hargreaves | -
-lofar2_unb2b_sdp_station_fsub-rc125dfd6d | 2021-04-21 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_filterbank.py
+lofar2_unb2b_sdp_station_adc-r087d98be6 | 2021-06-14 | J. Hargreaves | -
+lofar2_unb2b_sdp_station_fsub-rbc8dc7f66 | 2021-06-23 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_filterbank.py
lofar2_unb2b_sdp_station_bf-rc125dfd6d | 2021-04-21 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_beamformer.py
+lofar2_unb2b_sdp_station_bf-r087d98be6 | 2021-06-14 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_beamformer.py
+lofar2_unb2b_sdp_station_xsub_one-r087d98be6 | 2021-06-14 | R vd Walle |
diff --git a/applications/lofar2/images/lofar2_unb2b_sdp_station_adc-r087d98be6.tar.gz b/applications/lofar2/images/lofar2_unb2b_sdp_station_adc-r087d98be6.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..986f8ba24f15e0fbfad07aabcc2adabd65b54061
Binary files /dev/null and b/applications/lofar2/images/lofar2_unb2b_sdp_station_adc-r087d98be6.tar.gz differ
diff --git a/applications/lofar2/images/lofar2_unb2b_sdp_station_bf-r087d98be6.tar.gz b/applications/lofar2/images/lofar2_unb2b_sdp_station_bf-r087d98be6.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..94f7c081a9ea2c6f3b247bbdaaca0020648fecb5
Binary files /dev/null and b/applications/lofar2/images/lofar2_unb2b_sdp_station_bf-r087d98be6.tar.gz differ
diff --git a/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rc125dfd6d.tar.gz b/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rbc8dc7f66.tar.gz
similarity index 53%
rename from applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rc125dfd6d.tar.gz
rename to applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rbc8dc7f66.tar.gz
index 657af6ad73180869fb7708af746ed327b6005cd8..e8682233268a6a5f5b9e1a848437319f942ba078 100644
Binary files a/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rc125dfd6d.tar.gz and b/applications/lofar2/images/lofar2_unb2b_sdp_station_fsub-rbc8dc7f66.tar.gz differ
diff --git a/applications/lofar2/images/lofar2_unb2b_sdp_station_xsub_one-r087d98be6.tar.gz b/applications/lofar2/images/lofar2_unb2b_sdp_station_xsub_one-r087d98be6.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..d3c60a35b674071870dbb0af2591cb69bedeb3e3
Binary files /dev/null and b/applications/lofar2/images/lofar2_unb2b_sdp_station_xsub_one-r087d98be6.tar.gz differ
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index 2542eff1d91997df3074d65cd3546b415a56bfc5..42e5c311b2ea8cbe072575f3a0d6e631e1c713cd 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -6,56 +6,76 @@ hdl_library_name: sdp
hdl_library_description: "Station Digital Processor (SDP) for LOFAR2.0"
peripherals:
- - peripheral_name: sdp_info # pi_sdp_info.py ?
+ - peripheral_name: sdp_info # pi_sdp_info.py
peripheral_description: "SDP info."
mm_ports:
# MM port for sdp_info.vhd
- mm_port_name: REG_SDP_INFO
mm_port_type: REG
+ mm_port_span: 16 * MM_BUS_SIZE
mm_port_description: |
"The SDP info contains central SDP information. The station_id applies to the entire station.
The other info fields apply per antenna band (low band or high band). An FPGA node only
participates in one band."
fields:
- - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x0 }
- - - { field_name: antenna_band_index, mm_width: 1, access_mode: RO, address_offset: 0x4 }
- - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x8 }
- - - { field_name: nyquist_zone_index, mm_width: 2, access_mode: RW, address_offset: 0xC }
- - - { field_name: f_adc, mm_width: 1, access_mode: RO, address_offset: 0x10 }
- - - { field_name: fsub_type, mm_width: 1, access_mode: RO, address_offset: 0x14 }
+ - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x30 }
+ - - { field_name: antenna_band_index, mm_width: 1, access_mode: RO, address_offset: 0x2C }
+ - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: nyquist_zone_index, mm_width: 2, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: f_adc, mm_width: 1, access_mode: RO, address_offset: 0x20 }
+ - - { field_name: fsub_type, mm_width: 1, access_mode: RO, address_offset: 0x1C }
- - { field_name: beam_repositioning_flag, mm_width: 1, access_mode: RW, address_offset: 0x18 }
- - - { field_name: subband_calibrated_flag, mm_width: 1, access_mode: RW, address_offset: 0x1C }
- - - { field_name: O_si, mm_width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: N_si, mm_width: 8, access_mode: RW, address_offset: 0x24 }
- - - { field_name: O_rn, mm_width: 8, access_mode: RW, address_offset: 0x28 }
- - - { field_name: N_rn, mm_width: 8, access_mode: RW, address_offset: 0x2C }
- - - { field_name: block_period, mm_width: 16, access_mode: RO, address_offset: 0x30 }
- - - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x34 }
+ - - { field_name: O_si, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: N_si, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: O_rn, mm_width: 8, access_mode: RW, address_offset: 0xC }
+ - - { field_name: N_rn, mm_width: 8, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: block_period, mm_width: 16, access_mode: RO, address_offset: 0x4 }
+ - - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x0 }
+
+
+ - peripheral_name: sdp_crosslets_subband_select # pi_sdp_crosslets_info.py
+ peripheral_description: "SDP crosslets info."
+ mm_ports:
+ # MM port for sdp_info.vhd
+ - mm_port_name: REG_CROSSLETS_INFO
+ mm_port_type: REG
+ mm_port_span: 16 * MM_BUS_SIZE
+ mm_port_description: |
+ "The SDP crosslets info contains the step size and 15 offsets, that are used to select a new
+ crosslet subband for every integration interval"
+ fields:
+ - - { field_name: step, access_mode: RW, address_offset: 0x3C }
+ - - field_name: offset
+ number_of_fields: 15
+ address_offset: 0x0
- peripheral_name: sdp_subband_equalizer # pi_sdp_subband_equalizer.py
peripheral_description: "SDP Subband equalizer coefficients."
parameters:
# Parameters of pi_sdp_subband_equalizer.py, fixed in sdp_subband_equalizer.vhd / sdp_pkg.vhd
- - { name: g_nof_instances, value: 6 } # P_pfb = S_pn / Q_fft = 12 / 2 = 6
+ - { name: P_pfb, value: 6 } # P_pfb = S_pn / Q_fft = 12 / 2 = 6
+ - { name: Q_fft, value: 2 }
+ - { name: N_sub, value: 512 }
mm_ports:
# MM port for sdp_subband_equalizer.vhd
- mm_port_name: RAM_EQUALIZER_GAINS
mm_port_type: RAM
+ mm_port_span: ceil_pow2(Q_fft * N_sub) * MM_BUS_SIZE
mm_port_description: |
- "The subband weigths are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
+ "The subband weigths are stored in P_pfb = S_pn / Q_fft = 6 blocks of
Q_fft * N_sub = 2 * 512 = 1024 complex coefficients as:
(cint16)subband_weights[S_pn/Q_fft]_[Q_fft][N_sub]
where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
- number_of_mm_ports: g_nof_instances
+ number_of_mm_ports: P_pfb
fields:
- - field_name: coef
field_description: |
"Complex coefficient to calibrate the gain and phase per subband. Packed as imaginary in high part,
real in low part of mm_width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
- number_of_fields: 1024 # = Q_fft * N_sub = 2 signal inputs * 512 subbands
+ number_of_fields: Q_fft * N_sub # = 1024 = 2 signal inputs * 512 subbands
address_offset: 0x0
mm_width: 32 # = N_complex * W_sub_weight
radix: cint16_ir
@@ -65,14 +85,17 @@ peripherals:
peripheral_description: "SDP Beamformer weights (= beamlet weights)."
parameters:
# Parameters of pi_sdp_bf_weights.py, fixed in sdp_bf_weights.vhd / sdp_pkg.vhd
- - { name: g_nof_instances, value: 12 } # = N_pol_bf * P_pfb
- - { name: g_nof_gains, value: 976 } # = Q_fft * S_sub_bf
+ - { name: N_pol_bf, value: 2 }
+ - { name: P_pfb, value: 6 } # P_pfb = S_pn / Q_fft = 12 / 2 = 6
+ - { name: Q_fft, value: 2 }
+ - { name: S_sub_bf, value: 488 }
mm_ports:
# MM port for sdp_beamformer_local.vhd / sdp_bf_weights.vhd / mms_dp_gain_serial_arr.vhd
- mm_port_name: RAM_BF_WEIGHTS
mm_port_type: RAM
+ mm_port_span: ceil_pow2(Q_fft * S_sub_bf) * MM_BUS_SIZE
mm_port_description: |
- "The beamlet weigths are stored in g_nof_instances = N_pol_bf * P_pfb = 2 * 6 = 12, where
+ "The beamlet weigths are stored in N_pol_bf * P_pfb = 2 * 6 = 12 instances, where
P_pfb = S_pn / Q_fft = 6. Per instance there is a block of Q_fft * S_sub_bf =
2 * 488 = 976 complex BF weights. The N_pol_bf = 2 represents the two beamformer
polarizations, to distinguish these from the N_pol = 2 antenna polarizations. The
@@ -97,13 +120,13 @@ peripherals:
when index of N_pol_bf and index of N_pol are the same. The cross-polarization BF
weights (XY, YX) are set when index of N_pol_bf and index of N_pol are different. If
no cross-polarization weighting is needed, then these weights can be kept 0."
- number_of_mm_ports: g_nof_instances
+ number_of_mm_ports: N_pol_bf * P_pfb # = 12 = 2 beam polarizations * 6 complex PFB units
fields:
- - field_name: coef
field_description: |
"Complex weight per subband. Packed as imaginary in high part, real in low part
of mm_width = N_complex * W_bf_weight = 2 * 16 = 32 bit."
- number_of_fields: g_nof_gains
+ number_of_fields: Q_fft * S_sub_bf # = 976 = 2 signal inputs * 488 beamlets
address_offset: 0x0
mm_width: 32 # = N_complex * W_bf_weight
radix: cint16_ir
@@ -119,6 +142,7 @@ peripherals:
# MM port for node_sdp_beamformer.vhd / mms_dp_scale.vhd / mms_dp_gain.vhd / mms_dp_gain_arr.vhd
- mm_port_name: REG_BF_SCALE
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: |
"The beamlet scale function scales the beamlet sum with a real scale factor and then
requantizes the result to beamlet data output with less bits.
@@ -136,7 +160,7 @@ peripherals:
number_of_fields: 1
address_offset: 0x0
mm_width: g_gain_w
- #user_width: g_gain_w # EK TODO check parameter passing to user_width
+ #user_width: g_gain_w # EK TODO: check parameter passing to user_width
radix: uint32 # scale factor is unsigned value
resolution_w: 0 - g_lsb_w
- - field_name: unused
@@ -150,6 +174,7 @@ peripherals:
# MM port for sdp_beamformer_output.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
mm_port_type: REG
+ mm_port_span: 64 * MM_BUS_SIZE
mm_port_description: |
"The ETH/IP/UDP/application header fields for the beamlet data output offload UDP packets.
@@ -225,6 +250,7 @@ peripherals:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
mm_port_type: REG
+ mm_port_span: 64 * MM_BUS_SIZE
mm_port_description: |
"The ETH/IP/UDP/application header fields for the SST offload UDP packets.
@@ -293,6 +319,7 @@ peripherals:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
mm_port_type: REG
+ mm_port_span: 64 * MM_BUS_SIZE
mm_port_description: |
"The ETH/IP/UDP/application header fields for the BST offload UDP packets.
@@ -361,6 +388,7 @@ peripherals:
# MM port for sdp_statistics_offload.vhd / dp_offload_tx_v3.vhd
- mm_port_name: REG_DP_OFFLOAD_TX_HDR_DAT
mm_port_type: REG
+ mm_port_span: 64 * MM_BUS_SIZE
mm_port_description: |
"The ETH/IP/UDP/application header fields for the XST offload UDP packets.
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index c2b6942f2a7a57349ae260b8f17091191d80ac55..ae271ee613332fceee60cd871908b4d6690bd0a9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
--- Authors : J Hargreaves, L Hiemstra
+-- Authors : J Hargreaves, L Hiemstra, R van der Walle
-- Purpose:
-- AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
-- Description:
@@ -99,7 +99,8 @@ ENTITY node_sdp_adc_input_and_timing IS
jesd204b_sync_n : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
-- Streaming data output
- out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0)
+ out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
+ dp_bsn_source_restart : OUT STD_LOGIC
);
END node_sdp_adc_input_and_timing;
@@ -123,6 +124,8 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
SIGNAL rx_rst : STD_LOGIC;
SIGNAL rx_sysref : STD_LOGIC;
+ SIGNAL rx_bsn_source_restart : STD_LOGIC;
+
-- Sosis and sosi arrays
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
@@ -209,7 +212,7 @@ BEGIN
GENERIC MAP (
g_nof_streams => c_sdp_S_pn,
g_nof_words => c_sdp_V_sample_delay,
- g_data_w => c_sdp_W_adc_jesd,
+ g_data_w => c_sdp_W_adc,
g_use_sync_in => TRUE
)
PORT MAP (
@@ -252,7 +255,9 @@ BEGIN
reg_miso => reg_bsn_source_v2_miso,
-- Streaming clock domain
- bs_sosi => bs_sosi
+ bs_sosi => bs_sosi,
+
+ bs_restart => rx_bsn_source_restart
);
u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
@@ -387,7 +392,7 @@ BEGIN
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_nof_streams => c_sdp_S_pn,
- g_symbol_w => c_sdp_W_adc_jesd,
+ g_symbol_w => c_sdp_W_adc,
g_nof_symbols_per_data => 1, -- Wideband factor is 1
g_nof_accumulations => g_bsn_nof_clk_per_sync
)
@@ -417,7 +422,7 @@ BEGIN
GENERIC MAP (
g_technology => g_technology,
g_nof_streams => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc_jesd,
+ g_data_w => c_sdp_W_adc,
g_buf_nof_data => g_buf_nof_data,
g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
@@ -441,28 +446,31 @@ BEGIN
-- Output Stage
-- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
-----------------------------------------------------------------------------
-
- gen_dp_fifo_dc : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
- u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_data_w => c_sdp_W_adc_jesd,
- g_use_empty => FALSE, --TRUE,
- g_use_ctrl => TRUE,
- g_use_sync => TRUE,
- g_use_bsn => TRUE,
- g_fifo_size => c_dp_fifo_dc_size
- )
- PORT MAP (
- wr_rst => rx_rst,
- wr_clk => rx_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
- snk_in => st_sosi_arr(I),
- src_out => out_sosi_arr(I)
- );
- END GENERATE;
+ u_dp_fifo_dc_arr : ENTITY dp_lib.dp_fifo_dc_arr
+ GENERIC MAP (
+ g_nof_streams => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_bsn_w => c_bs_bsn_w,
+ g_use_empty => FALSE,
+ g_use_ctrl => TRUE,
+ g_use_sync => TRUE,
+ g_use_bsn => TRUE,
+ g_use_aux => TRUE,
+ g_fifo_size => c_dp_fifo_dc_size
+ )
+ PORT MAP (
+ wr_rst => rx_rst,
+ wr_clk => rx_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+ snk_in_arr => st_sosi_arr,
+ src_out_arr => out_sosi_arr,
+ in_aux(0) => rx_bsn_source_restart,
+ out_aux(0) => dp_bsn_source_restart
+ );
- -----------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 1a28839eecb89d4fec64d3176b3d0bed61bb06d9..47b5fe4db662beeb34011a709bb341c35c57a558 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -60,8 +60,8 @@ ENTITY node_sdp_correlator IS
reg_crosslets_info_miso : OUT t_mem_miso;
reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso;
--sdp_info : IN t_sdp_info;
--gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -75,7 +75,10 @@ ENTITY node_sdp_correlator IS
END node_sdp_correlator;
ARCHITECTURE str OF node_sdp_correlator IS
-
+
+ CONSTANT c_nof_blk_per_sync_max : NATURAL := c_sdp_xst_nof_blk_per_sync_max;
+ CONSTANT c_nof_blk_per_sync_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min;
+
-- CONSTANT c_nof_masters : POSITIVE := 2;
-- crosslet statistics offload
@@ -126,8 +129,8 @@ BEGIN
u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
GENERIC MAP (
g_nof_streams => c_sdp_P_pfb,
- g_nof_blk_per_sync => 200000,
- g_nof_blk_per_sync_min => 19530
+ g_nof_blk_per_sync => c_nof_blk_per_sync_max,
+ g_nof_blk_per_sync_min => c_nof_blk_per_sync_min
)
PORT MAP (
dp_rst => dp_rst,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index cea8db61daf21b5f74863ceeddee8085124c7e26..a30bf342f7766974952a2bc51bdb9824b95d587d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -63,8 +63,10 @@ ENTITY node_sdp_filterbank IS
sst_udp_sosi : OUT t_dp_sosi;
sst_udp_siso : IN t_dp_siso := c_dp_siso_rst;
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ dp_bsn_source_restart : IN STD_LOGIC;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
reg_si_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_si_miso : OUT t_mem_miso;
@@ -99,6 +101,8 @@ ARCHITECTURE str OF node_sdp_filterbank IS
CONSTANT c_nof_masters : POSITIVE := 2;
+ CONSTANT c_si_pipeline : NATURAL := 1;
+
SIGNAL ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -118,7 +122,10 @@ ARCHITECTURE str OF node_sdp_filterbank IS
SIGNAL subband_equalizer_out_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL dp_selector_out_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL scope_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn-1 DOWNTO 0);
-
+
+ SIGNAL selector_en : STD_LOGIC;
+ SIGNAL subband_calibrated_flag : STD_LOGIC;
+ SIGNAL dp_bsn_source_restart_pipe : STD_LOGIC;
BEGIN
---------------------------------------------------------------
-- SPECTRAL INVERSION
@@ -126,7 +133,7 @@ BEGIN
u_si_arr : ENTITY si_lib.si_arr
GENERIC MAP (
g_nof_streams => c_sdp_S_pn,
- g_pipeline => 1,
+ g_pipeline => c_si_pipeline,
g_dat_w => c_sdp_W_adc
)
PORT MAP(
@@ -154,7 +161,19 @@ BEGIN
wpfb_unit_in_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(si_sosi_arr(2*I+1).data);
END LOOP;
END PROCESS;
-
+
+ -- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
+ u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
+ GENERIC MAP (
+ g_pipeline => c_si_pipeline
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
+
-- PFB
u_wpfb_unit_dev : ENTITY wpfb_lib.wpfb_unit_dev
GENERIC MAP (
@@ -162,7 +181,8 @@ BEGIN
g_use_prefilter => TRUE,
g_stats_ena => FALSE,
g_use_bg => FALSE,
- g_coefs_file_prefix => c_coefs_file_prefix
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => FALSE
)
PORT MAP (
dp_rst => dp_rst,
@@ -175,7 +195,9 @@ BEGIN
in_sosi_arr => wpfb_unit_in_sosi_arr,
fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_sosi_arr => wpfb_unit_out_sosi_arr
+ out_sosi_arr => wpfb_unit_out_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
);
-- Output PFB streams
@@ -224,7 +246,9 @@ BEGIN
pipe_sosi_arr => wpfb_unit_out_sosi_arr,
ref_sosi_arr => subband_equalizer_out_sosi_arr,
- out_sosi_arr => dp_selector_out_sosi_arr
+ out_sosi_arr => dp_selector_out_sosi_arr,
+
+ selector_en => selector_en
);
---------------------------------------------------------------
@@ -307,6 +331,8 @@ BEGIN
---------------------------------------------------------------
-- STATISTICS OFFLOAD
---------------------------------------------------------------
+ subband_calibrated_flag <= NOT selector_en;
+
u_sdp_sst_udp_offload: ENTITY work.sdp_statistics_offload
GENERIC MAP (
g_statistics_type => "SST",
@@ -330,6 +356,7 @@ BEGIN
sdp_info => sdp_info,
gn_index => TO_UINT(gn_id),
+ subband_calibrated_flag => subband_calibrated_flag,
in_sosi => dp_selector_out_sosi_arr(0),
out_sosi => sst_udp_sosi,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 5400b70e891a44d1835da0be6150ebb100f02824..6186496de7639b08c7c70444aa041e917c994603 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -167,6 +167,7 @@ BEGIN
BEGIN
v := r;
v.col_select_mosi := c_mem_mosi_rst;
+ v_offsets := r.offsets;
-- start/restart
IF start_trigger = '1' THEN
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
index bcd6e5a201e0665eca382bc41940a8684bfe3273..e3497967e850d654ab0c24440e158f6a6442e680 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
@@ -60,7 +60,7 @@ END sdp_info_reg;
ARCHITECTURE str OF sdp_info_reg IS
- CONSTANT c_field_arr : t_common_field_arr(13 DOWNTO 0) :=
+ CONSTANT c_field_arr : t_common_field_arr(12 DOWNTO 0) :=
( (field_name_pad("station_id"), "RW", 16, field_default(0)),
(field_name_pad("antenna_band_index"), "RO", 1, field_default(0)),
(field_name_pad("observation_id"), "RW", 32, field_default(0)),
@@ -68,7 +68,6 @@ ARCHITECTURE str OF sdp_info_reg IS
(field_name_pad("f_adc"), "RO", 1, field_default(0)),
(field_name_pad("fsub_type"), "RO", 1, field_default(0)),
(field_name_pad("beam_repositioning_flag"), "RW", 1, field_default(0)),
- (field_name_pad("subband_calibrated_flag"), "RW", 1, field_default(0)),
(field_name_pad("O_si"), "RW", 8, field_default(0)),
(field_name_pad("N_si"), "RW", 8, field_default(0)),
(field_name_pad("O_rn"), "RW", 8, field_default(0)),
@@ -131,7 +130,6 @@ BEGIN
sdp_info_wr.observation_id <= mm_fields_out(field_hi(c_field_arr, "observation_id") DOWNTO field_lo(c_field_arr, "observation_id"));
sdp_info_wr.nyquist_zone_index <= mm_fields_out(field_hi(c_field_arr, "nyquist_zone_index") DOWNTO field_lo(c_field_arr, "nyquist_zone_index"));
sdp_info_wr.beam_repositioning_flag <= sl(mm_fields_out(field_hi(c_field_arr, "beam_repositioning_flag") DOWNTO field_lo(c_field_arr, "beam_repositioning_flag")));
- sdp_info_wr.subband_calibrated_flag <= sl(mm_fields_out(field_hi(c_field_arr, "subband_calibrated_flag") DOWNTO field_lo(c_field_arr, "subband_calibrated_flag")));
sdp_info_wr.O_si <= mm_fields_out(field_hi(c_field_arr, "O_si") DOWNTO field_lo(c_field_arr, "O_si"));
sdp_info_wr.N_si <= mm_fields_out(field_hi(c_field_arr, "N_si") DOWNTO field_lo(c_field_arr, "N_si"));
sdp_info_wr.O_rn <= mm_fields_out(field_hi(c_field_arr, "O_rn") DOWNTO field_lo(c_field_arr, "O_rn"));
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 00b4b5ed89099bea08523565cf334bf162088f70..25745ee6f4b2179b3b16fa5617c88c89e11cb146 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -51,7 +51,6 @@ PACKAGE sdp_pkg is
f_adc : STD_LOGIC;
fsub_type : STD_LOGIC;
beam_repositioning_flag : STD_LOGIC;
- subband_calibrated_flag : STD_LOGIC;
O_si : STD_LOGIC_VECTOR(7 DOWNTO 0);
N_si : STD_LOGIC_VECTOR(7 DOWNTO 0);
O_rn : STD_LOGIC_VECTOR(7 DOWNTO 0);
@@ -62,7 +61,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_info_rst : t_sdp_info :=
( (OTHERS => '0'), '0', (OTHERS => '0'), (OTHERS => '0'),
- '0', '0', '0', '0',
+ '0', '0', '0',
(OTHERS => '0'), (OTHERS => '0'), (OTHERS => '0'), (OTHERS => '0'),
(OTHERS => '0'), (OTHERS => '0') );
@@ -101,12 +100,14 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_W_subband : NATURAL := 18;
-- Derived constants
+ CONSTANT c_sdp_FS_adc : NATURAL := 2**(c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0
CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft;
CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps;
CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc;
CONSTANT c_sdp_W_bf_fraction : NATURAL := c_sdp_W_bf_weight - c_sdp_W_bf_magnitude -1;
CONSTANT c_sdp_W_bf_product : NATURAL := c_sdp_W_subband + c_sdp_W_bf_weight -1;
CONSTANT c_sdp_W_sub_fraction : NATURAL := c_sdp_W_sub_weight - c_sdp_W_sub_magnitude -1;
+ CONSTANT c_sdp_X_sq : NATURAL := c_sdp_S_pn * c_sdp_S_pn;
--
CONSTANT c_sdp_marker_sst : NATURAL := 83; -- = 0x53 = 'S'
@@ -138,54 +139,74 @@ PACKAGE sdp_pkg is
true, 54, 2, 195313, c_fft_pipeline, c_fft_pipeline,
c_fil_ppf_pipeline);
- -- JESD204
- CONSTANT c_sdp_jesd204b_freq : STRING := "200MHz";
- CONSTANT c_sdp_jesd204b_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ -- statistics offload
+ -- The statistics offload uses the same 1GbE port as the NiosII for M&C. The 1GbE addresses defined in SW and here in FW.
+ -- See NiosII code:
+ -- https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
+ -- https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
+ -- and g_base_ip = x"0A63" in:
+ -- https://git.astron.nl/desp/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
- -- AIT MM address widths
- CONSTANT c_sdp_jesd204b_addr_w : NATURAL := 8 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_jesd_ctrl_addr_w : NATURAL := 1;
- CONSTANT c_sdp_reg_bsn_monitor_input_addr_w : NATURAL := 8;
- CONSTANT c_sdp_reg_wg_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_ram_wg_addr_w : NATURAL := 10 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_reg_dp_shiftram_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_reg_bsn_source_v2_addr_w : NATURAL := 3;
- CONSTANT c_sdp_reg_bsn_scheduler_addr_w : NATURAL := 1;
- CONSTANT c_sdp_ram_diag_data_buf_bsn_addr_w : NATURAL := ceil_log2(c_sdp_S_pn*c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
- CONSTANT c_sdp_reg_diag_data_buf_bsn_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_reg_aduh_monitor_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_stat_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 00:22:86:08:pp:qq
+ CONSTANT c_sdp_stat_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0A63"; -- 10.99.xx.yy
+ CONSTANT c_sdp_sst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D0"; -- TBC
+ CONSTANT c_sdp_bst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D1"; -- TBC
+ CONSTANT c_sdp_xst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D2"; -- TBC
- -- FSUB MM address widths
- CONSTANT c_sdp_ram_fil_coefs_addr_w : NATURAL := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
- CONSTANT c_sdp_ram_st_sst_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft*c_sdp_wpfb_subbands.stat_data_sz);
- CONSTANT c_sdp_reg_si_addr_w : NATURAL := 1; --enable/disable
- CONSTANT c_sdp_ram_equalizer_gains_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft);
- CONSTANT c_sdp_reg_dp_selector_addr_w : NATURAL := 1; --Select input 0 or 1.
+ CONSTANT c_sdp_stat_nof_hdr_fields : NATURAL := 1+3+12+4+20+1; -- 592b; 18.5 32b words
+ CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111111111001"&"0111"&"0100"&"000000000"&"0000100"&"0"; -- 0=data path, 1=MM controlled TODO
+--CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"000000010"&"1000000"&"0"; -- 0=data path, 1=MM controlled TODO
- -- BF MM address widths
- CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
- CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+ CONSTANT c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := (
+ ( field_name_pad("word_align" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B217176B9") ), -- 001B217176B9 = DOP36-enp2s0
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
- -- SST UDP offload MM address widths
- CONSTANT c_sdp_reg_stat_enable_addr_w :NATURAL := 1;
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(4156) ),
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A6300FE") ), -- 0A6300FE = DOP36-enp2s0 '10.99.0.254'
- -- XSUB
- CONSTANT c_sdp_crosslets_index_w : NATURAL := ceil_log2(c_sdp_N_sub);
- CONSTANT c_sdp_mm_reg_crosslets_info : t_c_mem := (latency => 1,
- adr_w => 4,
- dat_w => c_sdp_crosslets_index_w,
- nof_dat => 16, -- 15 offsets + 1 step
- init_sl => '0');
- CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w;
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(5001) ),
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(4136) ),
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(5) ),
+ ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_station_id" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_subband_calibrated_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_reserved" ), "RW", 3, field_default(0) ),
+ ( field_name_pad("sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
+
+ ( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
+ ( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("sdp_nof_signal_inputs" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("sdp_nof_bytes_per_statistics" ), "RW", 8, field_default(8) ),
+ ( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(0) ),
+
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ );
+ CONSTANT c_sdp_reg_stat_hdr_dat_addr_w : NATURAL := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
-- 10GbE offload (cep = central processor)
CONSTANT c_sdp_cep_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
@@ -244,81 +265,70 @@ PACKAGE sdp_pkg is
( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
+ -- ST UDP offload MM address widths
+ CONSTANT c_sdp_reg_stat_enable_addr_w : NATURAL := 1;
-- 10GbE MM address widths
CONSTANT c_sdp_reg_hdr_dat_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
CONSTANT c_sdp_reg_nw_10GbE_mac_addr_w : NATURAL := 13;
CONSTANT c_sdp_reg_nw_10GbE_eth10g_addr_w : NATURAL := 1;
- -- statistics offload
- -- The statistics offload uses the same 1GbE port as the NiosII for M&C. The 1GbE addresses defined in SW and here in FW.
- -- See NiosII code:
- -- https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
- -- https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
- -- and g_base_ip = x"0A63" in:
- -- https://git.astron.nl/desp/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
-
- CONSTANT c_sdp_stat_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 00:22:86:08:pp:qq
- CONSTANT c_sdp_stat_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0A63"; -- 10.99.xx.yy
- CONSTANT c_sdp_sst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D0"; -- TBC
- CONSTANT c_sdp_bst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D1"; -- TBC
- CONSTANT c_sdp_xst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D2"; -- TBC
-
- CONSTANT c_sdp_stat_nof_hdr_fields : NATURAL := 1+3+12+4+20+1; -- 592b; 18.5 32b words
- CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111111111001"&"0111"&"0100"&"000000000"&"0000100"&"0"; -- 0=data path, 1=MM controlled TODO
---CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"000000010"&"1000000"&"0"; -- 0=data path, 1=MM controlled TODO
-
- CONSTANT c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := (
- ( field_name_pad("word_align" ), "RW", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B217176B9") ), -- 001B217176B9 = DOP36-enp2s0
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+ -- JESD204
+ CONSTANT c_sdp_jesd204b_freq : STRING := "200MHz";
+ CONSTANT c_sdp_jesd204b_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(4156) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A6300FE") ), -- 0A6300FE = DOP36-enp2s0 '10.99.0.254'
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(5001) ),
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(4136) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ -- AIT MM address widths
+ CONSTANT c_sdp_jesd204b_addr_w : NATURAL := 8 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_jesd_ctrl_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_reg_bsn_monitor_input_addr_w : NATURAL := 8;
+ CONSTANT c_sdp_reg_wg_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_ram_wg_addr_w : NATURAL := 10 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_reg_dp_shiftram_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_reg_bsn_source_v2_addr_w : NATURAL := 3;
+ CONSTANT c_sdp_reg_bsn_scheduler_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_ram_diag_data_buf_bsn_addr_w : NATURAL := ceil_log2(c_sdp_S_pn*c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
+ CONSTANT c_sdp_reg_diag_data_buf_bsn_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
+ CONSTANT c_sdp_reg_aduh_monitor_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
- ( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ),
- ( field_name_pad("sdp_version_id" ), "RW", 8, field_default(5) ),
- ( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_station_id" ), "RW", 16, field_default(0) ),
+ -- FSUB MM address widths
+ CONSTANT c_sdp_ram_fil_coefs_addr_w : NATURAL := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
+ CONSTANT c_sdp_ram_st_sst_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft*c_sdp_wpfb_subbands.stat_data_sz);
+ CONSTANT c_sdp_reg_si_addr_w : NATURAL := 1; --enable/disable
+ CONSTANT c_sdp_ram_equalizer_gains_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft);
+ CONSTANT c_sdp_reg_dp_selector_addr_w : NATURAL := 1; --Select input 0 or 1.
- ( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
- ( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_subband_calibrated_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_reserved" ), "RW", 3, field_default(0) ),
- ( field_name_pad("sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
+ -- BF MM address widths
+ CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+ CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
+ CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w: NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
- ( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
- ( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
- ( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
- ( field_name_pad("sdp_nof_signal_inputs" ), "RW", 8, field_default(0) ),
- ( field_name_pad("sdp_nof_bytes_per_statistics" ), "RW", 8, field_default(8) ),
- ( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
- ( field_name_pad("sdp_block_period" ), "RW", 16, field_default(0) ),
+ -- XSUB
+ CONSTANT c_sdp_crosslets_index_w : NATURAL := ceil_log2(c_sdp_N_sub);
+ CONSTANT c_sdp_mm_reg_crosslets_info : t_c_mem := (latency => 1,
+ adr_w => 4,
+ dat_w => c_sdp_crosslets_index_w,
+ nof_dat => 16, -- 15 offsets + 1 step
+ init_sl => '0');
+ CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w;
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
- );
- CONSTANT c_sdp_reg_stat_hdr_dat_addr_w : NATURAL := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
+ CONSTANT c_sdp_xst_nof_blk_per_sync_max : NATURAL := 200000;
+ CONSTANT c_sdp_xst_nof_blk_per_sync_min : NATURAL := 19530;
+ -- XSUB MM address widths
+ CONSTANT c_sdp_reg_dp_sync_insert_v2_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
+ CONSTANT c_sdp_reg_bsn_scheduler_xsub_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
END PACKAGE sdp_pkg;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 8a5953606a796ee0ac203c5265b200167b5ace99..dce30f2147dcd9cf534c73e145618a69d9fc2f59 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -74,10 +74,11 @@ ENTITY sdp_statistics_offload IS
out_siso : IN t_dp_siso;
-- inputs from other blocks
- eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- sdp_info : IN t_sdp_info;
+ eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ sdp_info : IN t_sdp_info;
+ subband_calibrated_flag : IN STD_LOGIC := '0';
gn_index : IN NATURAL
);
@@ -168,7 +169,7 @@ BEGIN
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type" )) <= SLV(sdp_info.fsub_type);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error" )) <= SLV(r.payload_err);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag" )) <= SLV(sdp_info.beam_repositioning_flag);
- dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" )) <= SLV(sdp_info.subband_calibrated_flag);
+ dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" )) <= SLV(subband_calibrated_flag);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved" )) <= (OTHERS => '0');
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" )) <= TO_UVEC(gn_index, 5);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_reserved" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_reserved" )) <= (OTHERS => '0');
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index 2f691bdbcdd74a93cb43dd6db278bf85d1fcab60..e5dd58d4268f8d3efbd19229577b823a42c17d19 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -58,14 +58,13 @@ ARCHITECTURE tb OF tb_sdp_info IS
CONSTANT c_mm_addr_O_rn : NATURAL := 3;
CONSTANT c_mm_addr_N_si : NATURAL := 4;
CONSTANT c_mm_addr_O_si : NATURAL := 5;
- CONSTANT c_mm_addr_subband_calibrated_flag : NATURAL := 6;
- CONSTANT c_mm_addr_beam_repositioning_flag : NATURAL := 7;
- CONSTANT c_mm_addr_fsub_type : NATURAL := 8;
- CONSTANT c_mm_addr_f_adc : NATURAL := 9;
- CONSTANT c_mm_addr_nyquist_zone_index : NATURAL := 10;
- CONSTANT c_mm_addr_observation_id : NATURAL := 11;
- CONSTANT c_mm_addr_antenna_band_index : NATURAL := 12;
- CONSTANT c_mm_addr_station_id : NATURAL := 13;
+ CONSTANT c_mm_addr_beam_repositioning_flag : NATURAL := 6;
+ CONSTANT c_mm_addr_fsub_type : NATURAL := 7;
+ CONSTANT c_mm_addr_f_adc : NATURAL := 8;
+ CONSTANT c_mm_addr_nyquist_zone_index : NATURAL := 9;
+ CONSTANT c_mm_addr_observation_id : NATURAL := 10;
+ CONSTANT c_mm_addr_antenna_band_index : NATURAL := 11;
+ CONSTANT c_mm_addr_station_id : NATURAL := 12;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL tb_mm_reg_end : STD_LOGIC := '0';
@@ -110,7 +109,6 @@ BEGIN
proc_mem_mm_bus_wr(c_mm_addr_O_rn ,13 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_N_si ,14 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_O_si ,15 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_subband_calibrated_flag,1 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_beam_repositioning_flag,1 ,mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_wr(c_mm_addr_fsub_type ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
proc_mem_mm_bus_wr(c_mm_addr_f_adc ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
@@ -144,10 +142,6 @@ BEGIN
mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mm_natural_response = 15 REPORT "wrong O_si" SEVERITY ERROR;
- proc_mem_mm_bus_rd(c_mm_addr_subband_calibrated_flag, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
- mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1);
- ASSERT mm_natural_response = 1 REPORT "wrong subband_calibrated_flag" SEVERITY ERROR;
-
proc_mem_mm_bus_rd(c_mm_addr_beam_repositioning_flag, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mm_natural_response = 1 REPORT "wrong beam_repositioning_flag" SEVERITY ERROR;
@@ -235,7 +229,6 @@ BEGIN
ASSERT TO_UINT(sdp_info.O_rn) = 13 REPORT "wrong sdp_info.O_rn value" SEVERITY ERROR;
ASSERT TO_UINT(sdp_info.N_si) = 14 REPORT "wrong sdp_info.N_si value" SEVERITY ERROR;
ASSERT TO_UINT(sdp_info.O_si) = 15 REPORT "wrong sdp_info.O_si value" SEVERITY ERROR;
- ASSERT sdp_info.subband_calibrated_flag = '1' REPORT "wrong sdp_info.subband_calibrated_flag value" SEVERITY ERROR;
ASSERT sdp_info.beam_repositioning_flag = '1' REPORT "wrong sdp_info.beam_repositioning_flag value" SEVERITY ERROR;
ASSERT sdp_info.fsub_type = '1' REPORT "wrong sdp_info.fsub_type value" SEVERITY ERROR;
ASSERT sdp_info.f_adc = '1' REPORT "wrong sdp_info.f_adc value" SEVERITY ERROR;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 751119c7d17c5a81dc1d7a0544e5f43001d2cf3c..ad26814881b3aa41ff5e9114e3f3128ca294f5d8 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -145,7 +145,6 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
'0', -- f_adc
'1', -- fsub_type
'0', -- beam_repositioning_flag
- '1', -- subband_calibrated_flag
x"01", -- O_si
x"02", -- N_si
x"04", -- O_rn
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 58bd7d22dccf0090f87864f2266bd4a486847293..b74bbd3a32ca0092cb3dbdf5e7165cf2cc0fe0a2 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -701,6 +701,8 @@ Start --> Administration --> Synaptic package manager
> sudo pip install numpy # to run Python2 library installer as root
> sudo pip3 install numpy # to run Python3 library installer as root
+> sudo apt-get install python3-tk # worked, now I can do: python3 test_plot.py
+
> sudo apt-get install pip # to install Python2 library installer
> sudo apt-get install python-matplotlib
diff --git a/libraries/base/common/common.peripheral.yaml b/libraries/base/common/common.peripheral.yaml
index 5d06bbdbda5d1d9331af904518ebbc63f6a51c9d..ea7a6033b7663732f36bca0048823bee4788c94c 100644
--- a/libraries/base/common/common.peripheral.yaml
+++ b/libraries/base/common/common.peripheral.yaml
@@ -17,6 +17,7 @@ peripherals:
# MM port for mms_common_variable_delay.vhd / mms_common_reg.vhd
- mm_port_name: REG_COMMON_VARIABLE_DELAY
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: enable
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 79591b0b305fbab6107ee2acb05afe6e709a73ef..ba09970a6f98b5f6896ef7036894ca27fa5b024f 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -325,36 +325,42 @@ PACKAGE common_pkg IS
-- . Note that using func_slv_concat() without the BOOLEAN use_* is equivalent to using the
-- slv concatenation operator & directly. However this overloaded func_slv_concat() is
-- still nice to have, because it shows the relation with the inverse func_slv_extract().
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c, use_d : BOOLEAN; a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b, use_c : BOOLEAN; a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( use_a, use_b : BOOLEAN; a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat( a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_concat_w(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL) RETURN NATURAL;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( use_a, use_b : BOOLEAN; a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
- FUNCTION func_slv_extract( a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c, use_d : BOOLEAN; a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b, use_c : BOOLEAN; a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( use_a, use_b : BOOLEAN; a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat( a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_concat_w(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL) RETURN NATURAL;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( use_a, use_b : BOOLEAN; a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_slv_extract( a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION TO_UINT(vec : STD_LOGIC_VECTOR) RETURN NATURAL; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
FUNCTION TO_SINT(vec : STD_LOGIC_VECTOR) RETURN INTEGER;
@@ -1508,10 +1514,9 @@ PACKAGE BODY common_pkg IS
RETURN v_mat;
END;
-
- -- Support concatenation of up to 7 slv into 1 slv
- FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
- CONSTANT c_max_w : NATURAL := a'LENGTH + b'LENGTH + c'LENGTH + d'LENGTH + e'LENGTH + f'LENGTH + g'LENGTH;
+ -- Support concatenation of up to 8 slv into 1 slv
+ FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ CONSTANT c_max_w : NATURAL := a'LENGTH + b'LENGTH + c'LENGTH + d'LENGTH + e'LENGTH + f'LENGTH + g'LENGTH + h'LENGTH;
VARIABLE v_res : STD_LOGIC_VECTOR(c_max_w-1 DOWNTO 0) := (OTHERS=>'0');
VARIABLE v_len : NATURAL := 0;
BEGIN
@@ -1522,34 +1527,45 @@ PACKAGE BODY common_pkg IS
IF use_e = TRUE THEN v_res(e'LENGTH-1 + v_len DOWNTO v_len) := e; v_len := v_len + e'LENGTH; END IF;
IF use_f = TRUE THEN v_res(f'LENGTH-1 + v_len DOWNTO v_len) := f; v_len := v_len + f'LENGTH; END IF;
IF use_g = TRUE THEN v_res(g'LENGTH-1 + v_len DOWNTO v_len) := g; v_len := v_len + g'LENGTH; END IF;
+ IF use_h = TRUE THEN v_res(h'LENGTH-1 + v_len DOWNTO v_len) := h; v_len := v_len + h'LENGTH; END IF;
RETURN v_res(v_len-1 DOWNTO 0);
END func_slv_concat;
-
+
+ FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g, FALSE, a, b, c, d, e, f, g, "0");
+ END func_slv_concat;
+
FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a, b, c, d, e, f : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, a, b, c, d, e, f, "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, FALSE, a, b, c, d, e, f, "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a, b, c, d, e : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, a, b, c, d, e, "0", "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, FALSE, a, b, c, d, e, "0", "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b, use_c, use_d : BOOLEAN; a, b, c, d : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, a, b, c, d, "0", "0", "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, FALSE, a, b, c, d, "0", "0", "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b, use_c : BOOLEAN; a, b, c : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, a, b, c, "0", "0", "0", "0");
+ RETURN func_slv_concat(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, FALSE, a, b, c, "0", "0", "0", "0", "0");
END func_slv_concat;
FUNCTION func_slv_concat(use_a, use_b : BOOLEAN; a, b : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_concat(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a, b, "0", "0", "0", "0", "0");
+ RETURN func_slv_concat(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, a, b, "0", "0", "0", "0", "0", "0");
END func_slv_concat;
-
+
+ FUNCTION func_slv_concat(a, b, c, d, e, f, g, h : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a, b, c, d, e, f, g, h);
+ END func_slv_concat;
+
FUNCTION func_slv_concat(a, b, c, d, e, f, g : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN func_slv_concat(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a, b, c, d, e, f, g);
@@ -1580,7 +1596,7 @@ PACKAGE BODY common_pkg IS
RETURN func_slv_concat(TRUE, TRUE, a, b);
END func_slv_concat;
- FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL IS
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL) RETURN NATURAL IS
VARIABLE v_len : NATURAL := 0;
BEGIN
IF use_a = TRUE THEN v_len := v_len + a_w; END IF;
@@ -1590,36 +1606,42 @@ PACKAGE BODY common_pkg IS
IF use_e = TRUE THEN v_len := v_len + e_w; END IF;
IF use_f = TRUE THEN v_len := v_len + f_w; END IF;
IF use_g = TRUE THEN v_len := v_len + g_w; END IF;
+ IF use_h = TRUE THEN v_len := v_len + h_w; END IF;
RETURN v_len;
END func_slv_concat_w;
-
+
+ FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL) RETURN NATURAL IS
+ BEGIN
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, use_g, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, 0);
+ END func_slv_concat_w;
+
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0, 0);
END func_slv_concat_w;
FUNCTION func_slv_concat_w(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL) RETURN NATURAL IS
BEGIN
- RETURN func_slv_concat_w(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0);
+ RETURN func_slv_concat_w(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0, 0);
END func_slv_concat_w;
-
+
-- extract slv
- FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g, use_h : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
VARIABLE v_w : NATURAL := 0;
VARIABLE v_lo : NATURAL := 0;
BEGIN
@@ -1660,36 +1682,55 @@ PACKAGE BODY common_pkg IS
IF use_d = TRUE THEN v_lo := v_lo + d_w; END IF;
IF use_e = TRUE THEN v_lo := v_lo + e_w; END IF;
IF use_f = TRUE THEN v_lo := v_lo + f_w; END IF;
+ WHEN 7 =>
+ IF use_h = TRUE THEN v_w := h_w; ELSE RETURN c_slv0(h_w-1 DOWNTO 0); END IF;
+ IF use_a = TRUE THEN v_lo := v_lo + a_w; END IF;
+ IF use_b = TRUE THEN v_lo := v_lo + b_w; END IF;
+ IF use_c = TRUE THEN v_lo := v_lo + c_w; END IF;
+ IF use_d = TRUE THEN v_lo := v_lo + d_w; END IF;
+ IF use_e = TRUE THEN v_lo := v_lo + e_w; END IF;
+ IF use_f = TRUE THEN v_lo := v_lo + f_w; END IF;
+ IF use_g = TRUE THEN v_lo := v_lo + g_w; END IF;
WHEN OTHERS => REPORT "Unknown common_pkg func_slv_extract argument" SEVERITY FAILURE;
END CASE;
RETURN vec(v_w-1 + v_lo DOWNTO v_lo); -- extracted slv
END func_slv_extract;
-
+
+ FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, use_g, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, 0, vec, sel);
+ END func_slv_extract;
+
FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f : BOOLEAN; a_w, b_w, c_w, d_w, e_w, f_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, use_f, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, f_w, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b, use_c, use_d, use_e : BOOLEAN; a_w, b_w, c_w, d_w, e_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, use_e, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, e_w, 0, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b, use_c, use_d : BOOLEAN; a_w, b_w, c_w, d_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, use_d, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, d_w, 0, 0, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b, use_c : BOOLEAN; a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, use_c, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, c_w, 0, 0, 0, 0, 0, vec, sel);
END func_slv_extract;
FUNCTION func_slv_extract(use_a, use_b : BOOLEAN; a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN func_slv_extract(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
+ RETURN func_slv_extract(use_a, use_b, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, a_w, b_w, 0, 0, 0, 0, 0, 0, vec, sel);
END func_slv_extract;
-
+
+ FUNCTION func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, h_w, vec, sel);
+ END func_slv_extract;
+
FUNCTION func_slv_extract(a_w, b_w, c_w, d_w, e_w, f_w, g_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN func_slv_extract(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, a_w, b_w, c_w, d_w, e_w, f_w, g_w, vec, sel);
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
index ac86812ef1440c831599e5e484f71145a97cec63..8081e7e15c2f3168838d7ac8112d02f52d705ccb 100644
--- a/libraries/base/diag/diag.peripheral.yaml
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -15,6 +15,7 @@ peripherals:
# MM port for diag_wg_wideband_reg.vhd
- mm_port_name: REG_DIAG_WG
mm_port_type: REG
+ mm_port_span: 4 * MM_BUS_SIZE
mm_port_description: "Waveform control."
number_of_mm_ports: g_nof_streams
fields:
@@ -51,6 +52,7 @@ peripherals:
# MM port for mms_diag_wg_wideband.vhd
- mm_port_name: RAM_DIAG_WG
mm_port_type: RAM
+ mm_port_span: 1024 * MM_BUS_SIZE
mm_port_description: "Waveform buffer."
number_of_mm_ports: g_nof_streams
fields:
@@ -72,6 +74,7 @@ peripherals:
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: REG_DIAG_DB
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: "Data buffer status."
number_of_mm_ports: g_nof_streams
fields:
@@ -86,6 +89,7 @@ peripherals:
# MM port for mms_diag_data_buffer.vhd
- mm_port_name: RAM_DIAG_DB
mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_nof_data * ceil_div(g_data_w, c_word_w)) * MM_BUS_SIZE
mm_port_description: "Data buffer memory, gets filled after the sync when g_use_in_sync = True, else after the last word was read."
number_of_mm_ports: g_nof_streams
fields:
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 7a8008c0e8addecda2dee9e1579f39f0fd09c9d6..22ec8afb33b8e8755a86d7093a3b075c41408d9c 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -12,6 +12,7 @@ peripherals:
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm_reg.vhd
- mm_port_name: REG_DPMM_CTRL
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: "DPMM = Monitor the DP to MM read FIFO."
fields:
- - field_name: rd_usedw
@@ -21,6 +22,7 @@ peripherals:
# MM port for mms_dp_fifo_to_mm.vhd / dp_fifo_to_mm.vhd
- mm_port_name: REG_DPMM_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_dpmm.py
mm_port_type: FIFO
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: "DPMM = read word from the DP to MM read FIFO"
fields:
- - field_name: rd_data
@@ -35,6 +37,7 @@ peripherals:
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm_reg.vhd
- mm_port_name: REG_MMDP_CTRL
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: "MMDP = Monitor the MM to DP write FIFO."
fields:
- - field_name: wr_usedw
@@ -49,6 +52,7 @@ peripherals:
# MM port for mms_dp_fifo_from_mm.vhd / dp_fifo_from_mm.vhd
- mm_port_name: REG_MMDP_DATA # Use REG_, instead of preferred FIFO_, to match mm_port_name in pi_mmdp.py
mm_port_type: FIFO
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: "MMDP = write word to the MM to DP write FIFO."
fields:
- - field_name: data
@@ -67,6 +71,7 @@ peripherals:
# MM port for mms_dp_xonoff.vhd
- mm_port_name: REG_DP_XONOFF
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: "When g_combine_streams = False then there is one enable bit per stream, else there is one enable bit for all streams."
fields:
- - field_name: enable_stream
@@ -90,6 +95,7 @@ peripherals:
# MM port for dp_shiftram.vhd
- mm_port_name: REG_DP_SHIFTRAM
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: ""
number_of_mm_ports: g_nof_streams
fields:
@@ -109,6 +115,7 @@ peripherals:
# MM port for dp_bsn_source_reg.vhd
- mm_port_name: REG_DP_BSN_SOURCE
mm_port_type: REG
+ mm_port_span: 4 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: dp_on
@@ -148,6 +155,7 @@ peripherals:
# MM port for dp_bsn_source_reg_v2.vhd
- mm_port_name: REG_DP_BSN_SOURCE_V2
mm_port_type: REG
+ mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: dp_on
@@ -187,6 +195,7 @@ peripherals:
# MM port for dp_bsn_scheduler_reg.vhd
- mm_port_name: REG_DP_BSN_SCHEDULER
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: scheduled_bsn
@@ -206,6 +215,7 @@ peripherals:
# MM port for dp_bsn_monitor_reg.vhd
- mm_port_name: REG_DP_BSN_MONITOR
mm_port_type: REG
+ mm_port_span: 16 * MM_BUS_SIZE
mm_port_description: ""
number_of_mm_ports: g_nof_streams
fields:
@@ -266,6 +276,7 @@ peripherals:
# MM port for dp_bsn_monitor_reg_v2.vhd
- mm_port_name: REG_DP_BSN_MONITOR_V2
mm_port_type: REG
+ mm_port_span: 8 * MM_BUS_SIZE
mm_port_description: ""
number_of_mm_ports: g_nof_streams
fields:
@@ -317,6 +328,7 @@ peripherals:
# MM port for dp_selector_arr.vhd
- mm_port_name: REG_DP_SELECTOR
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: input_select
@@ -326,3 +338,19 @@ peripherals:
address_offset: 0x0
mm_width: 1
access_mode: RW
+
+
+ - peripheral_name: dp_sync_insert_v2 # pi_dp_sync_insert_v2.py
+ peripheral_description: "Every nof_blk_per_sync block a sync pulse is created at the output."
+ mm_ports:
+ # MM port for dp_sync_insert_v2.vhd
+ - mm_port_name: REG_DP_SYNC_INSERT_V2
+ mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
+ mm_port_description: ""
+ fields:
+ - - field_name: nof_blk_per_sync
+ field_description: |
+ "The block counter resets if a sync arrives at the input or when nof_blk_per_sync is reached."
+ address_offset: 0x0
+ access_mode: RW
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 9bceeae7d50a99e04c724a62f37821888af5a23f..39ca669c8f184bc1e880bf341840641e720fd402 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -43,8 +43,10 @@ synth_files =
src/vhdl/dp_shiftreg.vhd
src/vhdl/dp_fifo_info.vhd
src/vhdl/dp_fifo_core.vhd
+ src/vhdl/dp_fifo_core_arr.vhd
src/vhdl/dp_fifo_sc.vhd
src/vhdl/dp_fifo_dc.vhd
+ src/vhdl/dp_fifo_dc_arr.vhd
src/vhdl/dp_fifo_dc_mixed_widths.vhd
src/vhdl/dp_fifo_fill_core.vhd
src/vhdl/dp_fifo_fill_sc.vhd
@@ -134,6 +136,7 @@ synth_files =
src/vhdl/dp_offload_tx_len_calc.vhd
src/vhdl/dp_sync_insert.vhd
src/vhdl/dp_sync_insert_v2.vhd
+ src/vhdl/dp_sync_recover.vhd
src/vhdl/dp_field_blk.vhd
src/vhdl/dp_concat_field_blk.vhd
@@ -218,6 +221,7 @@ test_bench_files =
tb/vhdl/tb_dp_fifo_fill_sc.vhd
tb/vhdl/tb_dp_fifo_info.vhd
tb/vhdl/tb_dp_fifo_dc.vhd
+ tb/vhdl/tb_dp_fifo_dc_arr.vhd
tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
tb/vhdl/tb_dp_fifo_sc.vhd
tb/vhdl/tb_dp_fifo_to_mm.vhd
@@ -255,6 +259,7 @@ test_bench_files =
tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
tb/vhdl/tb_dp_sync_insert.vhd
tb/vhdl/tb_dp_sync_insert_v2.vhd
+ tb/vhdl/tb_dp_sync_recover.vhd
tb/vhdl/tb_dp_folder.vhd
tb/vhdl/tb_dp_switch.vhd
tb/vhdl/tb_dp_counter_func.vhd
@@ -289,6 +294,7 @@ test_bench_files =
tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
tb/vhdl/tb_tb_dp_fifo_dc.vhd
+ tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
tb/vhdl/tb_tb_dp_frame_scheduler.vhd
tb/vhdl/tb_tb_dp_latency_fifo.vhd
@@ -307,6 +313,7 @@ test_bench_files =
tb/vhdl/tb_tb_dp_sync_checker.vhd
tb/vhdl/tb_tb_dp_sync_insert.vhd
tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+ tb/vhdl/tb_tb_dp_sync_recover.vhd
tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
@@ -369,6 +376,7 @@ regression_test_vhdl =
tb/vhdl/tb_mms_dp_sync_checker.vhd
tb/vhdl/tb_tb_dp_sync_insert.vhd
tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+ tb/vhdl/tb_tb_dp_sync_recover.vhd
tb/vhdl/tb_dp_counter_func.vhd
tb/vhdl/tb_tb_dp_counter.vhd
tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 7f2fd8aed81aba0ee3dd2924874cd8fb3afe0fc0..2520c398666f8fa545c8e61c4cb38b375f29aee6 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -68,7 +68,7 @@ BEGIN
address <= start_address + r.word_index + r.step_index;
mm_mosi.address <= TO_MEM_ADDRESS(address);
mm_mosi.wrdata <= RESIZE_MEM_DATA(in_sosi.data);
- mm_mosi.wr <= r.wr;
+ mm_mosi.wr <= d.wr;
p_reg : PROCESS(rst, clk)
BEGIN
@@ -104,4 +104,4 @@ BEGIN
END IF;
END PROCESS;
-END rtl;
\ No newline at end of file
+END rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index eb5600b1832a4b802f2271f09ce347e7b3efb083..94535504404868246c757a796885e8c6f53738db 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -82,7 +82,7 @@ ARCHITECTURE rtl OF dp_bsn_source_reg_v2 IS
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => 3,
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 3**2,
+ nof_dat => 2**3,
init_sl => '0');
-- Registers in mm_clk domain
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index f73edbf022860bb34582210adf067f6f0e8fab46..66598b4d337c739710274cbe38b8ebebb8d85bf6 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -58,6 +58,7 @@ ENTITY dp_bsn_source_v2 IS
dp_on_pps : IN STD_LOGIC;
dp_on_status : OUT STD_LOGIC;
+ bs_restart : OUT STD_LOGIC;
nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
@@ -102,6 +103,7 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
SIGNAL i_dp_on_status : STD_LOGIC;
SIGNAL nxt_dp_on_status : STD_LOGIC;
+ SIGNAL nxt_bs_restart : STD_LOGIC;
SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
@@ -132,6 +134,7 @@ BEGIN
nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
nxt_sync <= sync;
nxt_dp_on_status <= i_dp_on_status;
+ nxt_bs_restart <= '0';
nxt_bsn_time_offset_cnt <= bsn_time_offset_cnt;
nxt_current_bsn_time_offset <= bsn_time_offset;
@@ -187,6 +190,9 @@ BEGIN
nxt_src_out.sync <= '1';
nxt_sync <= '0';
END IF;
+ IF i_dp_on_status = '0' THEN -- transition from 0 to 1 is a (re)start
+ nxt_bs_restart <= '1'; -- bs_restart indicates a restart as a pulse on the sop (and sync if dp_on_pps is used).
+ END IF;
WHEN s_dp_on =>
nxt_src_out.valid <= '1';
@@ -221,6 +227,7 @@ BEGIN
sync <= '0';
block_size_cnt <= (OTHERS=>'0');
i_dp_on_status <= '0';
+ bs_restart <= '0';
bsn_time_offset_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
prev_state <= state;
@@ -230,6 +237,7 @@ BEGIN
sync <= nxt_sync;
block_size_cnt <= nxt_block_size_cnt;
i_dp_on_status <= nxt_dp_on_status;
+ bs_restart <= nxt_bs_restart;
bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
i_current_bsn_time_offset <= nxt_current_bsn_time_offset;
END IF;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..83964e22b64cf0a3cdc95ad955082f8752e7d713
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -0,0 +1,308 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose:
+-- Provide input ready control and use output ready control to the FIFO.
+-- Pass sop and eop along with the data through the FIFO if g_use_ctrl=TRUE.
+-- Default the RL=1, use g_fifo_rl=0 for a the show ahead FIFO.
+-- Description:
+-- Similar to dp_fifo_core but for multiple synchronous inputs. All data fields
+-- of the in sosi's are concatenated in addition to the the control signals of
+-- in_sosi_arr(0) and in_aux. So the control signals of in_sosi_arr(1 TO g_nof_streams-1)
+-- are not used. It is useful to have dp_fifo_core_arr to ensure that all inputs
+-- are crossed over to the rd_clk domain on the same clock cycle, this cannot
+-- be guaranteed when using multiple dp_fifo_core instances. For single clock,
+-- dp_fifo_core_arr is also useful as it saves logic on the control signals since
+-- it only uses the control signals of in_sosi_arr(0).
+-- Remark:
+-- . dp_fifo_core_arr is not built on top of dp_fifo_core as the input of dp_fifo_core
+-- is of type t_dp_sosi which has a limited size and could cause issues when concatenating
+-- multiple input streams.
+-- . It is assumed all inputs are synchronous (identical control signals).
+-- If the inputs are asynchronous, better use multiple instances of
+-- dp_fifo_core.
+-- . It is possible to add additonal signals to the fifo using in_aux/out_aux.
+
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY dp_fifo_core_arr IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_streams : NATURAL := 1;
+ g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_dual_clock : BOOLEAN := FALSE;
+ g_use_lut_sc : BOOLEAN := FALSE; -- when TRUE then force using LUTs instead of block RAM for single clock FIFO (bot available for dual clock FIFO)
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_signed : BOOLEAN := FALSE; -- TRUE extends g_data_w bits with the sign bit, FALSE pads g_data_w bits with zeros.
+ g_bsn_w : NATURAL := 1;
+ g_empty_w : NATURAL := 1;
+ g_channel_w : NATURAL := 1;
+ g_error_w : NATURAL := 1;
+ g_aux_w : NATURAL := 1;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_empty : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_error : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_use_aux : BOOLEAN := FALSE; -- extra signal in_aux/out_aux
+ g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
+ g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl : NATURAL := 1
+ );
+ PORT (
+ wr_rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ -- Monitor FIFO filling
+ wr_ful : OUT STD_LOGIC; -- corresponds to the carry bit of wr_usedw when FIFO is full
+ wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_emp : OUT STD_LOGIC;
+ -- ST sink
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ in_aux : IN STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0) := (OTHERS => '0');
+ -- ST source
+ src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_aux : OUT STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0)
+ );
+END dp_fifo_core_arr;
+
+
+ARCHITECTURE str OF dp_fifo_core_arr IS
+
+ CONSTANT c_use_data : BOOLEAN := TRUE;
+ CONSTANT c_total_data_w : NATURAL := g_nof_streams * g_data_w;
+ CONSTANT c_ctrl_w : NATURAL := 2; -- sop and eop
+
+ CONSTANT c_complex_w : NATURAL := smallest(c_dp_stream_dsp_data_w, g_data_w/2); -- needed to cope with g_data_w > 2*c_dp_stream_dsp_data_w
+
+ CONSTANT c_fifo_almost_full : NATURAL := g_fifo_size-g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
+ CONSTANT c_fifo_dat_w : NATURAL := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
+
+ SIGNAL nxt_snk_out : t_dp_siso := c_dp_siso_rst;
+
+ SIGNAL arst : STD_LOGIC;
+
+ TYPE t_wr_data_complex_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(2*c_complex_w-1 DOWNTO 0);
+ TYPE t_rd_data_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+
+ SIGNAL wr_data_complex_arr : t_wr_data_complex_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL wr_data : STD_LOGIC_VECTOR(c_total_data_w-1 DOWNTO 0);
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_total_data_w-1 DOWNTO 0);
+ SIGNAL rd_data_arr : t_rd_data_arr(g_nof_streams-1 DOWNTO 0);
+
+ SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
+ SIGNAL fifo_wr_req : STD_LOGIC;
+ SIGNAL fifo_wr_ful : STD_LOGIC;
+ SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
+
+ SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL fifo_rd_val : STD_LOGIC;
+ SIGNAL fifo_rd_req : STD_LOGIC;
+ SIGNAL fifo_rd_emp : STD_LOGIC;
+ SIGNAL fifo_rd_usedw : STD_LOGIC_VECTOR(rd_usedw'RANGE);
+
+ SIGNAL wr_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL rd_sync : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL wr_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL rd_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL wr_aux : STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0);
+
+ SIGNAL rd_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rd_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- initialize default values for unused sosi fields
+
+ SIGNAL in_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ -- Output monitor FIFO filling
+ wr_ful <= fifo_wr_ful;
+ wr_usedw <= fifo_wr_usedw;
+ rd_usedw <= fifo_rd_usedw;
+ rd_emp <= fifo_rd_emp;
+
+ p_wr_clk: PROCESS(wr_clk, wr_rst)
+ BEGIN
+ IF wr_rst='1' THEN
+ snk_out_arr <= (OTHERS => c_dp_siso_rst);
+ ELSIF rising_edge(wr_clk) THEN
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ snk_out_arr(I) <= nxt_snk_out;
+ END LOOP;
+ END IF;
+ END PROCESS;
+
+ wr_sync(0) <= snk_in_arr(0).sync;
+ wr_ctrl <= snk_in_arr(0).sop & snk_in_arr(0).eop;
+ wr_aux <= in_aux;
+
+ -- Assign the snk_in_arr data field or concatenated complex fields to the FIFO wr_data depending on g_use_complex
+ gen_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ wr_data_complex_arr(I) <= snk_in_arr(I).im(c_complex_w-1 DOWNTO 0) & snk_in_arr(I).re(c_complex_w-1 DOWNTO 0);
+ wr_data((I+1) * g_data_w -1 DOWNTO I * g_data_w) <= snk_in_arr(I).data(g_data_w-1 DOWNTO 0) WHEN g_use_complex = FALSE ELSE RESIZE_UVEC(wr_data_complex_arr(I), g_data_w);
+ END GENERATE;
+ -- fifo wr wires
+ fifo_wr_req <= snk_in_arr(0).valid;
+ fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ wr_data,
+ snk_in_arr(0).bsn( g_bsn_w-1 DOWNTO 0),
+ snk_in_arr(0).empty( g_empty_w-1 DOWNTO 0),
+ snk_in_arr(0).channel(g_channel_w-1 DOWNTO 0),
+ snk_in_arr(0).err( g_error_w-1 DOWNTO 0),
+ wr_sync,
+ wr_ctrl,
+ wr_aux);
+
+ -- pass on frame level flow control
+ nxt_snk_out.xon <= src_in_arr(0).xon;
+
+ -- up stream use fifo almost full to control snk_out.ready
+ nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
+
+ gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
+ u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
+ );
+
+ fifo_wr_usedw <= fifo_rd_usedw;
+ END GENERATE;
+
+ gen_common_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
+ u_common_fifo_dc : ENTITY common_lib.common_fifo_dc
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ PORT MAP (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => fifo_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rdusedw => fifo_rd_usedw,
+ rd_val => fifo_rd_val
+ );
+
+ arst <= wr_rst OR rd_rst;
+ END GENERATE;
+
+ -- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
+ rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w,
+ fifo_rd_dat, 0);
+
+ -- fifo rd wires
+ -- SISO
+ fifo_rd_req <= rd_siso_arr(0).ready;
+ rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 5);
+ rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 6);
+
+ -- AUX
+ in_aux_sosi.data <= RESIZE_DP_DATA(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 7));
+ in_aux_sosi.valid <= fifo_rd_val;
+ out_aux <= out_aux_sosi.data(g_aux_w-1 DOWNTO 0);
+
+ -- SOSI
+ gen_rd_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ rd_data_arr(I) <= rd_data( (I+1) * g_data_w -1 DOWNTO I * g_data_w);
+ rd_sosi_arr(I).data <= RESIZE_DP_SDATA(rd_data_arr(I)) WHEN g_data_signed=TRUE ELSE RESIZE_DP_DATA(rd_data_arr(I));
+ rd_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(rd_data_arr(I)( c_complex_w-1 DOWNTO 0));
+ rd_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(rd_data_arr(I)(2*c_complex_w-1 DOWNTO c_complex_w));
+ rd_sosi_arr(I).bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 1));
+ rd_sosi_arr(I).empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 2));
+ rd_sosi_arr(I).channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 3));
+ rd_sosi_arr(I).err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 4));
+ rd_sosi_arr(I).sync <= fifo_rd_val AND rd_sync(0);
+ rd_sosi_arr(I).valid <= fifo_rd_val;
+ rd_sosi_arr(I).sop <= fifo_rd_val AND rd_ctrl(1);
+ rd_sosi_arr(I).eop <= fifo_rd_val AND rd_ctrl(0);
+
+ u_ready_latency : ENTITY work.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso_arr(I),
+ snk_in => rd_sosi_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
+ END GENERATE;
+
+ -- Using extra dp_latency_adapter for aux signal
+ u_ready_latency_aux : ENTITY work.dp_latency_adapter
+ GENERIC MAP (
+ g_in_latency => 1,
+ g_out_latency => g_fifo_rl
+ )
+ PORT MAP (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_in => in_aux_sosi,
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => out_aux_sosi
+ );
+
+END str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e788c2b57913f8cef7638e3288e83aa7ef55da3c
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: DP FIFO array for dual clock (= dc) domain wr and rd.
+-- Description: See dp_fifo_core_arr.vhd.
+
+LIBRARY IEEE,common_lib, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY dp_fifo_dc_arr IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_streams : NATURAL := 1;
+ g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_bsn_w : NATURAL := 1;
+ g_empty_w : NATURAL := 1;
+ g_channel_w : NATURAL := 1;
+ g_error_w : NATURAL := 1;
+ g_aux_w : NATURAL := 1;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_empty : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_error : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_use_aux : BOOLEAN := FALSE;
+ g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
+ g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
+ g_fifo_rl : NATURAL := 1
+ );
+ PORT (
+ wr_rst : IN STD_LOGIC;
+ wr_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+ rd_clk : IN STD_LOGIC;
+ -- Monitor FIFO filling
+ wr_ful : OUT STD_LOGIC;
+ wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
+ rd_emp : OUT STD_LOGIC;
+ -- ST sink
+ snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ in_aux : IN STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0);
+ -- ST source
+ src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_aux : OUT STD_LOGIC_VECTOR(g_aux_w-1 DOWNTO 0)
+ );
+END dp_fifo_dc_arr;
+
+
+ARCHITECTURE str OF dp_fifo_dc_arr IS
+BEGIN
+
+ u_dp_fifo_core_arr : ENTITY work.dp_fifo_core_arr
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_use_dual_clock => TRUE,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_aux_w => g_aux_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_aux => g_use_aux,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ PORT MAP (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ in_aux => in_aux,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ out_aux => out_aux
+ );
+
+END str;
diff --git a/libraries/base/dp/src/vhdl/dp_selector.vhd b/libraries/base/dp/src/vhdl/dp_selector.vhd
index f3eb8790bb103007e06e439bc044b668aaebe37e..682bbb15d1afe3dd8035d1c1bcb7abcf6a297455 100644
--- a/libraries/base/dp/src/vhdl/dp_selector.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector.vhd
@@ -52,7 +52,9 @@ ENTITY dp_selector IS
pipe_sosi : IN t_dp_sosi;
ref_sosi : IN t_dp_sosi;
- out_sosi : OUT t_dp_sosi
+ out_sosi : OUT t_dp_sosi;
+
+ selector_en : OUT STD_LOGIC
);
END dp_selector;
@@ -76,7 +78,9 @@ BEGIN
pipe_sosi_arr(0) => pipe_sosi,
ref_sosi_arr(0) => ref_sosi,
- out_sosi_arr(0) => out_sosi
+ out_sosi_arr(0) => out_sosi,
+
+ selector_en => selector_en
);
END str;
diff --git a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
index 5b5f2c8d6c5a5f9eaffb6a545f281e3d6760d036..38c352179337af02be8c7791da4914c78f35f814 100644
--- a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
@@ -56,7 +56,9 @@ ENTITY dp_selector_arr IS
pipe_sosi_arr : IN t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0);
ref_sosi_arr : IN t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0);
- out_sosi_arr : OUT t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0)
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0);
+
+ selector_en : OUT STD_LOGIC
);
END dp_selector_arr;
@@ -72,6 +74,8 @@ ARCHITECTURE str OF dp_selector_arr IS
BEGIN
+ selector_en <= reg_selector_en(0);
+
u_mms_common_reg : ENTITY common_lib.mms_common_reg
GENERIC MAP (
g_mm_reg => c_selector_mem_reg
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f4ff1b9746c7856b039b387c034a1403e8ff3a80
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -0,0 +1,150 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose : Recover DP control signals (sync, valid, sop, eop, bsn) from input of a processing component and the out valid of that component.
+-- Description: dp_sync_recover generates the control signals based on in_sosi.sync, in_sosi.bsn and recover_val.
+-- dp_sync_recover is used in combination with a processing component that doesn't keep the control signals. By connecting the input of the
+-- processing component to in_sosi and the valid of the output of the processing component to recover_val, dp_sync_recover will generate the
+-- missing control signals at out_sosi.
+-- . A data counter is used to count the valids from the input "recover_val" and compare to g_nof_data_per_block to generate sop/eop.
+-- . A block counter is used generate the BSN
+-- . The BSN at sync of in_sosi is captured to determine when to generate the sync at the output.
+-- . IN recover_val is used to indicate when to start outputting the control signals. recover_val is also used for out_sosi.valid, these are connected as wires, so no latency.
+-- . IN restart is used to restart the counters. On the restart pulse the in_sosi.bsn is used as the initial value for the bsn counter.
+-- Remarks:
+-- . The recover_val input signal should be connected to the valid of the output of the related processing component. It determines when
+-- the first block will start after a (re)start.
+-- . It is assumed that the restart pulse is synchronous with in_sosi.sop (if it would have a sop)
+-- . IN recover_val should have at least a latency of 1 compared to in_sosi.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_sync_recover IS
+ GENERIC (
+ g_nof_data_per_block : POSITIVE := 1
+ );
+ PORT (
+
+ -- Clocks and reset
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ in_sosi : IN t_dp_sosi := c_dp_sosi_rst;
+ recover_val : IN STD_LOGIC; -- valid of the out_sosi that needs to be recoverd.
+ restart : IN STD_LOGIC := '0'; -- pulse to restart bsn counter
+
+ out_sosi : OUT t_dp_sosi
+ );
+END dp_sync_recover;
+
+
+ARCHITECTURE rtl OF dp_sync_recover IS
+
+ TYPE t_reg IS RECORD -- local registers
+ bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store at which to generate a sync pulse.
+ bsn_before_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store at which to restart te bsn counter.
+ bsn_at_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store inital bsn after (re)start.
+ restart : STD_LOGIC;
+ started : STD_LOGIC;
+ data_cnt : NATURAL RANGE 0 TO g_nof_data_per_block;
+ out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
+ out_sosi : t_dp_sosi;
+ END RECORD;
+
+ CONSTANT c_reg_rst : t_reg := ( (OTHERS => '0'), (OTHERS => '0'), (OTHERS => '0'), '0', '0', 0, (OTHERS => '0'), c_dp_sosi_rst);
+
+ -- Define the local registers in t_reg record
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
+
+BEGIN
+
+ out_sosi <= nxt_r.out_sosi;
+
+ p_clk : PROCESS(dp_rst, dp_clk)
+ BEGIN
+ IF dp_rst='1' THEN
+ r <= c_reg_rst;
+ ELSIF rising_edge(dp_clk) THEN
+ r <= nxt_r;
+ END IF;
+ END PROCESS;
+
+ p_comb : PROCESS(r, in_sosi, recover_val)
+ VARIABLE v : t_reg;
+ BEGIN
+ v := r;
+ v.out_sosi := c_dp_sosi_rst;
+ v.out_sosi.valid := recover_val;
+ v.out_sosi.bsn := r.out_sosi.bsn;
+
+ IF r.restart = '0' AND restart = '0' THEN -- keep track of last bsn before restart
+ v.bsn_before_restart := in_sosi.bsn;
+ END IF;
+
+ IF in_sosi.sync = '1' THEN -- capture bsn at sync
+ v.bsn_at_sync := in_sosi.bsn;
+ END IF;
+
+ IF recover_val = '1' THEN
+ v.data_cnt := r.data_cnt + 1;
+ IF r.data_cnt = 0 THEN -- generate sop + bsn
+ v.out_sosi.sop := '1';
+ v.out_bsn := STD_LOGIC_VECTOR(UNSIGNED(r.out_bsn) + 1); -- increase block counter
+ v.out_sosi.bsn := r.out_bsn;
+ IF r.out_bsn = r.bsn_at_sync THEN -- generate sync pulse
+ v.out_sosi.sync := '1';
+ END IF;
+ END IF;
+ IF r.data_cnt = g_nof_data_per_block-1 THEN --reset data counter and generate eop.
+ v.data_cnt := 0;
+ v.out_sosi.eop := '1';
+ END IF;
+ END IF;
+
+ -- overwrite v.out_bsn if a restart has occurd.
+ IF restart = '1' THEN -- Capture BSN at restart
+ v.bsn_at_restart := in_sosi.bsn; -- initial bsn value
+ v.restart := '1';
+ IF r.started = '0' OR r.out_sosi.bsn = r.bsn_before_restart THEN -- if restarted for the first time or if the restart should happen at the current bsn use the in_sosi.bsn immidiatly.
+ v.started := '1';
+ v.restart := '0';
+ v.out_bsn := in_sosi.bsn;
+ END IF;
+ END IF;
+
+ -- If the latency is larger than one block, it is needed wait with the restart until the last block has arrived.
+ IF r.restart = '1' AND r.out_sosi.bsn = r.bsn_before_restart THEN -- set bsn to initial value after restart
+ v.out_bsn := r.bsn_at_restart;
+ v.restart := '0';
+ END IF;
+
+ nxt_r <= v;
+ END PROCESS;
+
+END rtl;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 9d096d2a96a0c3943ce7a037d5565206d7e823bf..bc82cda1f4970574aa8da25eee1ecfd57bec1d35 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -50,7 +50,9 @@ ENTITY mms_dp_bsn_source_v2 IS
reg_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
-- Streaming clock domain
- bs_sosi : OUT t_dp_sosi
+ bs_sosi : OUT t_dp_sosi;
+
+ bs_restart : OUT STD_LOGIC -- pulse to indicate if the bsn_source has restarted
);
END mms_dp_bsn_source_v2;
@@ -115,6 +117,7 @@ BEGIN
dp_on => dp_on,
dp_on_pps => dp_on_pps,
dp_on_status => dp_on_status,
+ bs_restart => bs_restart,
bsn_init => bsn_init,
nof_clk_per_sync => nof_clk_per_sync,
bsn_time_offset => bsn_time_offset,
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index 6e001091967a2795a22b90992d61109e0418a1af..b924263f39b412d409da0a0dadcbec09d2ee2926 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -248,6 +248,7 @@ BEGIN
out_sosi_arr(I).sop <= in_sosi_arr_pipe_ctrl(I).sop;
out_sosi_arr(I).eop <= in_sosi_arr_pipe_ctrl(I).eop;
out_sosi_arr(I).sync <= in_sosi_arr_pipe_ctrl(I).sync;
+ out_sosi_arr(I).bsn <= in_sosi_arr_pipe_ctrl(I).bsn;
END PROCESS;
END GENERATE gen_real_multiply;
@@ -301,6 +302,7 @@ BEGIN
out_sosi_arr(I).sop <= in_sosi_arr_pipe_ctrl(I).sop;
out_sosi_arr(I).eop <= in_sosi_arr_pipe_ctrl(I).eop;
out_sosi_arr(I).sync <= in_sosi_arr_pipe_ctrl(I).sync;
+ out_sosi_arr(I).bsn <= in_sosi_arr_pipe_ctrl(I).bsn;
END PROCESS;
END GENERATE gen_complex_multiply;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index 10eba26202abd8eafd39ac04b3387b9c67b77117..7898f94d3415f65df10ac943340699cb361cff52 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -59,11 +59,13 @@ END tb_dp_block_from_mm;
ARCHITECTURE tb OF tb_dp_block_from_mm IS
CONSTANT c_nof_blocks : NATURAL := g_step_size / g_data_size;
- CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks + g_data_size; -- Size is g_data_size addresses more than needed, to check for oversized blocks.
+ CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks;
CONSTANT c_ram_adr_w : NATURAL := ceil_log2(c_ram_data_size);
CONSTANT c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
+ CONSTANT c_init : NATURAL := 42; -- inital data counter value, should be > 0 for better test coverage.
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '1';
@@ -117,8 +119,8 @@ BEGIN
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
FOR i IN 0 TO c_ram_data_size - 1 LOOP
- ram_wr_adr <= TO_UVEC(i, c_ram.adr_w);
- ram_wr_dat <= TO_UVEC(i, c_ram.dat_w);
+ ram_wr_adr <= TO_UVEC( i, c_ram.adr_w);
+ ram_wr_dat <= TO_UVEC(c_init + i, c_ram.dat_w);
ram_wr_en <= '1';
proc_common_wait_some_cycles(clk, 1);
END LOOP;
@@ -154,7 +156,7 @@ BEGIN
WHILE tb_end = '0' LOOP
WAIT UNTIL rising_edge(clk);
IF block_done = '1' THEN
- ASSERT stop_address = TO_UINT(wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0)) REPORT "wrong data at mm_done signal, must be same as stop_address" SEVERITY ERROR;
+ ASSERT stop_address = TO_UINT(wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0)) - c_init REPORT "wrong data at mm_done signal, must be same as stop_address + c_init" SEVERITY ERROR;
END IF;
END LOOP;
WAIT;
@@ -179,22 +181,20 @@ BEGIN
ram_prev_rd_val <= ram_rd_val WHEN rising_edge(clk);
+ rd_data <= TO_UINT(ram_rd_dat);
p_verify_read_ram_data: PROCESS
BEGIN
- rd_nxt_data <= 1;
+ rd_nxt_data <= c_init;
proc_common_wait_until_high(clk, transfer_done);
WHILE tb_end = '0' LOOP
WAIT UNTIL rising_edge(clk);
- rd_data <= TO_UINT(ram_rd_dat);
- IF rd_data > 0 THEN
- IF ram_rd_val = '1' THEN
- ASSERT rd_data = rd_nxt_data REPORT "wrong order of RAM values" SEVERITY ERROR;
- ASSERT rd_data <= stop_address REPORT "wrong RAM values, greater then block size" SEVERITY ERROR;
- rd_nxt_data <= rd_nxt_data + 1;
- END IF;
- IF ram_rd_val = '0' AND ram_prev_rd_val = '1' THEN -- If ram_rd_val goes from hi tot lo.
- ASSERT rd_data = stop_address REPORT "wrong last RAM values, not same as block size" SEVERITY ERROR;
- END IF;
+ IF ram_rd_val = '1' THEN
+ ASSERT rd_data = rd_nxt_data REPORT "wrong order of RAM values" SEVERITY ERROR;
+ ASSERT rd_data - c_init <= stop_address REPORT "wrong RAM values, greater than block size" SEVERITY ERROR;
+ rd_nxt_data <= rd_nxt_data + 1;
+ END IF;
+ IF ram_rd_val = '0' AND ram_prev_rd_val = '1' THEN -- If ram_rd_val goes from hi tot lo.
+ ASSERT rd_data - c_init = stop_address REPORT "wrong last RAM values, not same as block size" SEVERITY ERROR;
END IF;
END LOOP;
WAIT;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..514ebe5def34235e3eab48d0502a83b7c860190d
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -0,0 +1,251 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Test dp_fifo_dc_arr.
+-- Description:
+-- Verifies output data and ctrl signals of DUT. This is configurable using generics.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+ENTITY tb_dp_fifo_dc_arr IS
+ GENERIC (
+ -- Try FIFO settings
+ g_dut_nof_streams : NATURAL := 3;
+ g_dut_wr_clk_freq : POSITIVE := 2; -- normalized write clock frequency
+ g_dut_rd_clk_freq : POSITIVE := 3; -- normalized read clock frequency
+ g_dut_use_bsn : BOOLEAN := TRUE;
+ g_dut_use_empty : BOOLEAN := TRUE;
+ g_dut_use_channel : BOOLEAN := TRUE;
+ g_dut_use_sync : BOOLEAN := TRUE;
+ g_dut_use_ctrl : BOOLEAN := TRUE;
+ g_dut_use_aux : BOOLEAN := TRUE;
+ g_dut_out_latency : NATURAL := 1 -- selectable for dp_fifo_dc_arr: default 1 or 0 for look ahead FIFO
+ );
+END tb_dp_fifo_dc_arr;
+
+
+ARCHITECTURE tb OF tb_dp_fifo_dc_arr IS
+
+ -- See tb_dp_pkg.vhd for explanation and run time, increase the run time by g_dut_rd_clk_freq/g_dut_wr_clk_freq if g_dut_rd_clk_freq>g_dut_wr_clk_freq
+
+ -- DUT
+ CONSTANT c_dut_fifo_size : NATURAL := 64;
+ CONSTANT c_dut_in_latency : NATURAL := 1; -- fixed for dp_fifo_dc_arr
+
+ -- Stimuli
+ CONSTANT c_tx_latency : NATURAL := c_dut_in_latency; -- TX ready latency of TB
+ CONSTANT c_tx_void : NATURAL := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0
+ CONSTANT c_tx_offset_sop : NATURAL := 3;
+ CONSTANT c_tx_period_sop : NATURAL := 7; -- sop in data valid cycle 3, 10, 17, ...
+ CONSTANT c_tx_offset_eop : NATURAL := 5; -- eop in data valid cycle 5, 12, 19, ...
+ CONSTANT c_tx_period_eop : NATURAL := c_tx_period_sop;
+ CONSTANT c_tx_offset_sync : NATURAL := 3; -- sync in data valid cycle 3, 20, 37, ...
+ CONSTANT c_tx_period_sync : NATURAL := 17;
+ CONSTANT c_rx_latency : NATURAL := g_dut_out_latency; -- RX ready latency from DUT
+ CONSTANT c_verify_en_wait : NATURAL := 20; -- wait some cycles before asserting verify enable
+
+ CONSTANT c_bsn_offset : NATURAL := 1;
+ CONSTANT c_empty_offset : NATURAL := 2;
+ CONSTANT c_channel_offset : NATURAL := 3;
+
+ CONSTANT c_random_w : NATURAL := 19;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL wr_clk : STD_LOGIC := '0';
+ SIGNAL rd_clk : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL sync : STD_LOGIC;
+ SIGNAL lfsr1 : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL lfsr2 : STD_LOGIC_VECTOR(c_random_w DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL cnt_dat : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL cnt_val : STD_LOGIC;
+ SIGNAL cnt_en : STD_LOGIC;
+
+ SIGNAL tx_data : t_dp_data_arr(0 TO c_tx_latency + c_tx_void) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL tx_val : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void) := (OTHERS=>'0');
+
+ SIGNAL in_ready : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL in_sync : STD_LOGIC;
+ SIGNAL in_val : STD_LOGIC;
+ SIGNAL in_sop : STD_LOGIC;
+ SIGNAL in_eop : STD_LOGIC;
+ SIGNAL in_aux : STD_LOGIC;
+
+ SIGNAL in_siso_arr : t_dp_siso_arr(g_dut_nof_streams-1 DOWNTO 0);
+ SIGNAL in_sosi_arr : t_dp_sosi_arr(g_dut_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL out_siso_arr : t_dp_siso_arr(g_dut_nof_streams-1 DOWNTO 0);
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(g_dut_nof_streams-1 DOWNTO 0);
+
+ SIGNAL out_ready : STD_LOGIC;
+ SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency);
+ SIGNAL out_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0);
+ SIGNAL out_bsn : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_empty : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_channel : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL out_sync : STD_LOGIC;
+ SIGNAL out_val : STD_LOGIC;
+ SIGNAL out_sop : STD_LOGIC;
+ SIGNAL out_eop : STD_LOGIC;
+ SIGNAL out_aux : STD_LOGIC;
+ SIGNAL prev_out_data : STD_LOGIC_VECTOR(out_data'RANGE);
+
+ SIGNAL state : t_dp_state_enum;
+
+ SIGNAL verify_en : STD_LOGIC;
+ SIGNAL verify_done : STD_LOGIC;
+
+ SIGNAL exp_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := TO_UVEC(19000/g_dut_wr_clk_freq, c_dp_data_w);
+
+ SIGNAL usedw : STD_LOGIC_VECTOR(ceil_log2(c_dut_fifo_size)-1 DOWNTO 0);
+
+BEGIN
+
+ wr_clk <= NOT wr_clk OR tb_end AFTER g_dut_rd_clk_freq*clk_period/2;
+ rd_clk <= NOT rd_clk OR tb_end AFTER g_dut_wr_clk_freq*clk_period/2;
+ rst <= '1', '0' AFTER clk_period*7;
+
+ -- Sync interval
+ proc_dp_sync_interval(wr_clk, sync);
+
+ -- Input data
+ cnt_val <= in_ready AND cnt_en;
+
+ proc_dp_cnt_dat(rst, wr_clk, cnt_val, cnt_dat);
+ proc_dp_tx_data(c_tx_latency, rst, wr_clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val);
+ proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
+ proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop);
+ proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop);
+
+ in_bsn <= INCR_UVEC(in_data, c_bsn_offset);
+ in_empty <= INCR_UVEC(in_data, c_empty_offset);
+ in_channel <= INCR_UVEC(in_data, c_channel_offset);
+
+ -- Stimuli control
+ proc_dp_count_en(rst, wr_clk, sync, lfsr1, state, verify_done, tb_end, cnt_en);
+ proc_dp_out_ready(rst, wr_clk, sync, lfsr2, out_ready);
+
+ -- Output verify
+ proc_dp_verify_en(c_verify_en_wait, rst, rd_clk, sync, verify_en);
+ proc_dp_verify_data("out_sosi.data", c_rx_latency, rd_clk, verify_en, out_ready, out_val, out_data, prev_out_data);
+ proc_dp_verify_valid(c_rx_latency, rd_clk, verify_en, out_ready, prev_out_ready, out_val);
+
+ gen_verify_sync : IF g_dut_use_sync=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", rd_clk, verify_en, out_data, out_val, out_sync);
+ END GENERATE;
+
+ gen_verify_aux : IF g_dut_use_aux=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "aux", rd_clk, verify_en, out_data, out_val, out_aux);
+ END GENERATE;
+
+ gen_verify_ctrl : IF g_dut_use_ctrl=TRUE GENERATE
+ proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", rd_clk, verify_en, out_data, out_val, out_sop);
+ proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", rd_clk, verify_en, out_data, out_val, out_eop);
+ END GENERATE;
+
+ gen_verify_bsn : IF g_dut_use_bsn=TRUE GENERATE
+ proc_dp_verify_other_sosi("bsn", INCR_UVEC(out_data, c_bsn_offset), rd_clk, verify_en, out_bsn);
+ END GENERATE;
+
+ gen_verify_empty : IF g_dut_use_empty=TRUE GENERATE
+ proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data, c_empty_offset), rd_clk, verify_en, out_empty);
+ END GENERATE;
+
+ gen_verify_channel : IF g_dut_use_channel=TRUE GENERATE
+ proc_dp_verify_other_sosi("channel", INCR_UVEC(out_data, c_channel_offset), rd_clk, verify_en, out_channel);
+ END GENERATE;
+
+ -- Check that the test has ran at all
+ proc_dp_verify_value(e_at_least, rd_clk, verify_done, exp_data, out_data);
+
+ ------------------------------------------------------------------------------
+ -- DUT dp_fifo_dc_arr
+ ------------------------------------------------------------------------------
+
+ -- map sl, slv to record
+ in_ready <= in_siso_arr(0).ready; -- SISO
+ in_aux <= in_sync; -- use sync to test aux data
+ gen_streams : FOR I IN 0 TO g_dut_nof_streams -1 GENERATE
+ in_sosi_arr(I).data(c_dp_data_w-1 DOWNTO 0) <= in_data; -- SOSI
+ in_sosi_arr(I).bsn(c_dp_bsn_w-1 DOWNTO 0) <= in_bsn(c_dp_bsn_w-1 DOWNTO 0);
+ in_sosi_arr(I).empty <= in_empty(c_dp_empty_w-1 DOWNTO 0);
+ in_sosi_arr(I).channel <= in_channel(c_dp_channel_w-1 DOWNTO 0);
+ in_sosi_arr(I).sync <= in_sync;
+ in_sosi_arr(I).valid <= in_val;
+ in_sosi_arr(I).sop <= in_sop;
+ in_sosi_arr(I).eop <= in_eop;
+ out_siso_arr(I).ready <= out_ready; -- SISO
+ END GENERATE;
+ out_data <= out_sosi_arr(0).data(c_dp_data_w-1 DOWNTO 0); -- SOSI
+ out_bsn(c_dp_bsn_w-1 DOWNTO 0) <= out_sosi_arr(0).bsn(c_dp_bsn_w-1 DOWNTO 0);
+ out_empty(c_dp_empty_w-1 DOWNTO 0) <= out_sosi_arr(0).empty;
+ out_channel(c_dp_channel_w-1 DOWNTO 0) <= out_sosi_arr(0).channel;
+ out_sync <= out_sosi_arr(0).sync;
+ out_val <= out_sosi_arr(0).valid;
+ out_sop <= out_sosi_arr(0).sop;
+ out_eop <= out_sosi_arr(0).eop;
+
+ dut : ENTITY work.dp_fifo_dc_arr
+ GENERIC MAP (
+ g_nof_streams => g_dut_nof_streams,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_aux_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => FALSE,
+ g_use_sync => g_dut_use_sync,
+ g_use_aux => g_dut_use_aux,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ PORT MAP (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ in_aux(0) => in_aux,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi_arr,
+ out_aux(0) => out_aux
+ );
+
+END tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7650451cd09ac897b307e35667f2ad58aa3fed3b
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -0,0 +1,235 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify dp_sync_recover
+-- Description: The tb verifies:
+-- . data valid gaps between blocks
+-- . data valid gaps within blocks
+-- . output sop, eop, valid, bsn and sync
+-- . restarts of the dut using IN restart of the dut
+-- Usage:
+-- > as 8
+-- > run -all
+--
+-- * The tb is self stopping because tb_end will stop the simulation by
+-- stopping the clk and thus all toggling.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+
+
+ENTITY tb_dp_sync_recover IS
+ GENERIC (
+ g_nof_data_per_block : NATURAL := 16;
+ g_nof_blk_per_sync : NATURAL := 8;
+ g_gap_size_during_block : NATURAL := 0;
+ g_gap_size_between_block : NATURAL := 0;
+ g_init_bsn : NATURAL := 23;
+ g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
+ g_dut_latency : NATURAL := 25;
+ g_nof_repeat : NATURAL := 14
+ );
+END tb_dp_sync_recover;
+
+
+ARCHITECTURE tb OF tb_dp_sync_recover IS
+
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL dp_clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC := '1';
+
+ -- DUT
+ SIGNAL ref_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_sosi : t_dp_sosi;
+ SIGNAL restart : STD_LOGIC := '0';
+
+ -- Verification
+ SIGNAL dly_valid_arr : STD_LOGIC_VECTOR(0 TO g_dut_latency) := (OTHERS=>'0');
+ SIGNAL dly_ref_sosi_arr : t_dp_sosi_arr(0 TO g_dut_latency) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL exp_sync : STD_LOGIC := '0';
+ SIGNAL out_hold_sop : STD_LOGIC := '0';
+ SIGNAL exp_size : NATURAL := g_nof_data_per_block;
+ SIGNAL cnt_size : NATURAL;
+
+BEGIN
+
+ dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
+ rst <= '1', '0' AFTER c_dp_clk_period*7;
+
+ ------------------------------------------------------------------------------
+ -- STIMULI
+ ------------------------------------------------------------------------------
+
+ p_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ BEGIN
+ proc_common_wait_until_low(dp_clk, rst);
+ proc_common_wait_some_cycles(dp_clk, 5);
+
+ FOR I IN 0 TO g_nof_repeat-1 LOOP
+ -- Generate first block with sync
+ ref_sosi.sync <= '1';
+ ref_sosi.sop <= '1';
+ ref_sosi.valid <= '1';
+ v_bsn := g_init_bsn + I * g_nof_blk_per_sync;
+ IF v_bsn = g_bsn_at_restart OR I = 0 THEN
+ v_bsn := g_init_bsn;
+ restart <= '1';
+ ELSIF v_bsn > g_bsn_at_restart THEN
+ v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync - g_bsn_at_restart;
+ END IF;
+ ref_sosi.bsn <= TO_DP_BSN(v_bsn);
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.sync <= '0';
+ ref_sosi.sop <= '0';
+ restart <= '0';
+
+ -- Optionally apply valid='0' during block of data
+ ref_sosi.valid <= '0';
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_during_block);
+ ref_sosi.valid <= '1';
+
+ proc_common_wait_some_cycles(dp_clk, g_nof_data_per_block-2);
+ ref_sosi.eop <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.eop <= '0';
+ ref_sosi.valid <= '0';
+
+ -- Optionally apply valid='0' between block of data
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_between_block);
+
+ -- Generate next blocks after sync
+ FOR J IN 0 TO g_nof_blk_per_sync-2 LOOP
+ v_bsn := g_init_bsn + I * g_nof_blk_per_sync + J + 1;
+ ref_sosi.sop <= '1';
+ ref_sosi.valid <= '1';
+ IF v_bsn = g_bsn_at_restart THEN
+ v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync + J + 1 - g_bsn_at_restart;
+ restart <= '1';
+ ELSIF v_bsn > g_bsn_at_restart THEN
+ v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync + J + 1 - g_bsn_at_restart;
+ END IF;
+
+ ref_sosi.bsn <= TO_DP_BSN(v_bsn);
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.sync <= '0';
+ ref_sosi.sop <= '0';
+ restart <= '0';
+
+ -- Optionally apply valid='0' during block of data
+ ref_sosi.valid <= '0';
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_during_block);
+ ref_sosi.valid <= '1';
+
+ proc_common_wait_some_cycles(dp_clk, g_nof_data_per_block-2);
+ ref_sosi.eop <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.eop <= '0';
+ ref_sosi.valid <= '0';
+
+ -- Optionally apply valid='0' between block of data
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_between_block);
+ END LOOP;
+ END LOOP;
+
+ -- End of stimuli
+ proc_common_wait_some_cycles(dp_clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ ref_sosi.data <= INCR_UVEC(ref_sosi.data, 1) WHEN rising_edge(dp_clk);
+ ref_sosi.re <= INCR_UVEC(ref_sosi.re, 2) WHEN rising_edge(dp_clk);
+ ref_sosi.im <= INCR_UVEC(ref_sosi.im, 3) WHEN rising_edge(dp_clk);
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_dut: ENTITY work.dp_sync_recover
+ GENERIC MAP (
+ g_nof_data_per_block => g_nof_data_per_block
+ )
+ PORT MAP (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ -- Streaming sink
+ in_sosi => ref_sosi,
+ recover_val => dly_ref_sosi_arr(g_dut_latency).valid,
+ restart => restart,
+ -- Streaming source
+ out_sosi => out_sosi
+ );
+
+ ------------------------------------------------------------------------------
+ -- Verification
+ -- . use some DUT specific verification
+ -- . use some general Verification means from tb_dp_pkg.vhd, dp_stream_verify.vhd
+ ------------------------------------------------------------------------------
+ dly_ref_sosi_arr(0) <= ref_sosi;
+ dly_ref_sosi_arr(1 TO g_dut_latency) <= dly_ref_sosi_arr(0 TO g_dut_latency-1) WHEN rising_edge(dp_clk);
+
+ p_exp_sync : PROCESS(dp_clk)
+ VARIABLE blk_cnt : NATURAL := 0;
+ BEGIN
+ IF rising_edge(dp_clk) THEN
+ exp_sync <= '0';
+ IF dly_ref_sosi_arr(g_dut_latency-1).sop = '1' THEN
+ IF dly_ref_sosi_arr(g_dut_latency-1).sync = '1' OR blk_cnt >= g_nof_blk_per_sync-1 THEN
+ blk_cnt := 0;
+ exp_sync <= '1';
+ ELSE
+ blk_cnt := blk_cnt+1;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ p_verify_out_sosi : PROCESS(dp_clk)
+ BEGIN
+ IF rising_edge(dp_clk) THEN
+ ASSERT out_sosi.valid = dly_ref_sosi_arr(g_dut_latency).valid REPORT "Wrong out_sosi.valid" SEVERITY ERROR;
+ ASSERT out_sosi.sop = dly_ref_sosi_arr(g_dut_latency).sop REPORT "Wrong out_sosi.sop" SEVERITY ERROR;
+ ASSERT out_sosi.eop = dly_ref_sosi_arr(g_dut_latency).eop REPORT "Wrong out_sosi.eop" SEVERITY ERROR;
+ ASSERT out_sosi.bsn = dly_ref_sosi_arr(g_dut_latency).bsn REPORT "Wrong out_sosi.bsn" SEVERITY ERROR;
+ ASSERT out_sosi.sync = dly_ref_sosi_arr(g_dut_latency).sync REPORT "Wrong out_sosi.sync" SEVERITY ERROR;
+ END IF;
+ END PROCESS;
+
+ -- Verify output packet ctrl
+ proc_dp_verify_sop_and_eop(dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_hold_sop);
+ -- Verify output packet block size
+ proc_dp_verify_block_size(exp_size, dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, cnt_size);
+
+
+
+END tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a5a8429a8e0cefa5eae73755b8df3b083df2b55b
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Test multiple instances of tb_dp_fifo_dc_arr.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_tb_dp_fifo_dc_arr IS
+END tb_tb_dp_fifo_dc_arr;
+
+
+ARCHITECTURE tb OF tb_tb_dp_fifo_dc_arr IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+ -- > as 10
+ -- > run g_dut_rd_clk_freq * 330 us --> OK
+
+ -- Try FIFO settings : GENERIC MAP (g_dut_wr_clk_freq, g_dut_rd_clk_freq, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_use_ctrl, g_dut_out_latency)
+
+ u_use_all_rl_0 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_2_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_1_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 2, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_3_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 2, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+ u_use_all_rl_0_clk_2_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 3, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 0);
+
+ u_use_all : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (1, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_use_all_clk_3_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 1, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_use_all_clk_1_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 3, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+
+ u_use_ctrl_rl_0 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (1, 1, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl_rl_0_clk_1_3 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 3, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl_rl_0_clk_3_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 3, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 0);
+ u_use_ctrl : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+ u_use_ctrl_clk_1_2 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 2, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+ u_use_ctrl_clk_2_1 : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 2, 1, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE, 1);
+
+ u_no_bsn : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_no_empty : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, FALSE, TRUE, TRUE, TRUE, TRUE, 1);
+ u_no_channel : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, FALSE, TRUE, TRUE, TRUE, 1);
+ u_no_sync : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, FALSE, TRUE, TRUE, 1);
+ u_no_ctrl : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, FALSE, TRUE, 1);
+ u_no_aux : ENTITY work.tb_dp_fifo_dc_arr GENERIC MAP (3, 1, 1, TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, 1);
+
+END tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e91f0319413b94a924b926df1fcc815113dcb4a8
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
@@ -0,0 +1,57 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify multiple variations of tb_dp_sync_recover
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_dp_sync_recover IS
+END tb_tb_dp_sync_recover;
+
+ARCHITECTURE tb OF tb_tb_dp_sync_recover IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+-- g_nof_data_per_block : NATURAL := 16;
+-- g_nof_blk_per_sync : NATURAL := 8;
+-- g_gap_size_during_block : NATURAL := 0;
+-- g_gap_size_between_block : NATURAL := 0;
+-- g_init_bsn : NATURAL := 23;
+-- g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
+-- g_dut_latency : NATURAL := 25;
+-- g_nof_repeat : NATURAL := 14
+
+ u_no_gaps : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 0, 0, 3, 50, 10, 14);
+ u_gap : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 10, 14);
+ u_restart_at_sync : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 10, 14);
+ u_restart_at_sync_hi : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 100, 14);
+ u_restart_at_sync_lo : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 1, 14);
+ u_high_latency : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 100, 14);
+ u_low_latency : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 1, 14);
+
+END tb;
diff --git a/libraries/base/reorder/reorder.peripheral.yaml b/libraries/base/reorder/reorder.peripheral.yaml
index fa238d51081386f0d1330737dc6f921421944d0a..91a27205798b4d895550235c5a845f506b787a4c 100644
--- a/libraries/base/reorder/reorder.peripheral.yaml
+++ b/libraries/base/reorder/reorder.peripheral.yaml
@@ -23,6 +23,7 @@ peripherals:
# MM port for reorder_col_wide.vhd / reorder_col.vhd
- mm_port_name: RAM_SS_SS_WIDE
mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_nof_ch_sel) * MM_BUS_SIZE
mm_port_description: ""
number_of_mm_ports: g_wb_factor
fields:
diff --git a/libraries/dsp/filter/filter.peripheral.yaml b/libraries/dsp/filter/filter.peripheral.yaml
index 0e13878acb86d6fbb3315e8cc5692b88869b4225..bbdc0db669179fa058da97b01eb622d63fc3d927 100644
--- a/libraries/dsp/filter/filter.peripheral.yaml
+++ b/libraries/dsp/filter/filter.peripheral.yaml
@@ -34,6 +34,7 @@ peripherals:
# MM port for fil_ppf_wide.vhd / fil_ppf_single.vhd
- mm_port_name: RAM_FIL_COEFS
mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_fil_ppf.nof_bands / g_fil_ppf.wb_factor) * MM_BUS_SIZE
mm_port_description: |
"The FIR filter coefficients are stored in blocks of g_fil_ppf.nof_bands/g_fil_ppf.wb_factor
real coefficients:
diff --git a/libraries/dsp/st/doc/st_histogram_status.txt b/libraries/dsp/st/doc/st_histogram_status.txt
new file mode 100644
index 0000000000000000000000000000000000000000..f657cbdac864fb1e3fb1bbdac710093afe9ed959
--- /dev/null
+++ b/libraries/dsp/st/doc/st_histogram_status.txt
@@ -0,0 +1,102 @@
+Status of st_histogram on june 2021 after merge to master in GitLab.
+
+EK = Eric Kooistra
+DS = Daniel van der Schuur
+
+In summary the things to do still for st_histogram are (this can be done in new Jira story):
+
+- add top level functional description (see 2b, 3)
+- explain why common_paged_ram_r_w was not used (see 2a)
+- remove control via MM (see 3, 4, 5a)
+- verify using DC signal (see 5b)
+- verify that sum(bins) has expected constant value every sync interval (see 5c)
+
+Below, for reference, EK copied the left over comments and answers from the GitLab merge ( https://git.astron.nl/desp/hdl/-/merge_requests/101 ) of the st_histogram VHDL in L2SDP-151 into L2SDP-143 and then into the master.
+
+
+1) mms_st_histogram.vhd - no comments
+
+2) st_histogram.vhd
+
+a) EK comment
+
+Why common_ram_r_w was selected instead of common_ram_cr_cw ?
+
+Waarom gebruik je niet common_paged_ram_r_w.vhd voor de RAM ? Kun je dat in comment aangeven, of vermelden dat common_paged_ram_r_w ook gebruikt had kunnen worden.
+
+
+b) EK comment
+
+Waarom kan read en write tegelijk voorkomen? --> Wat beslist de bus arbiter dan? --> Wat is het gevolg dan voor de bin waardes ?
+
+Hoe ziet de st_histogram werking er in de tijd van een sync interval uit? Tellen de bins echt alle samples, of gaan er steed bijv K samples per sync interval verloren, dat is acceptabel mits K constant is en K << N = nof samples per sync.
+
+Eigenlijk ontbreekt nog de beschrijving op functioneel niveau, los van de implementatie details, bijvoorbeeld zaken als:
+
+* The number of bins in the histogram g_nof_bins is a power of 2 and g_nof_bins_w <= g_data_w, so each bin counts the occurance of a subrange with 2**(g_data_w - g_nof_bins_w) samples values.
+* The sample values in range g_data_w get mapped to g_nof_bins by counting how often the sample value(s) for that bin occur during a sync interval.
+* The sum of the histogram bin values in each sync interval is : sum(bins) = N - K (klopt dat)?
+
+
+
+3) st_histogram_reg.vhd
+
+==> EK comment
+
+Ik snap niet waarom ram_clear en ram_fill nodig zijn op het MM interface. Voor ADUH_MON mean, power en voor SST is dat ook niet nodig.
+
+Eigenlijk moet het zo zijn dat de user op elk moment st_histogram RAM uit mag lezen, zonder extra polling of controlling. Als de user toevallig leest terwijl de pages swap, dan zal een deel van de bins bij het ene sync interval horen en de rest van de bins uit het volgende sync interval komen, maar dat is niet erg, want waarschijnlijk veranderd de histogram toch niet veel van sync interval op sync interval. Daarbij komt dat de kans dat de user precies tijdens een sync het histogram leest klein is, want lezen duurt veel korter dan 1 sync interval.
+
+Kunnen we st_histogram_reg.vhd verwijderen van het MM interface en vervangen door een intern VHDL process dat op fixed momenten de write velden bedient ?
+
+In een los Python scriptje is st_histogram_reg nog wel te bedienen, maar in een compleet M&C systeem (driver) is het denk ik te ingewikkeld en te belastend.
+
+
+==> DS antwoord:
+
+De ram_clear control is per abuis achtergebleven; deze was al vervangen voor een automatisch VHDL proces. Ik heb dit gefixt in de code.
+
+De ram_fill control bedient in essentie een g_nof_instances (12 voor LOFAR) naar 1 DP->MM selector. Er is dus maar 1 MM RAM en de user kiest middels de ram_fill control van welke van de g_nof_instances (12 voor lofar) de inhoud in de MM RAM moet staan. Dit bespaart g_nof_instances-1 RAM blocks.
+
+Goed punt over de M&C belasting hierdoor. We zouden hier (automated VHDL proces ipv MM control) een JIRA ticket van kunnen maken.
+
+
+4) tb_mms_st_histogram.vhd
+
+==> EK comment:
+
+Only needs to verify that the MM interface is connected properly, so should be a minimal tb. The details of the st_histogram inner workings have already been verified by tb_st_histogram.
+
+==> DS antwoord:
+tb_st_histogram tests only a single instance. tb_mms_st_histogram tests mms_st_histogram which has multi-instance support and the ram_fill control discussed above. Depending on what we do with ram_fill topic, we might no longer need the tb_mms. Possible JIRA ticket
+
+
+5) tb_st_histogram.vhd
+
+a) EK comment:
+
+The tb does not use reg_mosi, is that not needed ? But why is reg_mosi port then on the st_histogram ?
+
+==> DS antwoord:
+
+st_histogram.vhd does not have a reg_mosi port. tb_st_histogram tests only a single instance. tb_mms_st_histogram tests mms_st_histogram which has multi-instance support and the ram_fill control discussed above. Depending on what we do with ram_fill topic, we might no longer need the tb_mms. Possible JIRA ticket
+
+
+b) EK comment:
+
+What kind of data is used, does proc_dp_gen_block_data increment it?
+
+Have you tested using DC data ? I think having multiple sample values in a row that are important to try too.
+
+==> DS antwoord:
+
+Good point, we're only using counter data at this point. st_histogram should work with DC data but this really needs to be added to the TB. Possible JIRA ticket
+
+
+c) EK comment:
+
+Can you also check in a process that sum(bins) has always the expected constant value ?
+
+==> DS antwoord: Collapse replies
+
+This would be a good addition to the TB. Possible (par of) JIRE ticket
diff --git a/libraries/dsp/st/hdllib.cfg b/libraries/dsp/st/hdllib.cfg
index 02987cf05a878d6d473ef63930b6d49de9696b75..a00e04d87086a3e0910487baf04a6c559e4391e5 100644
--- a/libraries/dsp/st/hdllib.cfg
+++ b/libraries/dsp/st/hdllib.cfg
@@ -18,7 +18,6 @@ synth_files =
src/vhdl/st_histogram.vhd
src/vhdl/st_histogram_reg.vhd
src/vhdl/mms_st_histogram.vhd
- src/vhdl/st_histogram_8_april.vhd
tb/vhdl/tb_st_pkg.vhd
@@ -31,7 +30,9 @@ test_bench_files =
tb/vhdl/tb_st_xst.vhd
tb/vhdl/tb_tb_st_xst.vhd
tb/vhdl/tb_st_histogram.vhd
+
tb/vhdl/tb_mms_st_histogram.vhd
+ tb/vhdl/tb_st_histogram.vhd
tb/vhdl/tb_tb_st_histogram.vhd
regression_test_vhdl =
@@ -39,6 +40,7 @@ regression_test_vhdl =
tb/vhdl/tb_tb_st_xsq.vhd
tb/vhdl/tb_tb_st_xst.vhd
#tb/vhdl/tb_st_calc.vhd -- tb is not self checking yet
+ tb/vhdl/tb_tb_st_histogram.vhd
[modelsim_project_file]
diff --git a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd
index 8472efc40742fd61e77675a888cf84c742b56def..a17010950a6dd5c84c5cbece7105364dd6d51c08 100644
--- a/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/mms_st_histogram.vhd
@@ -18,37 +18,25 @@
--
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
---
--- Author: J.W.E. Oudman
--- Purpose: Create a histogram from the input data and present it to the MM bus
--- Description:
--- mms_st_histogram couples the st_histogram component which works entirely
--- in the dp clock domain through st_histogram_reg that handles the cross
--- domain conversion to the MM bus.
---
---
--- --------------------------------------
--- | mms_st_histogram |
--- | |
--- | ---------------- | -------
--- snk_in -->|-->| st_histogram | | ^
--- | ---------------- | |
--- | | ^ |
--- | | | | dp clock domain
--- | ram_st_histogram_miso |
--- | | | |
--- | | ram_st_histogram_mosi | |
--- | v | | v
--- | -------------------- | -------
--- | | st_histogram_reg |-- ram_miso -->|--> mm clock domain
--- | | |<-- ram_mosi --|<--
--- | -------------------- | -------
--- | |
--- --------------------------------------
---
---
--------------------------------------------------------------------------------
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- . MMS-wrapper that adds registers and multi-instance support to st_histogram.
+-- Description:
+-- . st_histogram_reg implements the registers to control all g_nof_instances
+-- . This MMS wrapper contains logic to fill a local RAM with the contents of
+-- a selected st_histogram instance.
+-- Usage (see st_histogram_reg.vhd for the register map):
+-- . Reading RAM contents:
+-- 1) User writes instance to read (0..g_nof_instances-1) to ram_fill_inst
+-- register via reg_mosi
+-- 2) Users writes to bit 0 of fill_ram register via reg_mosi
+-- . ram_filling status will go high
+-- 3) User reads ram_filling status until it reads zero via reg_mosi
+-- 4) User reads freshly filled RAM contents via ram_mosi
+-- . Clearing the RAMs:
+-- . The inactive RAM is cleared automatically just before the next input sync.
+-- . ram_clearing status will go high during this time.
LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
@@ -59,67 +47,187 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_st_histogram IS
GENERIC (
- g_in_data_w : NATURAL := 14; -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768)
- g_nof_bins : NATURAL := 512; -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
- g_nof_data : NATURAL; --
- g_str : STRING := "freq.density" -- to select output to MM bus ("frequency" or "freq.density")
+ g_nof_instances : NATURAL;
+ g_data_w : NATURAL;
+ g_nof_bins : NATURAL;
+ g_nof_data_per_sync : NATURAL
);
PORT (
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
-
- -- Streaming
- snk_in : IN t_dp_sosi;
-
- -- Memory Mapped
- ram_mosi : IN t_mem_mosi;
- ram_miso : OUT t_mem_miso
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ snk_in_arr : IN t_dp_sosi_arr(g_nof_instances-1 DOWNTO 0);
+
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ reg_mosi : IN t_mem_mosi;
+ reg_miso : OUT t_mem_miso;
+
+ ram_mosi : IN t_mem_mosi;
+ ram_miso : OUT t_mem_miso
);
END mms_st_histogram;
ARCHITECTURE str OF mms_st_histogram IS
-
- SIGNAL ram_st_histogram_mosi : t_mem_mosi;
- SIGNAL ram_st_histogram_miso : t_mem_miso;
-
+
+ CONSTANT c_reg_adr_w : NATURAL := 1;
+ CONSTANT c_ram_adr_w : NATURAL := ceil_log2(g_nof_bins);
+ CONSTANT c_ram_dat_w : NATURAL := ceil_log2(g_nof_data_per_sync);
+
+ CONSTANT c_ram : t_c_mem := (latency => 1,
+ adr_w => c_ram_adr_w,
+ dat_w => c_ram_dat_w,
+ nof_dat => g_nof_bins,
+ init_sl => '0');
+
+ CONSTANT c_addr_high : NATURAL := g_nof_bins-1;
+
+ SIGNAL common_ram_cr_cw_wr_mosi : t_mem_mosi;
+ SIGNAL nxt_common_ram_cr_cw_wr_mosi : t_mem_mosi;
+
+ SIGNAL common_ram_cr_cw_rd_mosi : t_mem_mosi;
+ SIGNAL common_ram_cr_cw_rd_miso : t_mem_miso;
+
+ SIGNAL ram_mosi_arr : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
+ SIGNAL ram_miso_arr : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0);
+
+ SIGNAL ram_clearing_arr : STD_LOGIC_VECTOR(g_nof_instances-1 DOWNTO 0);
+
+ SIGNAL ram_fill_inst : STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
+ SIGNAL ram_fill_inst_int : NATURAL;
+
+ SIGNAL ram_fill : STD_LOGIC;
+ SIGNAL ram_filling : STD_LOGIC;
+ SIGNAL nxt_ram_filling : STD_LOGIC;
+ SIGNAL address : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
+ SIGNAL nxt_address : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
+
BEGIN
+
+ -------------------------------------------------------------------------------
+ -- st_histogram instances and their registers
+ -------------------------------------------------------------------------------
+ gen_st_histogram : FOR i IN 0 TO g_nof_instances-1 GENERATE
+ u_st_histogram : ENTITY work.st_histogram
+ GENERIC MAP(
+ g_data_w => g_data_w,
+ g_nof_bins => g_nof_bins,
+ g_nof_data_per_sync => g_nof_data_per_sync
+ )
+ PORT MAP (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ snk_in => snk_in_arr(i),
- u_st_histogram : ENTITY work.st_histogram
- GENERIC MAP(
- g_in_data_w => g_in_data_w,
- g_nof_bins => g_nof_bins,
- g_nof_data => g_nof_data,
- g_str => g_str
+ ram_clearing => ram_clearing_arr(i),
+
+ ram_mosi => ram_mosi_arr(i),
+ ram_miso => ram_miso_arr(i)
+ );
+ END GENERATE;
+
+ u_st_histogram_reg : ENTITY work.st_histogram_reg
+ GENERIC MAP (
+ g_nof_instances => g_nof_instances
)
PORT MAP (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ ram_clearing => ram_clearing_arr(0),
+ ram_filling => ram_filling,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ ram_fill_inst => ram_fill_inst,
+ ram_fill => ram_fill,
- snk_in => snk_in,
- sla_in_ram_mosi => ram_st_histogram_mosi,
- sla_out_ram_miso => ram_st_histogram_miso
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
);
-
- u_st_histogram_reg : ENTITY work.st_histogram_reg
--- GENERIC MAP(
--- g_in_data_w =>
--- g_nof_bins =>
--- g_nof_data =>
--- g_str =>
--- )
+
+
+ -------------------------------------------------------------------------------
+ -- Dual clock RAM: DP write side, MM read side
+ -------------------------------------------------------------------------------
+ u_common_ram_cr_cw : ENTITY common_lib.common_ram_cr_cw
+ GENERIC MAP (
+ g_technology => c_tech_select_default,
+ g_ram => c_ram,
+ g_init_file => "UNUSED"
+ )
PORT MAP (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- mas_out_ram_mosi => ram_st_histogram_mosi,
- mas_in_ram_miso => ram_st_histogram_miso,
-
- ram_mosi => ram_mosi,
- ram_miso => ram_miso
+ wr_clk => dp_clk,
+ wr_rst => dp_rst,
+ wr_clken => '1',
+ wr_en => common_ram_cr_cw_wr_mosi.wr,
+ wr_adr => common_ram_cr_cw_wr_mosi.address(c_ram_adr_w-1 DOWNTO 0),
+ wr_dat => common_ram_cr_cw_wr_mosi.wrdata(c_ram_dat_w-1 DOWNTO 0),
+ rd_clk => mm_clk,
+ rd_rst => mm_rst,
+ rd_clken => '1',
+ rd_en => common_ram_cr_cw_rd_mosi.rd,
+ rd_adr => common_ram_cr_cw_rd_mosi.address(c_ram_adr_w-1 DOWNTO 0),
+ rd_dat => common_ram_cr_cw_rd_miso.rddata(c_ram_dat_w-1 DOWNTO 0),
+ rd_val => common_ram_cr_cw_rd_miso.rdval
);
-
+
+ -- User side MM bus for histogram readout
+ common_ram_cr_cw_rd_mosi <= ram_mosi;
+ ram_miso <= common_ram_cr_cw_rd_miso;
+
+
+ -------------------------------------------------------------------------------
+ -- Logic to move st_histogram RAM contents into the dual clock RAM above
+ -------------------------------------------------------------------------------
+
+ -- Keep track of ram_filling status and address
+ nxt_ram_filling <= '0' WHEN TO_UINT(address)=c_addr_high ELSE '1' WHEN ram_fill='1' ELSE ram_filling;
+ nxt_address <= (OTHERS=>'0') WHEN ram_filling='0' ELSE INCR_UVEC(address, 1) WHEN ram_filling='1' ELSE address;
+
+ -- Help signal for bus selection
+ ram_fill_inst_int <= TO_UINT(ram_fill_inst);
+
+ -- Do read request on ram_mosi when ram_filling
+ p_mosi_arr: PROCESS (ram_filling, address, ram_fill_inst_int)
+ BEGIN
+ FOR i IN 0 TO g_nof_instances-1 LOOP
+ ram_mosi_arr(i) <= c_mem_mosi_rst;
+ IF i = ram_fill_inst_int THEN
+ ram_mosi_arr(i).rd <= ram_filling;
+ ram_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0) <= address;
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+ -- Forward the read histogram data from ram_miso into write mosi of dual clock RAM
+ p_rd_miso_to_wr_mosi : PROCESS(ram_miso_arr, ram_fill_inst_int, address)
+ BEGIN
+ nxt_common_ram_cr_cw_wr_mosi <= common_ram_cr_cw_wr_mosi;
+ FOR i IN 0 TO g_nof_instances-1 LOOP
+ IF i = ram_fill_inst_int THEN
+ nxt_common_ram_cr_cw_wr_mosi.wr <= ram_miso_arr(i).rdval;
+ nxt_common_ram_cr_cw_wr_mosi.wrdata(c_ram_dat_w-1 DOWNTO 0) <= ram_miso_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0);
+ nxt_common_ram_cr_cw_wr_mosi.address(c_ram_adr_w-1 DOWNTO 0) <= address;
+ END IF;
+ END LOOP;
+ END PROCESS;
+
+ -- Registers
+ p_clk : PROCESS(dp_clk, dp_rst) IS
+ BEGIN
+ IF dp_rst = '1' THEN
+ common_ram_cr_cw_wr_mosi <= c_mem_mosi_rst;
+ address <= (OTHERS=>'0');
+ ram_filling <= '0';
+ ELSIF RISING_EDGE(dp_clk) THEN
+ common_ram_cr_cw_wr_mosi <= nxt_common_ram_cr_cw_wr_mosi;
+ address <= nxt_address;
+ ram_filling <= nxt_ram_filling;
+ END IF;
+ END PROCESS;
+
END str;
diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index 13b57e0ee13a3d5d2d04a7702d4a33686c2f0c31..f99a130b80b589f0a82b7120404d6c8267d09205 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -1,4 +1,4 @@
--------------------------------------------------------------------------------
+------------------------------------------------------------------------------
--
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
@@ -18,68 +18,65 @@
--
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
---
--- Author: J.W.E. Oudman
--- Purpose: Create a histogram from the input data and present it to
--- st_histogram_reg
+-- Author:
+-- . Daniel van der Schuur
+-- . Jan Oudman
+-- Purpose:
+-- . Count incoming data values and keep the counts in RAM as a histogram
-- Description:
--- The histogram component separates it's input samples in counter bins based
--- on the value of the MSbits of the input. These bins are adresses on a RAM
--- block that is swapped with another RAM block at every sync pulse plus 3
--- cycles. While one RAM block is used to count the input samples, the other
--- is read by the MM bus through st_histogram_reg.
---
---
--- ram_pointer ram_pointer
--- | |
--- | /o--- RAM_0 ---o |
--- |/ |
--- / |
--- snk_in ----o/ | /o----- ram_miso (st_histogram_reg)
--- |/ _mosi
--- /
--- o--- RAM_1 ---o/
---
---
--- The input data is a dp stream which obviously uses a dp_clk. Because the
--- RAM is swapped after every sync both RAM blocks need to use the dp_clk.
--- If the MM bus needs to acces the data in a RAM block it has to acces it
--- through st_histogram_reg as the mm_clk can't be used.
---
--- The design is basically devided in the following blocks of code:
--- . Assign inputs of RAM
--- . Bin reader
--- . Bin Writer
--- . Bin Arbiter
--- . RAM selector & Dual swapped RAM instances
--- . Connect interface to DUAL swapped RAM, read out histogram statistics
---
+-- . See st_histogram.txt for the original design description.
+-- . The contents of the inactive RAM is cleared automatically just before the
+-- next sync interval. This way, no data is lost and all valid input data
+-- contributes to the histogram. The ram_clearing status output is high
+-- during this automated clearing.
+-- . All valid data of a DC input contributes to the histogram, no data is
+-- lost.
+-- . The block schematic below shows the data flow from snk_in to ram_mosi:
+-- . snk_in.data is interpreted as address (bin) to read from RAM by bin_reader.
+-- . a RAM pointer 0 or 1 is kept as MS part of the address.
+-- . snk_in.sync determines the RAM pointer 0 or 1.
+-- . The data read from that adress, the bin count, is incremented and written
+-- back by bin_writer.
+-- . bin_arbiter decides whether a read or write accessw takes precedence, in case
+-- of simultanious RAM access requests by both bin_reader and bin_writer.
+-- . Upon request (ram_miso), the bin counts (the histogram) are output on
+-- ram_mosi.
+-- bin_reader_miso bin_arbiter_rd_miso
+-- __________ | ___________ | ___________
+-- | | | | | | | |
+-- ---snk_in--->|bin_reader|<--+--| |<--+--| |
+-- |__________| | | | |
+-- | | | | |
+-- | | | | |
+-- bin_reader_to_writer_mosi |bin_arbiter| | RAM(1..0) |----ram_mosi--->
+-- | | | | |
+-- ____v_____ | | | |
+-- | | | | | |
+-- |bin_writer|---+->| |---+->| |
+-- |__________| | |___________| | |___________|
+-- | |
+-- bin_writer_mosi bin_arbiter_wr_mosi
+-- Usage:
+-- . The ram_mosi input applies to the RAM page that is inactive (not
+-- being written to from data path) *at that time*. The user should take care to
+-- time these controls such that the active RAM page does not swap before these
+-- operation (ram_mosi readout) has finished.
-- Remarks:
--- . Because the values of the generics g_nof_bins depends on g_in_data_w
--- (you should not have more bins than data values) an assert is made to
--- warn in the simulation when the maximum value of g_nof_bins is reached.
--- If exceeded the simulator will throw fatal error ("...Port length (#) does
--- not match actual length (#)...")
---
--- . when an adress is determined it takes 2 cycles to receive it's value and
--- another cycle before the calculated value can be written into that RAM
--- adress (1st cycle: address; 3rd cycle: data available; 5th cycle: write
--- data). There is also the limitation of not being able to read and write
--- on the same adress at the same time. These limitations cause the following
--- complications in the implementation:
--- . repeating samples of the same adress have to be counted first till
--- another adress appears before written (as you would miss the second and
--- further consecutive samples and have the read/write limitation)
--- . If adresses are toggling at every cycle (e.g. adress 0; 1; 0; 1) you
--- have to remember the data to be written and increment it as you have the
--- read/write limitation (missing samples) and writing takes priority
--- in this case
--- . When a sync signal appears the RAM has to be swapped 4 cycles later so
--- the first 3 cycles may/can not ask a read from the old RAM block (the
--- read_enable takes one cycle hence the difference of 3 against 4 cycles)
---
--------------------------------------------------------------------------------
+-- . The RAM block we use basically needs 3 ports:
+-- 1 - read port in dp_clk domain to read current bin value
+-- 2 - write port in dp_clk domain to write back incremented bin value
+-- 3 - read port in mm_clk domain to read the inactive page
+-- . common_ram_r_w
+-- . Why common_ram_r_w was selected: it uses a single clock
+-- . We need to read and write back bins in the dp_clk clock domain, so our RAM
+-- block needs to have 2 separate address inputs - but in the same clock domain.
+-- . The other, dual clock, RAM blocks (e.g. common_ram_cr_cw) are based on
+-- common_ram_crw_crw and use 2 address inputs (adr_a,adr_b), each in
+-- its own (clk_a,clk_b) clock domain, which is not what we need here.
+-- . Downside of common_ram_r_w: it uses a single clock
+-- . This st_histogram.vhd operates in dp_clk domain only, so we need to
+-- provide MM access to the user, in the mm_clk domain, elsewhere. This
+-- has been done in mms_st_histogram.vhd.
LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
@@ -90,704 +87,332 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY st_histogram IS
GENERIC (
- g_in_data_w : NATURAL := 14; -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768) <-- maybe just g_data_w ??
- g_nof_bins : NATURAL := 512; -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
- g_nof_data : NATURAL; --
- g_str : STRING := "freq.density"; -- to select output to MM bus ("frequency" or "freq.density")
- g_ram_miso_sim_mode : BOOLEAN := FALSE -- when TRUE the ram_miso bus will get a copy of the data written into the RAM.
- );
+ g_data_w : NATURAL := 8;
+ g_nof_bins : NATURAL := 256;
+ g_nof_data_per_sync : NATURAL := 1024
+ );
PORT (
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
- -- Streaming
- snk_in : IN t_dp_sosi;
-
- -- DP clocked memory bus
- sla_in_ram_mosi : IN t_mem_mosi; -- Beware, works in dp clock domain !
- sla_out_ram_miso : OUT t_mem_miso; -- '' !
--- ram_mosi : IN t_mem_mosi; -- Beware, works in dp clock domain !
--- ram_miso : OUT t_mem_miso -- '' !
- -- Debug bus
- dbg_ram_miso : OUT t_mem_miso
+ snk_in : IN t_dp_sosi; -- Active RAM page swaps on snk_in.sync
+
+ ram_clearing : OUT STD_LOGIC; -- Status output: high while RAM is being cleared
+
+ ram_mosi : IN t_mem_mosi; -- MM access to the inactive RAM page
+ ram_miso : OUT t_mem_miso
);
END st_histogram;
ARCHITECTURE rtl OF st_histogram IS
--- CONSTANT c_data_span : NATURAL := pow2(g_in_data_w); -- any use?
--- CONSTANT c_bin_w : NATURAL := ceil_log2(g_nof_data); -- any use?
- CONSTANT c_clear : NATURAL := g_nof_data - g_nof_bins;
- CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins);
- CONSTANT c_adr_low_calc : INTEGER := g_in_data_w-c_adr_w; -- Calculation might yield a negative number
- CONSTANT c_adr_low : NATURAL := largest(0, c_adr_low_calc); -- Override any negative value of c_adr_low_calc
- CONSTANT c_ram : t_c_mem := (latency => 1,
- adr_w => c_adr_w, -- 9 bits needed to adress/select 512 adresses
- dat_w => c_word_w, -- 32bit, def. in common_pkg; >= c_bin_w
- nof_dat => g_nof_bins, -- 512 adresses with 32 bit words, so 512
- init_sl => '0'); -- MM side : sla_in, sla_out
-
--- CONSTANT c_mem_miso_setting : t_mem_miso := (rddata => mem_miso_init, -- c_mem_miso_rst; -- limit to 32 bit
--- rdval => '0',
--- waitrequest => '0' );
-
--- SIGNAL mem_miso_init : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS => '0');
+ -------------------------------------------------------------------------------
+ -- Constants derived from generics
+ -------------------------------------------------------------------------------
+ CONSTANT c_ram_adr_w : NATURAL := ceil_log2(g_nof_bins);
+ CONSTANT c_adr_low : NATURAL := g_data_w-c_ram_adr_w;
+ CONSTANT c_ram_dat_w : NATURAL := ceil_log2(g_nof_data_per_sync)+1;
- SIGNAL snk_in_p : t_dp_sosi;
- SIGNAL snk_in_pp : t_dp_sosi;
- SIGNAL snk_in_pppp : t_dp_sosi;
-
- SIGNAL bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL prev_bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL bin_reader_mosi_pp : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL bin_reader_mosi_ppp : t_mem_mosi := c_mem_mosi_rst;
+ -------------------------------------------------------------------------------
+ -- ram_pointer
+ -------------------------------------------------------------------------------
+ SIGNAL toggle_ram_pointer : STD_LOGIC;
+ SIGNAL nxt_toggle_ram_pointer : STD_LOGIC;
+ SIGNAL ram_pointer : STD_LOGIC;
+ SIGNAL prv_ram_pointer : STD_LOGIC;
- SIGNAL nxt_bin_writer_mosi : t_mem_mosi;
- SIGNAL bin_writer_mosi : t_mem_mosi;
+ -------------------------------------------------------------------------------
+ -- bin_reader
+ -------------------------------------------------------------------------------
+ SIGNAL bin_reader_mosi : t_mem_mosi;
+ SIGNAL bin_reader_miso : t_mem_miso;
- SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_wr_mosi : t_mem_mosi;
+ SIGNAL prv_bin_reader_mosi : t_mem_mosi;
- SIGNAL nxt_bin_arbiter_rd_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_rd_mosi : t_mem_mosi;
+ -------------------------------------------------------------------------------
+ -- bin_writer
+ -------------------------------------------------------------------------------
+ SIGNAL bin_reader_to_writer_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_rd_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL bin_reader_rd_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL common_ram_r_w_miso : t_mem_miso := c_mem_miso_rst;
-
- SIGNAL init_phase : STD_LOGIC := '1';
- SIGNAL nxt_init_phase : STD_LOGIC;
-
- SIGNAL rd_cnt_allowed : STD_LOGIC := '0';
- SIGNAL rd_cnt_allowed_pp : STD_LOGIC := '0';
-
- SIGNAL toggle_detect : STD_LOGIC := '0';
- SIGNAL toggle_detect_pp : STD_LOGIC;
- SIGNAL toggle_detect_false : STD_LOGIC := '1';
- SIGNAL nxt_toggle_detect_false : STD_LOGIC;
-
- SIGNAL nxt_prev_wrdata : NATURAL;
- SIGNAL prev_wrdata : NATURAL;
- SIGNAL prev_prev_wrdata : NATURAL;
- SIGNAL prev_prev_prev_wrdata : NATURAL;
-
- SIGNAL sync_detect : STD_LOGIC := '0';
- SIGNAL sync_detect_pp : STD_LOGIC;
-
- SIGNAL same_r_w_address : STD_LOGIC;
- SIGNAL same_r_w_address_pp : STD_LOGIC;
-
- --debug signals
- SIGNAL dbg_state_string : STRING(1 TO 3) := " ";
- SIGNAL dbg_snk_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
+ SIGNAL nxt_bin_writer_mosi : t_mem_mosi;
+ SIGNAL bin_writer_mosi : t_mem_mosi;
+
+ -------------------------------------------------------------------------------
+ -- bin_arbiter
+ -------------------------------------------------------------------------------
+ SIGNAL bin_arbiter_wr_ram_pointer : STD_LOGIC;
+ SIGNAL bin_arbiter_rd_ram_pointer : STD_LOGIC;
+ SIGNAL prv_bin_arbiter_rd_ram_pointer : STD_LOGIC;
+
+ SIGNAL read_allowed : BOOLEAN;
+ SIGNAL prv_read_allowed : BOOLEAN;
+
+ SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
+ SIGNAL bin_arbiter_wr_mosi : t_mem_mosi;
+ SIGNAL bin_arbiter_rd_mosi : t_mem_mosi;
+ SIGNAL bin_arbiter_rd_miso : t_mem_miso;
+
+ -------------------------------------------------------------------------------
+ -- 2x RAM (common_ram_r_w) instances
+ -------------------------------------------------------------------------------
+ CONSTANT c_nof_ram_pages : NATURAL := 2;
+
+ CONSTANT c_ram : t_c_mem := (latency => 1,
+ adr_w => c_ram_adr_w,
+ dat_w => c_ram_dat_w,
+ nof_dat => g_nof_bins,
+ init_sl => '0');
+
+ SIGNAL common_ram_r_w_wr_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
+ SIGNAL common_ram_r_w_rd_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
+ SIGNAL common_ram_r_w_rd_miso_arr : t_mem_miso_arr(1 DOWNTO 0);
+
+ SIGNAL histogram_wr_mosi : t_mem_mosi;
+ SIGNAL histogram_rd_mosi : t_mem_mosi;
+ SIGNAL histogram_rd_miso : t_mem_miso;
+
+ -------------------------------------------------------------------------------
+ -- ram_clear
+ -------------------------------------------------------------------------------
+ CONSTANT c_data_cnt_w : NATURAL := ceil_log2(g_nof_data_per_sync);
+
+ SIGNAL data_cnt : STD_LOGIC_VECTOR(c_data_cnt_w-1 DOWNTO 0);
+ SIGNAL nxt_data_cnt : STD_LOGIC_VECTOR(c_data_cnt_w-1 DOWNTO 0);
+
+ SIGNAL ram_clear : STD_LOGIC;
+
+ SIGNAL ram_clear_address : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
+ SIGNAL nxt_ram_clear_address : STD_LOGIC_VECTOR(c_ram_adr_w-1 DOWNTO 0);
+
+ SIGNAL i_ram_clearing : STD_LOGIC;
+ SIGNAL nxt_ram_clearing : STD_LOGIC;
-
- SIGNAL ram_pointer : STD_LOGIC := '0';
- SIGNAL cycle_cnt : NATURAL := 0 ;
- SIGNAL nxt_cycle_cnt : NATURAL := 0 ;
--- SIGNAL wr_en : STD_LOGIC := '0';
--- SIGNAL nxt_wr_en : STD_LOGIC;
--- SIGNAL wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
--- SIGNAL nxt_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
--- SIGNAL wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
--- SIGNAL rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
--- SIGNAL rd_en : STD_LOGIC := '0';
--- SIGNAL rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
--- SIGNAL rd_val : STD_LOGIC;
-
- SIGNAL mm_adr_cnt : NATURAL := 0 ;
- SIGNAL mm_adr_illegal : STD_LOGIC := '0';
- SIGNAL mm_adr_illegal_pp : STD_LOGIC := '0';
-
-
- SIGNAL ram_0_wr_en : STD_LOGIC;
- SIGNAL ram_0_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_0_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_0_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_0_rd_en : STD_LOGIC;
- SIGNAL ram_0_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_0_rd_val : STD_LOGIC;
-
- SIGNAL ram_1_wr_en : STD_LOGIC;
- SIGNAL ram_1_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_1_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_1_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_1_rd_en : STD_LOGIC;
- SIGNAL ram_1_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_1_rd_val : STD_LOGIC;
-
- SIGNAL ram_out_wr_en : STD_LOGIC;
- SIGNAL ram_out_wr_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_out_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_out_rd_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_out_rd_en : STD_LOGIC;
- SIGNAL ram_out_rd_dat : STD_LOGIC_VECTOR(c_word_w -1 DOWNTO 0);
- SIGNAL ram_out_rd_val : STD_LOGIC;
-
- SIGNAL prev_ram_out_wr_adr : STD_LOGIC_VECTOR(g_in_data_w -1 DOWNTO c_adr_low);
- SIGNAL ram_out_same_w_r_adr : STD_LOGIC;
-
BEGIN
-
- -----------------------------------------------------------------------------
- -- Check Generics
- -----------------------------------------------------------------------------
- ASSERT c_adr_low_calc>0 REPORT "ceil_log2(g_nof_bins) is as large as g_in_data_w, don't increase g_nof_bins" SEVERITY WARNING;
-
- -----------------------------------------------------------------------------
- -- Assign inputs of RAM: <-- use parts of description for bin_writer
- -- . Determine address based on input data
- -- . Compare adress with the two previous adresses and if:
- -- . it is the same as the last adress increase a counter
- -- . it is the same as 2 cycles back but not the last copy the data to be
- -- written directly into a local counter instead of trying to read (ask)
- -- it back from RAM at the same clock cycle (which is impossible)
- -- . it is not the same enable the nxt_wr_dat data to be written .
- -- at the next cycle by making nxt_wr_en high .
- -- . Write the wr_dat data to the RAM
- -- . At the snk_in.sync pulse:
- -- . let first 3 cycles start counting from 0 again
- -- . (plus 3 cycles) let counting depend on values in RAM (which should
- -- be 0)
- -- . Restart or pause counting when a snk_in.valid = '0' appears:
- -- . pause when adress is the same as the previous adress
- -- . restart from 0 when adress is not the same as previous adress
- -- . restart from 0 when also a sync appears
- --
- --
- -- . in : snk_in (latency: 0)
- -- : common_ram_r_w_miso (latency: 2)
- -- . out : snk_in_pppp.sync (latency: 4)
- -- : bin_arbiter_wr_mosi (latency: 4)
- -- : bin_arbiter_rd_mosi (latency: 1)
- --
- ----------------------------------------------------------------------------
-
- -----------------------------------------------------------------------------
- -- Bin reader: Convert snk_in data to bin_reader_mosi with read request
- -- and generate signals for detection of problems in the
- -- consecutive data.
- -- . in : snk_in (latency: 0)
- -- : bin_arbiter_rd_miso (latency: 2)
- -- . out : init_phase (latency: 0 ?
- -- : bin_reader_mosi (latency: 0)
- -- : prev_bin_reader_mosi (latency: 1)
- -- : bin_reader_mosi_pp (latency: 2)
- -- : bin_reader_mosi_ppp (latency: 3)
- -- : bin_reader_rd_miso (latency: 2)
- -- : rd_cnt_allowed_pp (latency: 2)
- -- : same_r_w_address_pp (latency: 2)
- -- : toggle_detect_pp (latency: 2)
- -- : sync_detect (latency: 0)
- -- : sync_detect_pp (latency: 2)
- -----------------------------------------------------------------------------
- bin_reader_mosi.rd <= snk_in.valid; -- when 1, count allowed
- bin_reader_mosi.address(c_adr_w-1 DOWNTO 0) <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low);
- bin_reader_rd_miso <= bin_arbiter_rd_miso;
-
- --snk_in pipeline; Enable sync and valid comparisons
- u_dp_pipeline_snk_in_1_cycle : ENTITY dp_lib.dp_pipeline
- GENERIC MAP (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => snk_in,
- src_out => snk_in_p
- );
-
--- init_phase <= '0' WHEN snk_in_p.sync = '1'; -- ELSE will be impossible since the init_phase may only be triggered once on the first sync
- nxt_init_phase <= '0' WHEN snk_in.sync='1' ELSE init_phase;
-
- p_init_phase : PROCESS(dp_clk, dp_rst)
+
+ -------------------------------------------------------------------------------
+ -- ram_pointer: Keep track of what RAM to target
+ -- . Target either RAM 0 or 1 per sync period
+ -- . RD/WR sides of RAM have shifted sync periods due to rd>wr latency
+ -- . e.g. a new sync period is read while an old sync period is written
+ -- . Solution: treat the RAM pointer as MS address bit in separate RD/WR buses
+ -- . ram_pointer is synchronous to snk_in.sync
+ -------------------------------------------------------------------------------
+ p_ram_pointer : PROCESS(dp_rst, dp_clk) IS
BEGIN
- IF dp_rst = '1' THEN
- init_phase <= '1';
- toggle_detect_false <= '1';
+ IF dp_rst='1' THEN
+ prv_ram_pointer <= '0';
+ toggle_ram_pointer <= '0';
ELSIF RISING_EDGE(dp_clk) THEN
- init_phase <= nxt_init_phase;
- toggle_detect_false <= nxt_toggle_detect_false;
+ toggle_ram_pointer <= nxt_toggle_ram_pointer;
+ prv_ram_pointer <= ram_pointer;
END IF;
END PROCESS;
-
- -- Enable sync comparisons
- u_dp_pipeline_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline
- GENERIC MAP (
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => snk_in,
- src_out => snk_in_pp
- );
-
- -- Enable switching the ram_pointer
- u_dp_pipeline_snk_in_4_cycle : ENTITY dp_lib.dp_pipeline
- GENERIC MAP (
- g_pipeline => 4 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => snk_in,
- src_out => snk_in_pppp
- );
-
- dbg_snk_data <= snk_in_pp.data(g_in_data_w-1 DOWNTO 0);
-
--- toggle_detect_false <= '0' WHEN snk_in_pp.sync = '1'; -- ELSE will be impossible since the toggle_detect_false may only be triggered once on the first sync
- nxt_toggle_detect_false <= '0' WHEN snk_in_p.sync='1' ELSE toggle_detect_false;
- sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR snk_in_p.sync='1' OR snk_in_pp.sync='1') ELSE '0'; -- @sync, first 3 cycles would try to read from the wrong (old) RAM block, detect this problem
-
- -- Line up to p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_sync_detect_2_cycle : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => sync_detect,
- out_dat => sync_detect_pp
- );
-
- -- Enable adress comparisons 1 cycle back
- -- Skip unvalid data with trigger bin_reader_mosi.rd to make comparisons between unvalid-data-seperated data possible.
- u_common_pipeline_bin_reader_mosi_1_cycle : ENTITY common_lib.common_pipeline
- GENERIC MAP (
- g_representation => "UNSIGNED", --orig. signed
- g_pipeline => 1,
- g_in_dat_w => c_adr_w, -- c_mem_address_w
- g_out_dat_w => c_adr_w
- )
- PORT MAP (
- clk => dp_clk,
- clken => bin_reader_mosi.rd, -- '1',
- in_dat => STD_LOGIC_VECTOR(bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
- out_dat => prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)
- );
-
- -- Enable adress comparisons 2 cycles back
- u_common_pipeline_bin_reader_mosi_2_cycle : ENTITY common_lib.common_pipeline
- GENERIC MAP (
- g_representation => "UNSIGNED", --orig. signed
- g_pipeline => 1,
- g_in_dat_w => c_adr_w,
- g_out_dat_w => c_adr_w
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => STD_LOGIC_VECTOR(prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
- out_dat => bin_reader_mosi_pp.address(c_adr_w-1 DOWNTO 0)
- );
-
- -- Enable adress comparisons 3 cycles back
- u_common_pipeline_bin_reader_mosi_3_cycle : ENTITY common_lib.common_pipeline
- GENERIC MAP (
- g_representation => "UNSIGNED", --orig. signed
- g_pipeline => 2,
- g_in_dat_w => c_adr_w,
- g_out_dat_w => c_adr_w
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => STD_LOGIC_VECTOR(prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
- out_dat => bin_reader_mosi_ppp.address(c_adr_w-1 DOWNTO 0)
- );
-
-
- -- Only count sequential valid data on the same address when: address is the same as last and 1 or 2 cycles after the sync when in sync_detect; address is the same as last and past the initialisation and outside sync_detect
- rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( snk_in_p.sync='1' OR (snk_in_pp.sync='1' AND snk_in_p.valid='1') ) )
- OR (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND sync_detect='0')
- ELSE '0';
-
- -- Line rd_cnt_allowed up to p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_rd_cnt_allowed : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => rd_cnt_allowed,
- out_dat => rd_cnt_allowed_pp
- );
-
- -- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync --also @sync, one wil be true; use NOT(1 or 1) instead of (0 or 0)
- toggle_detect <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND NOT(snk_in.sync='1' OR snk_in_p.sync='1') )
- ELSE '0';
-
- -- Line up to p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_toggle_detect : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => toggle_detect,
- out_dat => toggle_detect_pp
- );
-
- -- Detect an (valid) address that has to be read as well as written at the same time
- same_r_w_address <= snk_in.valid WHEN (bin_reader_mosi.address = bin_reader_mosi_ppp.address AND init_phase = '0' AND sync_detect = '0') ELSE '0';
-
- -- Line up top p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_same_r_w_address : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => same_r_w_address,
- out_dat => same_r_w_address_pp
- );
+ -- Don't toggle the RAM pointer on the first sync as we're already reading the RAM at that point.
+ nxt_toggle_ram_pointer <= '1' WHEN snk_in.sync='1' ELSE toggle_ram_pointer;
+ -- Toggle the RAM pointer starting from 2nd sync onwards
+ ram_pointer <= NOT prv_ram_pointer WHEN snk_in.sync='1' AND toggle_ram_pointer='1' ELSE prv_ram_pointer;
- -----------------------------------------------------------------------------
- -- Bin writer : increments current bin value and sets up write request
- -- . in : toggle_detect_pp (latency: 2)
- -- . in : same_r_w_address_pp (latency: 2)
- -- . in : bin_reader_mosi_pp (latency: 2)
- -- . in : bin_reader_rd_miso (latency: 2) aka bin_arbiter_rd_miso or common_ram_r_w_miso
- -- . in : rd_cnt_allowed_pp (latency: 2)
- -- . in : sync_detect_pp
- -- . out : bin_writer_mosi (latency: 3)
- -----------------------------------------------------------------------------
- p_nxt_bin_writer_mosi : PROCESS(bin_reader_rd_miso,
- bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp) IS
- BEGIN
- nxt_bin_writer_mosi <= c_mem_mosi_rst;
- dbg_state_string <= "unv";
- IF bin_reader_rd_miso.rdval='1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_reader_rd_miso.rddata, 1);
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= TO_UINT(bin_reader_rd_miso.rddata) + 1;
- dbg_state_string <= "val";
-
- ELSIF toggle_detect_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w);
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= prev_prev_wrdata+1;
- dbg_state_string <= "td ";
-
- ELSIF rd_cnt_allowed_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC( (prev_wrdata + 1), c_mem_data_w);
- nxt_prev_wrdata <= prev_wrdata + 1;
- dbg_state_string <= "r# ";
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
-
- ELSIF sync_detect_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; snk_in_p.sync (thus new adress): 1; snk_in_pp.sync (thus new adress): 1
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= 1;
- dbg_state_string <= "sd ";
-
- ELSIF same_r_w_address_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= prev_prev_prev_wrdata + 1;
- dbg_state_string <= "srw";
- END IF;
- END PROCESS;
-
- p_prev_wrdata : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi.wr) IS --seperated from p_bin_writer_mosi since the implementation was unwanted
+ -------------------------------------------------------------------------------
+ -- bin_reader : reads bin from RAM, sends bin to bin_writer.
+ -- . Input : snk_in (input data stream)
+ -- bin_reader_miso (reply to RAM read request: rddata = bin count)
+ -- ram_pointer (to put in MOSI buses as MS address bit)
+ -- . Output : bin_reader_mosi (RAM read request, address = bin)
+ -- bin_reader_to_writer_mosi (address = bin, wrdata = bin count)
+ -------------------------------------------------------------------------------
+ -- Fetch the bin from RAM
+ bin_reader_mosi.wrdata <= (OTHERS=>'0');
+ bin_reader_mosi.wr <= '0';
+ bin_reader_mosi.rd <= snk_in.valid;
+ bin_reader_mosi.address <= RESIZE_UVEC(ram_pointer & snk_in.data(g_data_w-1 DOWNTO c_adr_low), c_word_w);
+
+ -- Store the rd address as bin_writer needs to know where to write the bin count
+ p_prv_bin_reader_mosi : PROCESS(dp_clk, dp_rst) IS
BEGIN
IF dp_rst = '1' THEN
- prev_wrdata <= 0;
- prev_prev_wrdata <= 0;
- prev_prev_prev_wrdata <= 0;
- ELSIF nxt_bin_writer_mosi.wr='1' AND RISING_EDGE(dp_clk) THEN
- prev_wrdata <= nxt_prev_wrdata;
- prev_prev_wrdata <= prev_wrdata;
- prev_prev_prev_wrdata <= prev_prev_wrdata;
+ prv_bin_reader_mosi <= c_mem_mosi_rst;
+ ELSIF RISING_EDGE(dp_clk) THEN
+ prv_bin_reader_mosi <= bin_reader_mosi;
END IF;
END PROCESS;
- p_bin_writer_mosi : PROCESS(dp_clk, dp_rst) IS --, nxt_bin_writer_mosi, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata
+ -- Forward the read bin + count to bin writer
+ bin_reader_to_writer_mosi.wr <= bin_reader_miso.rdval;
+ bin_reader_to_writer_mosi.wrdata <= RESIZE_UVEC(bin_reader_miso.rddata(c_ram_dat_w-1 DOWNTO 0), c_mem_data_w);
+ bin_reader_to_writer_mosi.address <= prv_bin_reader_mosi.address;
+
+
+ -------------------------------------------------------------------------------
+ -- bin_writer : Increment the bin, forward write request to bin_arbiter
+ -- . Input : bin_reader_to_writer_mosi (from bin_reader = bin + bin count)
+ -- . Output : bin_writer_mosi (to bin_arbiter = bin + incremented bin count)
+ -------------------------------------------------------------------------------
+ nxt_bin_writer_mosi.rd <= '0';
+ nxt_bin_writer_mosi.wr <= bin_reader_to_writer_mosi.wr;
+ nxt_bin_writer_mosi.address <= bin_reader_to_writer_mosi.address;
+ nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_reader_to_writer_mosi.wrdata, 1) WHEN bin_reader_to_writer_mosi.wr='1' ELSE bin_writer_mosi.wrdata;
+
+ -- Register the outputs to bin_arbiter (above we have a combinational adder = propagation delay)
+ p_bin_writer_mosi : PROCESS(dp_clk, dp_rst) IS
BEGIN
IF dp_rst = '1' THEN
- bin_writer_mosi <= c_mem_mosi_rst;
--- prev_wrdata <= 0;
--- prev_prev_wrdata <= 0;
--- prev_prev_prev_wrdata <= 0;
+ bin_writer_mosi <= c_mem_mosi_rst;
ELSIF RISING_EDGE(dp_clk) THEN
- bin_writer_mosi <= nxt_bin_writer_mosi;
--- IF nxt_bin_writer_mosi.wr = '1' THEN
--- prev_wrdata <= nxt_prev_wrdata;
--- prev_prev_wrdata<= prev_wrdata;
--- prev_prev_prev_wrdata <= prev_prev_wrdata;
--- END IF;
+ bin_writer_mosi <= nxt_bin_writer_mosi;
END IF;
END PROCESS;
- -----------------------------------------------------------------------------
- -- Bin Arbiter: Determine next RAM access
- -- . in : bin_reader_mosi (latency: 0)
- -- : init_phase (latency: 0)
- -- : prev_bin_reader_mosi (latency: 1)
- -- : bin_reader_mosi_pp (latency: 2)
- -- : bin_reader_mosi_ppp (latency: 3)
- -- : bin_writer_mosi (latency: 3)
- -- : sync_detect (latency: 0? or 3?
- -- : common_ram_r_w_miso (latency: 2)
- -- . out : bin_arbiter_rd_mosi (latency: 1)
- -- . : bin_arbiter_rd_miso (latency: 2)
- -- . : bin_arbiter_wr_mosi (latency: 4)
- -----------------------------------------------------------------------------
- nxt_bin_arbiter_wr_mosi <= bin_writer_mosi;
- -- Read RAM when subsequent addresses are not the same, when there is no toggle detected and only when the same address is not going to be written to. When a sync is detected don't read in the old RAM block.
- nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address
- AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) AND sync_detect='0')
- OR (init_phase = '1') ELSE '0';
- nxt_bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
-
- p_bin_arbiter_mosi : PROCESS(dp_clk, dp_rst) IS --, nxt_bin_arbiter_wr_mosi, nxt_bin_arbiter_rd_mosi
+ -------------------------------------------------------------------------------
+ -- bin_arbiter : Take care of simultaneous rd/wr to the same RAM address
+ -- . Input: bin_reader_mosi (wants to read bins)
+ -- bin_writer_mosi (wants to write to bins)
+ -- bin_arbiter_rd_miso (carries the bins requested by bin_reader)
+ -- . Output: bin_arbiter_wr_mosi (wr requests to RAM)
+ -- bin_arbiter_rd_mosi (rd requests to RAM)
+ -- bin_reader_miso (carries the bins requested by bin_reader)
+ -------------------------------------------------------------------------------
+ -- Really simple arbitration: always allow writes, only allow reads when possible (rd_addr != wr_addr).
+ read_allowed <= FALSE WHEN bin_writer_mosi.wr='1' AND bin_writer_mosi.address=bin_reader_mosi.address ELSE TRUE;
+ -- save previous read_allowed
+ p_prv_read_allowed: PROCESS(dp_rst, dp_clk) IS
BEGIN
- IF dp_rst = '1' THEN
- bin_arbiter_wr_mosi <= c_mem_mosi_rst;
- bin_arbiter_rd_mosi <= c_mem_mosi_rst;
+ IF dp_rst='1' THEN
+ prv_read_allowed <= FALSE;
ELSIF RISING_EDGE(dp_clk) THEN
- bin_arbiter_wr_mosi <= nxt_bin_arbiter_wr_mosi;
- bin_arbiter_rd_mosi <= nxt_bin_arbiter_rd_mosi;
+ prv_read_allowed <= read_allowed;
END IF;
END PROCESS;
-
--- -- Temporary debug data
--- sla_out_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
-
- -- Make RAM data available for the bin_reader (or bin_writer)
- bin_arbiter_rd_miso <= common_ram_r_w_miso;
-
-
- -----------------------------------------------------------------------------
- -- RAM selector & Dual swapped RAM instances:
- -- 4 cycles after a sync the RAM block is swapped for an empty one to allow
- -- the block to be read out till the next sync+3 cycles
- -- The input is the st side, the output is the dp clocked mm side.
- --
- -- Depending on ram_pointer:
- -- ram_pointer = '0': input RAM_0, output RAM_1
- -- ram_pointer = '1': input RAM_1, output RAM_0
- --
- -- input in: snk_in_pppp.sync (latency: 4)
- -- bin_arbiter_wr_mosi (latency: 4)
- -- bin_arbiter_rd_mosi (latency: 1)
- -- out: common_ram_r_w_miso (latency: 2)
- --
- -- output in: ram_out_wr_en; ram_out_wr_dat; ram_out_wr_adr; ram_out_rd_adr;
- -- ram_out_rd_en
- -- out: ram_out_rd_dat; ram_out_rd_val
- -----------------------------------------------------------------------------
- p_ram_pointer_at_sync : PROCESS(snk_in_pppp) IS -- needs nxt_ram_pointer ??
+
+ -- Forward MOSI buses
+ -- . RD MOSI
+ bin_arbiter_rd_mosi.wr <= '0';
+ bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN read_allowed ELSE '0';
+ bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
+ -- . WR MOSI
+ bin_arbiter_wr_mosi.rd <= '0';
+ bin_arbiter_wr_mosi.wr <= bin_writer_mosi.wr;
+ bin_arbiter_wr_mosi.wrdata <= bin_writer_mosi.wrdata;
+ bin_arbiter_wr_mosi.address <= bin_writer_mosi.address;
+
+ -- Loop back the WR data to the RD side when read was not allowed or on second read of same address
+ p_bin_reader_miso : PROCESS(prv_read_allowed, bin_reader_mosi, bin_reader_miso, bin_writer_mosi, read_allowed, bin_arbiter_rd_miso) IS
BEGIN
- IF snk_in_pppp.sync = '1' THEN --needs snk_in_pppp <--
- ram_pointer <= NOT(ram_pointer);
+ bin_reader_miso <= bin_arbiter_rd_miso;
+ IF prv_bin_reader_mosi.rd = '1' AND prv_read_allowed = FALSE THEN -- Fake succesful readback when read was not allowed
+ bin_reader_miso.rdval <= '1';
+ bin_reader_miso.rddata <= bin_writer_mosi.wrdata;
+ ELSIF read_allowed = TRUE THEN
+ bin_reader_miso <= bin_arbiter_rd_miso;
+ ELSIF (prv_bin_reader_mosi.rd = '1' AND bin_reader_mosi.rd='1') AND (prv_bin_reader_mosi.address=bin_reader_mosi.address) THEN -- 2 reads on same address in row: 2nd read is outdated so return wrdata here
+ bin_reader_miso.rdval <= '1';
+ bin_reader_miso.rddata <= bin_writer_mosi.wrdata;
END IF;
END PROCESS;
-
- p_ram_pointer : PROCESS(ram_pointer, bin_arbiter_wr_mosi, bin_arbiter_rd_mosi, ram_0_rd_dat, ram_0_rd_val,
- ram_out_wr_en, ram_out_wr_dat, ram_out_wr_adr, ram_out_rd_adr, ram_out_rd_en, ram_1_rd_dat, ram_1_rd_val) IS
- BEGIN
- IF ram_pointer='0' THEN
-
- -- ST side (RAM 0)
- ram_0_wr_en <= bin_arbiter_wr_mosi.wr; -- bin_arbiter_wr_mosi.wr wr_en
- ram_0_wr_dat <= bin_arbiter_wr_mosi.wrdata(c_word_w-1 DOWNTO 0); -- bin_arbiter_wr_mosi.wrdata wr_dat
- ram_0_wr_adr <= bin_arbiter_wr_mosi.address(c_adr_w-1 DOWNTO 0); -- bin_arbiter_wr_mosi.address wr_adr
- ram_0_rd_adr <= bin_arbiter_rd_mosi.address(c_adr_w-1 DOWNTO 0); -- bin_arbiter_rd_mosi.address rd_adr
- ram_0_rd_en <= bin_arbiter_rd_mosi.rd; -- bin_arbiter_rd_mosi.rd rd_en
- common_ram_r_w_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_0_rd_dat; -- common_ram_r_w_miso.rddata rd_dat
- common_ram_r_w_miso.rdval <= ram_0_rd_val; -- common_ram_r_w_miso.rdval rd_val
-
-
- -- dp_clk'd MM side (RAM 1)
- ram_1_wr_en <= ram_out_wr_en;
- ram_1_wr_dat <= ram_out_wr_dat;
- ram_1_wr_adr <= ram_out_wr_adr;
- ram_1_rd_adr <= ram_out_rd_adr;
- ram_1_rd_en <= ram_out_rd_en;
- ram_out_rd_dat <= ram_1_rd_dat;
- ram_out_rd_val <= ram_1_rd_val;
-
-
- ELSE -- ram_pointer='1'
-
- -- ST side (RAM 1)
- ram_1_wr_en <= bin_arbiter_wr_mosi.wr;
- ram_1_wr_dat <= bin_arbiter_wr_mosi.wrdata(c_word_w-1 DOWNTO 0);
- ram_1_wr_adr <= bin_arbiter_wr_mosi.address(c_adr_w-1 DOWNTO 0);
- ram_1_rd_adr <= bin_arbiter_rd_mosi.address(c_adr_w-1 DOWNTO 0);
- ram_1_rd_en <= bin_arbiter_rd_mosi.rd;
- common_ram_r_w_miso.rddata(c_word_w-1 DOWNTO 0) <= ram_1_rd_dat;
- common_ram_r_w_miso.rdval <= ram_1_rd_val;
-
- --dp_clk'd MM side (RAM 0)
- ram_0_wr_en <= ram_out_wr_en;
- ram_0_wr_dat <= ram_out_wr_dat;
- ram_0_wr_adr <= ram_out_wr_adr;
- ram_0_rd_adr <= ram_out_rd_adr;
- ram_0_rd_en <= ram_out_rd_en;
- ram_out_rd_dat <= ram_0_rd_dat;
- ram_out_rd_val <= ram_0_rd_val;
- END IF;
- END PROCESS;
-
-
- -- Dual swapped RAM instances
- ram_0: ENTITY common_lib.common_ram_r_w
- GENERIC MAP (
- g_technology => c_tech_select_default,
- g_ram => c_ram,
- g_init_file => "UNUSED"
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- clken => '1', -- only necessary for Stratix iv
- wr_en => ram_0_wr_en,
- wr_adr => ram_0_wr_adr,
- wr_dat => ram_0_wr_dat,
- rd_en => ram_0_rd_en,
- rd_adr => ram_0_rd_adr,
- rd_dat => ram_0_rd_dat,
- rd_val => ram_0_rd_val
- );
-
- ram_1: ENTITY common_lib.common_ram_r_w
- GENERIC MAP (
- g_technology => c_tech_select_default,
- g_ram => c_ram,
- g_init_file => "UNUSED"
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- clken => '1', -- only necessary for Stratix iv
- wr_en => ram_1_wr_en,
- wr_adr => ram_1_wr_adr,
- wr_dat => ram_1_wr_dat,
- rd_en => ram_1_rd_en,
- rd_adr => ram_1_rd_adr,
- rd_dat => ram_1_rd_dat,
- rd_val => ram_1_rd_val
- );
-
-
-
- -----------------------------------------------------------------------------
- -- Connect interface to DUAL swapped RAM, read out histogram statistics:
- -- . Limit the data read by the MM master to the RAM block where it started
- -- to read (the values read after a new sync will be OTHERS => '0')
- -- . In the last g_nof_bins cycles all addresses will sequentially be cleared
- --
- -- RAM selector:
- -- input: ram_out_rd_dat; ram_out_rd_val
- -- output: ram_out_wr_en; ram_out_wr_dat; ram_out_wr_adr; ram_out_rd_adr;
- -- ram_out_wr_en
- -- (PORT):
- -- input: snk_in; sla_in_ram_mosi
- -- output: sla_out_ram_miso
- -----------------------------------------------------------------------------
-
- -- Pipeline for identified illegal read requests after new sync
- u_common_pipeline_sl_mm_adr_illegal : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => mm_adr_illegal,
- out_dat => mm_adr_illegal_pp
- );
-
- p_mm_adr_illegal : PROCESS(snk_in.sync, mm_adr_cnt) IS
+
+ -------------------------------------------------------------------------------
+ -- Two RAM (common_ram_r_w) instances. The user can read the histogram from the
+ -- instance that is not being written to by the bin_arbiter.
+ -- . Input: bin_arbiter_wr_mosi (writes bins)
+ -- bin_arbiter_rd_mosi (requests to read bins to increment bin count)
+ -- histogram_rd_mosi (requests to read the bins on the user side)
+ -- histogram_wr_mosi (on user side, auto clears RAM every sync)
+ -- . Output: histogram_rd_miso (carries the bins the user wants to read)
+ -- bin_arbiter_miso (carries then bins the bin_reader wants to read)
+ -- . Note: the ram_pointer is carried (with different latencies) as MSbit in:
+ -- . bin_arbiter_wr_mosi.address
+ -- . bin_arbiter_rd_mosi.address
+ -------------------------------------------------------------------------------
+ bin_arbiter_wr_ram_pointer <= bin_arbiter_wr_mosi.address(c_ram_adr_w);
+ bin_arbiter_rd_ram_pointer <= bin_arbiter_rd_mosi.address(c_ram_adr_w);
+
+ -- Store the previous RAM pointer of the read bus
+ p_prv_ram_pointer : PROCESS(dp_clk, dp_rst) IS
BEGIN
- IF snk_in.sync = '1' AND mm_adr_cnt /= 0 THEN
- mm_adr_illegal <= '1';
- ELSIF mm_adr_cnt = g_nof_bins-1 THEN
- mm_adr_illegal <= '0';
- ELSE
+ IF dp_rst = '1' THEN
+ prv_bin_arbiter_rd_ram_pointer <= '0';
+ ELSIF RISING_EDGE(dp_clk) THEN
+ prv_bin_arbiter_rd_ram_pointer <= bin_arbiter_rd_ram_pointer;
END IF;
END PROCESS;
-
- mm_adr_cnt <= TO_UINT(sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0)) WHEN sla_in_ram_mosi.rd = '1';
- ram_out_same_w_r_adr <= '1' WHEN ram_out_wr_adr = sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0) ELSE '0';
-
- p_ram_to_fifo : PROCESS(snk_in_pp.sync, cycle_cnt, sla_in_ram_mosi.address, sla_in_ram_mosi.rd, ram_out_rd_dat, ram_out_rd_val, prev_ram_out_wr_adr, mm_adr_illegal_pp, ram_out_same_w_r_adr, bin_arbiter_wr_mosi.wrdata) IS
+
+ -- Let bin_arbiter write RAM 0 while user reads RAM 1 and vice versa
+ common_ram_r_w_wr_mosi_arr(0) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_ram_pointer='0' ELSE histogram_wr_mosi;
+ common_ram_r_w_rd_mosi_arr(0) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_ram_pointer='0' ELSE histogram_rd_mosi;
+ common_ram_r_w_wr_mosi_arr(1) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_ram_pointer='1' ELSE histogram_wr_mosi;
+ common_ram_r_w_rd_mosi_arr(1) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_ram_pointer='1' ELSE histogram_rd_mosi;
+
+ -- Let bin_arbiter read RAM 0 while user reads RAM 1 and vice versa
+ -- . We always want the MISO bus to switch 1 cycle later than the MOSI (such that the MM operation can finish); hence using prv_bin_arbiter_rd_ram_pointer.
+ bin_arbiter_rd_miso <= common_ram_r_w_rd_miso_arr(0) WHEN prv_bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1);
+ histogram_rd_miso <= common_ram_r_w_rd_miso_arr(1) WHEN prv_bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(0);
+
+ gen_common_ram_r_w : FOR i IN 0 TO c_nof_ram_pages-1 GENERATE
+ u_common_ram_r_w : ENTITY common_lib.common_ram_r_w
+ GENERIC MAP (
+ g_technology => c_tech_select_default,
+ g_ram => c_ram,
+ g_init_file => "UNUSED"
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ clken => '1',
+ wr_en => common_ram_r_w_wr_mosi_arr(i).wr,
+ wr_adr => common_ram_r_w_wr_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
+ wr_dat => common_ram_r_w_wr_mosi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0),
+ rd_en => common_ram_r_w_rd_mosi_arr(i).rd,
+ rd_adr => common_ram_r_w_rd_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
+ rd_dat => common_ram_r_w_rd_miso_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0),
+ rd_val => common_ram_r_w_rd_miso_arr(i).rdval
+ );
+ END GENERATE;
+
+
+ -------------------------------------------------------------------------------
+ -- Clear the RAM just before the next sync interval
+ -------------------------------------------------------------------------------
+ -- Count input data for automatic RAM clear before next sync interval
+ nxt_data_cnt <= (OTHERS=>'0') WHEN TO_UINT(data_cnt)=g_nof_data_per_sync-1 ELSE INCR_UVEC(data_cnt, 1) WHEN snk_in.valid='1' ELSE data_cnt;
+
+ -- Clear all g_nof_bins RAM addresses just before the next sync
+ ram_clear <= '1' WHEN TO_UINT(data_cnt)=g_nof_data_per_sync-g_nof_bins-1 ELSE '0';
+
+ -- Signal to indicate when RAM is being cleared
+ nxt_ram_clearing <= '1' WHEN ram_clear='1' ELSE '0' WHEN TO_UINT(ram_clear_address)=g_nof_bins-1 ELSE i_ram_clearing;
+
+ -- Address counter: 0 to g_nof_bins-1.
+ nxt_ram_clear_address <= INCR_UVEC(ram_clear_address, 1) WHEN i_ram_clearing='1' ELSE (OTHERS=>'0');
+
+ histogram_wr_mosi.wr <= i_ram_clearing;
+ histogram_wr_mosi.address(c_ram_adr_w-1 DOWNTO 0) <= ram_clear_address;
+ histogram_wr_mosi.wrdata <= (OTHERS=>'0');
+ histogram_wr_mosi.rd <= '0';
+
+ -- Registers
+ p_ram_clearing : PROCESS(dp_clk, dp_rst) IS
BEGIN
- IF g_ram_miso_sim_mode = FALSE THEN
- IF snk_in_pppp.sync = '1' THEN
- ram_out_wr_en <= '0';
- nxt_cycle_cnt <= 0;
- ELSIF cycle_cnt = c_clear THEN
- ram_out_wr_adr <= (OTHERS => '0');
- ram_out_wr_dat <= (OTHERS => '0');
- ram_out_wr_en <= '1';
- IF ram_out_same_w_r_adr = '1' THEN
- ram_out_rd_en <= '0';
- sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
- sla_out_ram_miso.rdval <= ram_out_rd_val;
- ELSE
- ram_out_rd_adr <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
- ram_out_rd_en <= sla_in_ram_mosi.rd;
- sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
- sla_out_ram_miso.rdval <= ram_out_rd_val;
- END IF;
- nxt_cycle_cnt <= cycle_cnt +1;
- ELSIF cycle_cnt > c_clear THEN
- ram_out_wr_adr <= INCR_UVEC(prev_ram_out_wr_adr, 1);
- ram_out_wr_dat <= (OTHERS => '0');
- nxt_cycle_cnt <= cycle_cnt +1;
- IF ram_out_same_w_r_adr = '1' OR snk_in.sync = '1' THEN
- sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
- sla_out_ram_miso.rdval <= ram_out_rd_val;
- ELSE
- ram_out_rd_adr <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
- ram_out_rd_en <= sla_in_ram_mosi.rd;
- sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
- sla_out_ram_miso.rdval <= ram_out_rd_val;
- END IF;
- ram_out_wr_en <= '1';
- ELSIF mm_adr_illegal_pp = '1' THEN
- ram_out_rd_adr <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
- ram_out_rd_en <= sla_in_ram_mosi.rd;
- sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= (OTHERS => '0');
- sla_out_ram_miso.rdval <= ram_out_rd_val;
- nxt_cycle_cnt <= cycle_cnt +1;
- ram_out_wr_en <= '0';
- ELSE
- ram_out_rd_adr <= sla_in_ram_mosi.address(c_ram.adr_w-1 DOWNTO 0);
- ram_out_rd_en <= sla_in_ram_mosi.rd;
- sla_out_ram_miso.rddata(c_ram.dat_w-1 DOWNTO 0) <= ram_out_rd_dat;
- sla_out_ram_miso.rdval <= ram_out_rd_val;
- nxt_cycle_cnt <= cycle_cnt +1;
- ram_out_wr_en <= '0';
- END IF;
- dbg_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
- ELSE
- sla_out_ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
+ IF dp_rst = '1' THEN
+ ram_clear_address <= (OTHERS=>'0');
+ i_ram_clearing <= '0';
+ data_cnt <= (OTHERS=>'0');
+ ELSIF RISING_EDGE(dp_clk) THEN
+ ram_clear_address <= nxt_ram_clear_address;
+ i_ram_clearing <= nxt_ram_clearing;
+ data_cnt <= nxt_data_cnt;
END IF;
END PROCESS;
-
-
- p_clk : PROCESS(dp_clk, dp_rst)
- BEGIN
- IF dp_rst='1' THEN
- cycle_cnt <= 0;
- ELSIF rising_edge(dp_clk) THEN
- cycle_cnt <= nxt_cycle_cnt;
- prev_ram_out_wr_adr <= ram_out_wr_adr;
- END IF;
- END PROCESS;
-
+
+ ram_clearing <= i_ram_clearing;
+
+ -------------------------------------------------------------------------------
+ -- Expose the MM buses to the user
+ -------------------------------------------------------------------------------
+ ram_miso <= histogram_rd_miso;
+ histogram_rd_mosi <= ram_mosi;
END rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd b/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
deleted file mode 100644
index ed7f5e442446030567452187cff9bf95bc72c0bc..0000000000000000000000000000000000000000
--- a/libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
+++ /dev/null
@@ -1,413 +0,0 @@
-
--- Daniel's suggested restructured st_hitogram.vhd.
-
-LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
-USE IEEE.std_logic_1164.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-
-ENTITY st_histogram_8_april IS
- GENERIC (
- g_in_data_w : NATURAL := 14; -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768) <-- maybe just g_data_w ??
- g_nof_bins : NATURAL := 512; -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
- g_nof_data : NATURAL
--- g_sim_ram_miso_mode : BOOLEAN := FALSE -- when TRUE the ram_miso bus will get a copy of the data written into the RAM.
- );
- PORT (
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
-
- -- Streaming
- snk_in : IN t_dp_sosi;
-
- -- DP clocked memory bus
- ram_mosi : IN t_mem_mosi;
- ram_miso : OUT t_mem_miso
- );
-END st_histogram_8_april;
-
-
-ARCHITECTURE rtl OF st_histogram_8_april IS
-
- CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins);
- CONSTANT c_ram : t_c_mem := (latency => 1,
- adr_w => c_adr_w, -- 9 bits needed to adress/select 512 adresses
- dat_w => c_word_w, -- 32bit, def. in common_pkg; >= c_bin_w
- nof_dat => g_nof_bins, -- 512 adresses with 32 bit words, so 512
- init_sl => '0'); -- MM side : sla_in, sla_out
-
--- CONSTANT c_mem_miso_setting : t_mem_miso := (rddata => mem_miso_init, -- c_mem_miso_rst; -- limit to 32 bit
--- rdval => '0',
--- waitrequest => '0' );
-
- CONSTANT c_adr_low_calc : INTEGER := g_in_data_w-c_adr_w; -- Calculation might yield a negative number
- CONSTANT c_adr_low : NATURAL := largest(0, c_adr_low_calc); -- Override any negative value of c_adr_low_calc
-
--- SIGNAL mem_miso_init : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS => '0');
-
- SIGNAL bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst;
-
- SIGNAL nxt_bin_writer_mosi : t_mem_mosi;
- SIGNAL bin_writer_mosi : t_mem_mosi;
-
- SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_wr_mosi : t_mem_mosi;
-
- SIGNAL nxt_bin_arbiter_rd_mosi : t_mem_mosi;
- SIGNAL bin_arbiter_rd_mosi : t_mem_mosi;
-
- SIGNAL bin_arbiter_rd_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL bin_reader_rd_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL common_ram_r_w_0_miso : t_mem_miso := c_mem_miso_rst;
-
- SIGNAL init_phase : STD_LOGIC := '1';
- SIGNAL nxt_init_phase : STD_LOGIC;
- SIGNAL rd_cnt_allowed : STD_LOGIC := '0';
- SIGNAL rd_cnt_allowed_pp : STD_LOGIC := '0';
- SIGNAL toggle_detect : STD_LOGIC := '0';
- SIGNAL toggle_detect_pp : STD_LOGIC;
- SIGNAL toggle_detect_false : STD_LOGIC := '1';
- SIGNAL nxt_prev_wrdata : NATURAL;
- SIGNAL prev_wrdata : NATURAL;
- SIGNAL prev_prev_wrdata : NATURAL;
- SIGNAL prev_prev_prev_wrdata: NATURAL;
- SIGNAL sync_detect : STD_LOGIC := '0';
- SIGNAL sync_detect_pp : STD_LOGIC;
- SIGNAL same_r_w_address : STD_LOGIC;
- SIGNAL same_r_w_address_pp : STD_LOGIC;
-
- --pipelined signals
- SIGNAL snk_in_p : t_dp_sosi;
- SIGNAL snk_in_pp : t_dp_sosi;
- SIGNAL prev_bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst ;
- SIGNAL bin_reader_mosi_pp : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL bin_reader_mosi_ppp : t_mem_mosi := c_mem_mosi_rst;
-
- --debug signals
--- SIGNAL nxt_dbg_sync_detect : STD_LOGIC;
--- SIGNAL dbg_sync_detect : STD_LOGIC;
- SIGNAL dbg_state_string : STRING(1 TO 3) := " ";
- SIGNAL dbg_snk_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0);
-
-
-BEGIN
-
- -----------------------------------------------------------------------------
- -- Bin reader: Convert snk_in data to bin_reader_mosi with read request
- -- and generate signals for detection of problems in the
- -- consecutive data.
- -- . in : snk_in (latency: 0)
- -- : bin_arbiter_rd_miso (latency: 2)
- -- . out : init_phase (latency: 0 ?
- -- : bin_reader_mosi (latency: 0)
- -- : prev_bin_reader_mosi (latency: 1)
- -- : bin_reader_mosi_pp (latency: 2)
- -- : bin_reader_mosi_ppp (latency: 3)
- -- : bin_reader_rd_miso (latency: 2)
- -- : rd_cnt_allowed_pp (latency: 2)
- -- : same_r_w_address_pp (latency: 2)
- -- : toggle_detect_pp (latency: 2)
- -- : sync_detect (latency: 0)
- -- : sync_detect_pp (latency: 2)
- -----------------------------------------------------------------------------
- bin_reader_mosi.rd <= snk_in.valid; -- when 1, count allowed
- bin_reader_mosi.address(c_adr_w-1 DOWNTO 0) <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low);
- bin_reader_rd_miso <= bin_arbiter_rd_miso;
-
- --snk_in pipeline; Enable sync and valid comparisons
- u_dp_pipeline_snk_in_1_cycle : ENTITY dp_lib.dp_pipeline
- GENERIC MAP (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => snk_in,
- src_out => snk_in_p
- );
-
- init_phase <= '0' WHEN snk_in_p.sync = '1'; -- ELSE will be impossible since the init_phase may only be triggered once on the first sync
--- nxt_init_phase <= '0' WHEN snk_in_p_.sync='1' ELSE init_phase;
-
--- p_init_phase : PROCESS(dp_clk, dp_rst)
--- BEGIN
--- IF dp_rst = '1' THEN
--- init_phase <= '1';
--- ELSIF RISING_EDGE(dp_clk) THEN
--- init_phase <= nxt_init_phase;
--- END IF;
--- END PROCESS;
-
- -- Enable sync comparisons
- u_dp_pipeline_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline
- GENERIC MAP (
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => snk_in,
- src_out => snk_in_pp
- );
-
- dbg_snk_data <= snk_in_pp.data(g_in_data_w-1 DOWNTO 0);
-
- toggle_detect_false <= '0' WHEN snk_in_pp.sync = '1'; -- ELSE will be impossible since the toggle_detect_false may only be triggered once on the first sync
- sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR snk_in_p.sync='1' OR snk_in_pp.sync='1') ELSE '0'; -- @sync, first 3 cycles would try to read from the wrong (old) RAM block, detect this problem
-
- -- Line up to p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_sync_detect_2_cycle : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => sync_detect,
- out_dat => sync_detect_pp
- );
-
- -- Enable adress comparisons 1 cycle back
- -- Skip unvalid data with trigger bin_reader_mosi.rd to make comparisons between unvalid-data-seperated data possible.
- u_common_pipeline_bin_reader_mosi_1_cycle : ENTITY common_lib.common_pipeline
- GENERIC MAP (
- g_representation => "UNSIGNED", --orig. signed
- g_pipeline => 1,
- g_in_dat_w => c_adr_w, -- c_mem_address_w
- g_out_dat_w => c_adr_w
- )
- PORT MAP (
- clk => dp_clk,
- clken => bin_reader_mosi.rd, -- '1',
- in_dat => STD_LOGIC_VECTOR(bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
- out_dat => prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)
- );
-
- -- Enable adress comparisons 2 cycles back
- u_common_pipeline_bin_reader_mosi_2_cycle : ENTITY common_lib.common_pipeline
- GENERIC MAP (
- g_representation => "UNSIGNED", --orig. signed
- g_pipeline => 1,
- g_in_dat_w => c_adr_w,
- g_out_dat_w => c_adr_w
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => STD_LOGIC_VECTOR(prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
- out_dat => bin_reader_mosi_pp.address(c_adr_w-1 DOWNTO 0)
- );
-
- -- Enable adress comparisons 3 cycles back
- u_common_pipeline_bin_reader_mosi_3_cycle : ENTITY common_lib.common_pipeline
- GENERIC MAP (
- g_representation => "UNSIGNED", --orig. signed
- g_pipeline => 2,
- g_in_dat_w => c_adr_w,
- g_out_dat_w => c_adr_w
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => STD_LOGIC_VECTOR(prev_bin_reader_mosi.address(c_adr_w-1 DOWNTO 0)),
- out_dat => bin_reader_mosi_ppp.address(c_adr_w-1 DOWNTO 0)
- );
-
-
- -- Only count sequential valid data on the same address when: address is the same as last and 1 or 2 cycles after the sync when in sync_detect; address is the same as last and past the initialisation and outside sync_detect
- rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( snk_in_p.sync='1' OR (snk_in_pp.sync='1' AND snk_in_p.valid='1') ) )
- OR (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND sync_detect='0')
- ELSE '0';
-
- -- Line rd_cnt_allowed up to p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_rd_cnt_allowed : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => rd_cnt_allowed,
- out_dat => rd_cnt_allowed_pp
- );
-
- -- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync --also @sync, one wil be true; use NOT(1 or 1) instead of (0 or 0)
- toggle_detect <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND NOT(snk_in.sync='1' OR snk_in_p.sync='1') )
- ELSE '0';
-
-
- -- Line up to p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_toggle_detect : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => toggle_detect,
- out_dat => toggle_detect_pp
- );
-
- -- Detect an (valid) address that has to be read as well as written at the same time
- same_r_w_address <= snk_in.valid WHEN (bin_reader_mosi.address = bin_reader_mosi_ppp.address AND init_phase = '0' AND sync_detect = '0') ELSE '0';
-
- -- Line up top p_nxt_bin_writer_mosi process
- u_common_pipeline_sl_same_r_w_address : ENTITY common_lib.common_pipeline_sl
- GENERIC MAP(
- g_pipeline => 2 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- clk => dp_clk,
- in_dat => same_r_w_address,
- out_dat => same_r_w_address_pp
- );
-
-
- -----------------------------------------------------------------------------
- -- Bin writer : increments current bin value and sets up write request
- -- . in : toggle_detect_pp (latency: 2)
- -- . in : same_r_w_address_pp (latency: 2)
- -- . in : bin_reader_mosi_pp (latency: 2)
- -- . in : bin_reader_rd_miso (latency: 2) aka bin_arbiter_rd_miso or common_ram_r_w_0_miso
- -- . in : rd_cnt_allowed_pp (latency: 2)
- -- . in : sync_detect_pp
- -- . out : bin_writer_mosi (latency: 3)
- -----------------------------------------------------------------------------
- p_nxt_bin_writer_mosi : PROCESS(bin_reader_rd_miso,
- bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp) IS -- init_phase unnecesary? ; removed: common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata,
- BEGIN
- nxt_bin_writer_mosi <= c_mem_mosi_rst;
- dbg_state_string <= "unv";
- IF bin_reader_rd_miso.rdval='1' THEN -- common_ram_r_w_0_miso
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_reader_rd_miso.rddata, 1); -- common_ram_r_w_0_miso
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= TO_UINT(bin_reader_rd_miso.rddata) + 1; -- common_ram_r_w_0_miso
- dbg_state_string <= "val";
-
- ELSIF toggle_detect_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w);
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= prev_prev_wrdata+1;
- dbg_state_string <= "td ";
-
- ELSIF rd_cnt_allowed_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC( (prev_wrdata + 1), c_mem_data_w);
- nxt_prev_wrdata <= prev_wrdata + 1;
- dbg_state_string <= "r# ";
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
-
- ELSIF sync_detect_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; snk_in_p.sync (thus new adress): 1; snk_in_pp.sync (thus new adress): 1
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= 1;
- dbg_state_string <= "sd ";
-
- ELSIF same_r_w_address_pp = '1' THEN
- nxt_bin_writer_mosi.wr <= '1';
- nxt_bin_writer_mosi.wrdata <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);
- nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
- nxt_prev_wrdata <= prev_prev_prev_wrdata + 1;
- dbg_state_string <= "srw";
- END IF;
- END PROCESS;
-
- p_prev_wrdata : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi.wr) IS --seperated from p_bin_writer_mosi since the implementation was unwanted
- BEGIN
- IF dp_rst = '1' THEN
- prev_wrdata <= 0;
- prev_prev_wrdata <= 0;
- prev_prev_prev_wrdata <= 0;
- ELSIF nxt_bin_writer_mosi.wr='1' AND RISING_EDGE(dp_clk) THEN
- prev_wrdata <= nxt_prev_wrdata;
- prev_prev_wrdata <= prev_wrdata;
- prev_prev_prev_wrdata <= prev_prev_wrdata;
- END IF;
- END PROCESS;
-
- p_bin_writer_mosi : PROCESS(dp_clk, dp_rst) IS --, nxt_bin_writer_mosi, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata
- BEGIN
- IF dp_rst = '1' THEN
- bin_writer_mosi <= c_mem_mosi_rst;
--- prev_wrdata <= 0;
--- prev_prev_wrdata <= 0;
--- prev_prev_prev_wrdata <= 0;
- ELSIF RISING_EDGE(dp_clk) THEN
- bin_writer_mosi <= nxt_bin_writer_mosi;
--- IF nxt_bin_writer_mosi.wr = '1' THEN
--- prev_wrdata <= nxt_prev_wrdata;
--- prev_prev_wrdata<= prev_wrdata;
--- prev_prev_prev_wrdata <= prev_prev_wrdata;
--- END IF;
- END IF;
- END PROCESS;
-
-
- -----------------------------------------------------------------------------
- -- Bin Arbiter: Determine next RAM access
- -- . in : bin_reader_mosi (latency: 0)
- -- : init_phase (latency: 0)
- -- : prev_bin_reader_mosi (latency: 1)
- -- : bin_reader_mosi_pp (latency: 2)
- -- : bin_reader_mosi_ppp (latency: 3)
- -- : bin_writer_mosi (latency: 3)
- -- : sync_detect (latency: 0? or 3?
- -- : common_ram_r_w_0_miso (latency: 2)
- -- . out : bin_arbiter_rd_mosi (latency: 1)
- -- . : bin_arbiter_rd_miso (latency: 2)
- -- . : bin_arbiter_wr_mosi (latency: 4)
- -----------------------------------------------------------------------------
- nxt_bin_arbiter_wr_mosi <= bin_writer_mosi;
- -- Read RAM when subsequent addresses are not the same, when there is no toggle detected and only when the same address is not going to be written to. When a sync is detected don't read in the old RAM block.
- nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address
- AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) AND sync_detect='0')
- OR (init_phase = '1') ELSE '0';
- nxt_bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
-
- p_bin_arbiter_mosi : PROCESS(dp_clk, dp_rst) IS --, nxt_bin_arbiter_wr_mosi, nxt_bin_arbiter_rd_mosi
- BEGIN
- IF dp_rst = '1' THEN
- bin_arbiter_wr_mosi <= c_mem_mosi_rst;
- bin_arbiter_rd_mosi <= c_mem_mosi_rst;
- ELSIF RISING_EDGE(dp_clk) THEN
- bin_arbiter_wr_mosi <= nxt_bin_arbiter_wr_mosi;
- bin_arbiter_rd_mosi <= nxt_bin_arbiter_rd_mosi;
- END IF;
- END PROCESS;
-
- -- Temporary debug data
- ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
-
- -- Make RAM data available for the bin_reader (or bin_writer)
- bin_arbiter_rd_miso <= common_ram_r_w_0_miso;
-
-
- -----------------------------------------------------------------------------
- -- RAM that contains the bins
- -- . in : bin_arbiter_wr_mosi (latency: 4)
- -- . in : bin_arbiter_rd_mosi (latency: 1)
- -- . out : common_ram_r_w_0_miso (latency: 2)
- -----------------------------------------------------------------------------
- common_ram_r_w_0: ENTITY common_lib.common_ram_r_w
- GENERIC MAP (
- g_technology => c_tech_select_default,
- g_ram => c_ram,
- g_init_file => "UNUSED"
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- clken => '1',
- wr_en => bin_arbiter_wr_mosi.wr,
- wr_adr => bin_arbiter_wr_mosi.address(c_adr_w-1 DOWNTO 0),
- wr_dat => bin_arbiter_wr_mosi.wrdata(c_word_w-1 DOWNTO 0),
- rd_en => bin_arbiter_rd_mosi.rd,
- rd_adr => bin_arbiter_rd_mosi.address(c_adr_w-1 DOWNTO 0),
- rd_dat => common_ram_r_w_0_miso.rddata(c_word_w-1 DOWNTO 0),
- rd_val => common_ram_r_w_0_miso.rdval
- );
-
-
-
-END rtl;
-
diff --git a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
index 94b5895787d93f9e24bba470440a8a18b13e70a6..9230e11503c35feb7cbe26464f04d10776d48d51 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
@@ -18,98 +18,186 @@
--
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
---
--- Author: J.W.E. Oudman
--- Purpose: Provide MM slave register for st_histogram
--- Description:
--- Because the st_histogram component uses 2 RAM blocks that are swapped
--- after every sync pulse, both blocks have to work in the dp clock domain
--- and the Memory Mapped bus coming out of the component consequently also
--- works in the dp clock domain.
---
--- To convert the signals to the mm clock domain the common_reg_cross_domain
--- component is used. Because the inner workings of that component is
--- dependent on some components that take time to reliably stabialize the
--- conversion takes 12 mm clock cycles before the next address may be
--- requested.
---
---
--- [Alternative: shared dual clocked RAM block]
---
---
--------------------------------------------------------------------------------
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- . Provide MM registers for st_histogram
+-- Description:
+-- . Address 0, bit 0 = RAM clear
+-- . Read : 'ram_clearing' status output of st_histogram.vhd. '1' when RAM is clearing.
+-- . Address 1 = select RAM instance to fill (read out)
+-- . Read : read back selected instance
+-- . Write: select RAM instance to fill
+-- . Address 2, bit 0 = RAM fill
+-- . Read : 'ram_filling' status. '1' right after write of ram_fill. '0' when not filling RAM (anymore).
+-- . Write: 'ram_fill ' control. '1' to fill RAM on write event.
-LIBRARY IEEE, common_lib, dp_lib;-- mm_lib, technology_lib,
+
+LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
---USE technology_lib.technology_select_pkg.ALL;
ENTITY st_histogram_reg IS
--- GENERIC (
--- g_nof_bins : NATURAL := 512; -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
--- g_str : STRING := "freq.density" -- to select output to MM bus ("frequency" or "freq.density")
--- );
+ GENERIC (
+ g_nof_instances : NATURAL
+ );
PORT (
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
-
- -- DP clocked memory bus
- mas_out_ram_mosi : OUT t_mem_mosi ;--:= c_mem_mosi_rst; -- Beware, works in dp clock domain !
- mas_in_ram_miso : IN t_mem_miso ;--:= c_mem_miso_rst; -- '' !
--- ram_st_histogram_mosi : OUT t_mem_mosi; -- Beware, works in dp clock domain !
--- ram_st_histogram_miso : IN t_mem_miso; -- '' !
-
- -- Memory Mapped
- ram_mosi : IN t_mem_mosi;
- ram_miso : OUT t_mem_miso
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ ram_clearing : IN STD_LOGIC;
+
+ ram_fill_inst : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
+ ram_fill : OUT STD_LOGIC;
+ ram_filling : IN STD_LOGIC;
+
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ reg_mosi : IN t_mem_mosi;
+ reg_miso : OUT t_mem_miso
);
END st_histogram_reg;
-ARCHITECTURE str OF st_histogram_reg IS
-
--- CONSTANT c_mm_reg : t_c_mem := (latency => 1,
--- adr_w => 1,
--- dat_w => c_word_w,
--- nof_dat => 1,
--- init_sl => g_default_value);
+ARCHITECTURE rtl OF st_histogram_reg IS
+ CONSTANT c_nof_addresses : NATURAL := 3;
+
+ CONSTANT c_mm_reg : t_c_mem := (latency => 1,
+ adr_w => ceil_log2(c_nof_addresses),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_addresses,
+ init_sl => '0');
+
+ SIGNAL mm_ram_clearing : STD_LOGIC;
+
+ SIGNAL mm_ram_fill_inst : STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
+ SIGNAL mm_ram_fill : STD_LOGIC;
+ SIGNAL mm_ram_filling : STD_LOGIC;
BEGIN
+ ------------------------------------------------------------------------------
+ -- MM register access in the mm_clk domain
+ -- . Hardcode the shared MM slave register directly in RTL instead of using
+ -- the common_reg_r_w instance. Directly using RTL is easier when the large
+ -- MM register has multiple different fields and with different read and
+ -- write options per field in one MM register.
+ ------------------------------------------------------------------------------
+ p_mm_reg : PROCESS (mm_clk, mm_rst)
+ BEGIN
+ IF mm_rst = '1' THEN
+ -- Read access
+ reg_miso <= c_mem_miso_rst;
+
+ -- Access event, register values
+ mm_ram_fill <= '0';
+ mm_ram_fill_inst <= (OTHERS=>'0');
+
+ ELSIF rising_edge(mm_clk) THEN
+ -- Read access defaults
+ reg_miso.rdval <= '0';
+
+ -- Access event defaults
+ mm_ram_fill <= '0';
+
+ -- Write access: set register value
+ IF reg_mosi.wr = '1' THEN
+ CASE TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
+ WHEN 1 =>
+ mm_ram_fill_inst <= reg_mosi.wrdata(ceil_log2(g_nof_instances)-1 DOWNTO 0);
+ WHEN 2 =>
+ mm_ram_fill <= '1';
+ WHEN OTHERS => NULL; -- unused MM addresses
+ END CASE;
+
+ -- Read access: get register value
+ ELSIF reg_mosi.rd = '1' THEN
+ reg_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
+ reg_miso.rdval <= '1'; -- c_mm_reg.latency = 1
+ CASE TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
+ WHEN 0 =>
+ -- Read RAM clearing status
+ reg_miso.rddata(0) <= mm_ram_clearing;
+ WHEN 1 =>
+ -- Read selected RAM instance to fill
+ reg_miso.rddata(ceil_log2(g_nof_instances)-1 DOWNTO 0) <= mm_ram_fill_inst;
+ WHEN 2 =>
+ -- Read RAM filling status
+ reg_miso.rddata(0) <= mm_ram_filling;
+ WHEN OTHERS => NULL; -- unused MM addresses
+ END CASE;
+ END IF;
+ END IF;
+ END PROCESS;
- u_common_reg_cross_domain_mosi_address : ENTITY common_lib.common_reg_cross_domain
+ ------------------------------------------------------------------------------
+ -- Transfer register value between mm_clk and st_clk domain.
+ -- If the function of the register ensures that the value will not be used
+ -- immediately when it was set, then the transfer between the clock domains
+ -- can be done by wires only. Otherwise if the change in register value can
+ -- have an immediate effect then the bit or word value needs to be transfered
+ -- using:
+ --
+ -- . common_async --> for single-bit level signal
+ -- . common_spulse --> for single-bit pulse signal
+ -- . common_reg_cross_domain --> for a multi-bit (a word) signal
+ --
+ -- Typically always use a crossing component for the single bit signals (to
+ -- be on the save side) and only use a crossing component for the word
+ -- signals if it is necessary (to avoid using more logic than necessary).
+ ------------------------------------------------------------------------------
+
+ -- ST --> MM
+ u_common_async_clear : ENTITY common_lib.common_async
+ GENERIC MAP (
+ g_rst_level => '0'
+ )
PORT MAP (
- in_rst => mm_rst,
- in_clk => mm_clk,
-
- in_new => ram_mosi.rd,
- in_dat => ram_mosi.address,
+ clk => mm_clk,
+ rst => mm_rst,
- out_rst => dp_rst,
- out_clk => dp_clk,
+ din => ram_clearing,
+ dout => mm_ram_clearing
+ );
+
+ u_common_async_fill : ENTITY common_lib.common_async
+ GENERIC MAP (
+ g_rst_level => '0'
+ )
+ PORT MAP (
+ clk => mm_clk,
+ rst => mm_rst,
- out_dat => mas_out_ram_mosi.address,
- out_new => mas_out_ram_mosi.rd
+ din => ram_filling,
+ dout => mm_ram_filling
);
-
- u_reg_cross_domain_miso_rddata : ENTITY common_lib.common_reg_cross_domain
+
+ u_common_spulse_fill : ENTITY common_lib.common_spulse
PORT MAP (
- in_rst => dp_rst,
- in_clk => dp_clk,
-
- in_new => mas_in_ram_miso.rdval,
- in_dat => mas_in_ram_miso.rddata,
+ in_clk => mm_clk,
+ in_rst => mm_rst,
- out_rst => mm_rst,
- out_clk => mm_clk,
+ in_pulse => mm_ram_fill,
+ in_busy => OPEN,
- out_dat => ram_miso.rddata,
- out_new => ram_miso.rdval
- );
-
-END str;
+ out_clk => dp_clk,
+ out_rst => dp_rst,
+
+ out_pulse => ram_fill
+ );
+
+ u_common_reg_cross_domain : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_clk => mm_clk,
+ in_rst => mm_rst,
+ in_dat => mm_ram_fill_inst,
+ in_done => OPEN,
+ out_clk => dp_clk,
+ out_rst => dp_rst,
+ out_dat => ram_fill_inst,
+ out_new => OPEN
+ );
+
+END rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
index c12b28090198fd721d9e5f2610f28b6db06b378e..7b67d8e2083c598fa3645c48d5ddc7032bb9869c 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
@@ -60,14 +60,15 @@ ARCHITECTURE rtl OF st_xsq_dp_to_mm IS
SIGNAL reg_sosi_info : t_dp_sosi := c_dp_sosi_rst;
SIGNAL in_sosi_rewired : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL next_page : STD_LOGIC;
BEGIN
p_in_sosi : PROCESS(in_sosi)
BEGIN
in_sosi_rewired <= in_sosi;
- in_sosi_rewired.data( g_dsp_data_w -1 DOWNTO 0) <= in_sosi.re(g_dsp_data_w-1 DOWNTO 0);
- in_sosi_rewired.data(c_nof_complex * g_dsp_data_w -1 DOWNTO 0) <= in_sosi.im(g_dsp_data_w-1 DOWNTO 0);
+ in_sosi_rewired.data( g_dsp_data_w -1 DOWNTO 0) <= in_sosi.re(g_dsp_data_w-1 DOWNTO 0);
+ in_sosi_rewired.data(c_nof_complex * g_dsp_data_w -1 DOWNTO g_dsp_data_w) <= in_sosi.im(g_dsp_data_w-1 DOWNTO 0);
END PROCESS;
u_dp_block_to_mm : ENTITY dp_lib.dp_block_to_mm
@@ -111,16 +112,19 @@ BEGIN
IF rst='1' THEN
out_sosi_info <= c_dp_sosi_rst;
reg_sosi_info <= c_dp_sosi_rst;
+ next_page <= '0';
ELSIF rising_edge(clk) THEN
IF in_sosi.sop = '1' THEN
reg_sosi_info <= in_sosi;
END IF;
IF in_sosi.eop = '1' THEN
+ next_page <= '1';
out_sosi_info <= reg_sosi_info;
out_sosi_info.eop <= '1';
out_sosi_info.err <= in_sosi.err;
ELSE
out_sosi_info <= c_dp_sosi_rst;
+ next_page <= '0';
END IF;
END IF;
END PROCESS;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
index 0327d6162cd04d63f778800b4d4b2b04422743c3..7ba4f77b717a704897571900528cc7eba1ad8d99 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
@@ -62,17 +62,17 @@ ARCHITECTURE rtl OF st_xsq_mm_to_dp IS
crosslets_index : NATURAL;
in_a_index : NATURAL;
in_b_index : NATURAL;
+ mm_mosi : t_mem_mosi;
END RECORD;
- CONSTANT c_reg_rst : t_reg := (c_dp_sosi_rst, c_dp_sosi_rst, '0', 0, 0, 0);
+ CONSTANT c_reg_rst : t_reg := (c_dp_sosi_rst, c_dp_sosi_rst, '0', 0, 0, 0, c_mem_mosi_rst);
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
- SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
BEGIN
- mm_mosi_arr <= (OTHERS => mm_mosi); -- all mosi are identical.
+ mm_mosi_arr <= (OTHERS => nxt_r.mm_mosi); -- all mosi are identical.
u_sosi : PROCESS(r, mm_miso_arr)
BEGIN
@@ -98,7 +98,7 @@ BEGIN
BEGIN
v := r;
v.out_sosi_ctrl := c_dp_sosi_rst;
- mm_mosi.rd <= '0';
+ v.mm_mosi.rd := '0';
-- initiate next block and capture in_sosi strobe
IF r.busy = '0' AND in_sosi.sop = '1' THEN
@@ -106,8 +106,8 @@ BEGIN
v.in_sosi_strobe := in_sosi;
ELSIF r.busy = '1' THEN
-- continue with block
- mm_mosi.rd <= '1';
- mm_mosi.address <= TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index
+ v.mm_mosi.rd := '1';
+ v.mm_mosi.address := TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index
-- Indices counters to select data order
IF r.in_b_index < g_nof_signal_inputs - 1 THEN
diff --git a/libraries/dsp/st/src/vhdl/st_xst.vhd b/libraries/dsp/st/src/vhdl/st_xst.vhd
index ba841158b07c5399cc8468ae5a96089e98ef9742..1a0e75770b67e3cbe3710b95062940c087bf3a82 100644
--- a/libraries/dsp/st/src/vhdl/st_xst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xst.vhd
@@ -65,18 +65,16 @@ END st_xst;
ARCHITECTURE str OF st_xst IS
- CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
- CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
- CONSTANT c_nof_word : NATURAL := g_stat_data_sz*c_nof_statistics*c_nof_complex;
- CONSTANT c_nof_word_w : NATURAL := ceil_log2(c_nof_word);
-
TYPE t_reg IS RECORD
busy : STD_LOGIC;
in_a_index : NATURAL;
in_b_index : NATURAL;
+ x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ in_a_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
END RECORD;
- CONSTANT c_reg_rst : t_reg := ('0', 0, 0);
+ CONSTANT c_reg_rst : t_reg := ('0', 0, 0, (OTHERS=>(OTHERS => '0')), (OTHERS=>(OTHERS => '0')), (OTHERS => c_dp_sosi_rst) );
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
@@ -85,8 +83,6 @@ ARCHITECTURE str OF st_xst IS
SIGNAL in_b_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL x_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
- SIGNAL reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
BEGIN
-- MM -> DP
@@ -108,20 +104,7 @@ BEGIN
-- in_b_sosi_arr = x_sosi_arr
in_b_sosi_arr <= x_sosi_arr;
-
- -- Capture x_sosi_arr(0) data
- reg_x_sosi_0_re(nxt_r.in_b_index) <= x_sosi_arr(0).re;
- reg_x_sosi_0_im(nxt_r.in_b_index) <= x_sosi_arr(0).im;
-
- -- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
- p_in_a : PROCESS(x_sosi_arr, reg_x_sosi_0_re, reg_x_sosi_0_im, nxt_r.in_a_index)
- BEGIN
- FOR I IN 0 TO g_nof_streams-1 LOOP
- in_a_sosi_arr(I) <= x_sosi_arr(0);
- in_a_sosi_arr(I).re <= reg_x_sosi_0_re(nxt_r.in_a_index);
- in_a_sosi_arr(I).im <= reg_x_sosi_0_im(nxt_r.in_a_index);
- END LOOP;
- END PROCESS;
+ in_a_sosi_arr <= nxt_r.in_a_sosi_arr;
-- Register process
p_reg : PROCESS(dp_rst, dp_clk)
@@ -133,11 +116,19 @@ BEGIN
END IF;
END PROCESS;
- -- Combinatorial process to create in_a_index and in_b_index for reoredering x_sosi_arr(0) data.
+ -- Combinatorial process to create in_a_index and in_b_index and reoredering x_sosi_arr(0) data.
p_comb : PROCESS(r, x_sosi_arr)
VARIABLE v : t_reg;
+ VARIABLE v_in_a_index : NATURAL;
+ VARIABLE v_in_b_index : NATURAL;
+ VARIABLE v_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ VARIABLE v_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
BEGIN
v := r;
+ v_in_a_index := r.in_a_index;
+ v_in_b_index := r.in_b_index;
+ v_x_sosi_0_re := r.x_sosi_0_re;
+ v_x_sosi_0_im := r.x_sosi_0_im;
-- initiate next block
IF r.busy = '0' AND x_sosi_arr(0).sop = '1' THEN
v.busy := '1';
@@ -145,22 +136,39 @@ BEGIN
ELSIF r.busy = '1' THEN
-- Indices counters to select data order
IF r.in_b_index < g_nof_signal_inputs - 1 THEN
- v.in_b_index := r.in_b_index + 1;
+ v_in_b_index := r.in_b_index + 1;
ELSE
- v.in_b_index := 0;
+ v_in_b_index := 0;
IF r.in_a_index < g_nof_signal_inputs - 1 THEN
- v.in_a_index := r.in_a_index + 1;
+ v_in_a_index := r.in_a_index + 1;
ELSE
- v.in_a_index := 0;
+ v_in_a_index := 0;
END IF;
END IF;
END IF;
-- End of block
IF x_sosi_arr(0).eop = '1' THEN
v.busy := '0';
- v.in_a_index := 0;
- v.in_b_index := 0;
+ v_in_a_index := 0;
+ v_in_b_index := 0;
END IF;
+
+ -- Capture x_sosi_arr(0) data
+ v_x_sosi_0_re(v_in_b_index) := x_sosi_arr(0).re;
+ v_x_sosi_0_im(v_in_b_index) := x_sosi_arr(0).im;
+
+ -- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ v.in_a_sosi_arr(I) := x_sosi_arr(0);
+ v.in_a_sosi_arr(I).re := v_x_sosi_0_re(v_in_a_index);
+ v.in_a_sosi_arr(I).im := v_x_sosi_0_im(v_in_a_index);
+ END LOOP;
+
+ v.in_a_index := v_in_a_index;
+ v.in_b_index := v_in_b_index;
+ v.x_sosi_0_re := v_x_sosi_0_re;
+ v.x_sosi_0_im := v_x_sosi_0_im;
+
nxt_r <= v;
END PROCESS;
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index 13bbf592e2000dc1d0336ff519d3f8050e8cdef1..23b11ddf8086194ade628fc1ec8e98d84e14d0b3 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -23,6 +23,7 @@ peripherals:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_stat_data_sz * g_nof_stat) * MM_BUS_SIZE
mm_port_description: |
"The statistics are calculated for blocks of g_nof_stat time multiplexed data streams.
There are g_nof_instances parallel time multiplexed data streams.
@@ -54,6 +55,7 @@ peripherals:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_stat_data_sz * g_nof_stat) * MM_BUS_SIZE
mm_port_description: |
"The subband statistics per PN are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of
N_sub * Q_fft = 512 * 2 = 1024 real values as:
@@ -86,6 +88,7 @@ peripherals:
# MM port for st_sst.vhd
- mm_port_name: RAM_ST_SST
mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_stat_data_sz * g_nof_stat) * MM_BUS_SIZE
mm_port_description: |
"The beamlet statistics per PN are stored in 1 block of S_sub_bf * N_pol_bf = 488 * 2 = 976 real values as:
@@ -101,3 +104,36 @@ peripherals:
mm_width: 32
user_width: g_stat_data_w
radix: uint64
+
+
+ - peripheral_name: st_xst_for_sdp # pi_st_xst.py
+ peripheral_description: |
+ "Calculate Crosslets Statistics during a sync interval for the crosslets statistics (XST) in LOFAR2.0 SDP"
+ parameters:
+ # Parameters of pi_st_xst.py, fixed in node_sdp_correlator.vhd / sdp_pkg.vhd
+ - { name: g_nof_streams, value: 9 } # P_sq
+ # Parameters of st_xst.vhd, fixed in node_sdp_correlator.vhd / sdp_pkg.vhd
+ - { name: g_nof_crosslets, value: 1 } # N_crosslets
+ - { name: g_nof_signal_inputs, value: 12 } # S_pn = 12
+ - { name: g_in_data_w, value: 16 } # W_crosslet = 16
+ - { name: g_stat_data_w, value: 64 } # W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # W_statistic_sz = 2
+ mm_ports:
+ # MM port for st_sst.vhd
+ - mm_port_name: RAM_ST_XSQ
+ mm_port_type: RAM
+ mm_port_description: |
+ "The crosslets statistics per PN are stored in 1 block of
+ g_nof_crosslets * g_nof_signal_inputs**2 * c_nof_complex * g_stat_data_sz = 1 * 12 * 12 * 2 * 2 = 576 values as:
+
+ (cint64)XST[] = (cint64)XST[crosslets][in A][in B][complex][word]"
+
+ number_of_mm_ports: 1
+ fields:
+ - - field_name: power
+ field_description: ""
+ number_of_fields: 576
+ address_offset: 0x0
+ mm_width: 32
+ user_width: g_stat_data_w
+ radix: cint64_ir
diff --git a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
index fbb57a6c0ff7b8c3037c3adad36ed70083133620..0e8fea35b4f7ce3e88e4db243d208345db39ef2a 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd
@@ -20,283 +20,231 @@
-------------------------------------------------------------------------------
--
--- Author: J.W.E. Oudman
--- Purpose: Create a histogram from the input data and present it to the MM bus
--- Description:
---
---
---
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- .
+-- ModelSim usage:
+-- . (open project, compile)
+-- . (load simulation config)
+-- . as 8
+-- . run -a
+-- Description:
+-- .
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, mm_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
-USE common_lib.tb_common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
ENTITY tb_mms_st_histogram IS
GENERIC(
- g_sync_length : NATURAL := 338;
- g_nof_sync : NATURAL := 3;
- g_data_w : NATURAL := 4;
- g_nof_bins : NATURAL := 8;
- g_nof_data : NATURAL := 338;
- g_str : STRING := "freq.density";
- g_valid_gap : BOOLEAN := FALSE;
- g_snk_in_data_sim_type : STRING := "counter" -- "counter" or "toggle"
- );
+ g_nof_sync : NATURAL := 4;
+ g_nof_instances : NATURAL := 12;
+ g_data_w : NATURAL := 14;
+ g_nof_bins : NATURAL := 512;
+ g_nof_data_per_sync : NATURAL := 40000
+ );
END tb_mms_st_histogram;
ARCHITECTURE tb OF tb_mms_st_histogram IS
-
- CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins);
-
- CONSTANT c_mm_init_time : NATURAL := 5;
- CONSTANT c_dp_inti_time : NATURAL := 5;
-
- SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL first_sync : STD_LOGIC := '0';
-
- ----------------------------------------------------------------------------
+
+ ---------------------------------------------------------------------------
-- Clocks and resets
- ----------------------------------------------------------------------------
- CONSTANT c_mm_clk_period : TIME := 20 ns;
- CONSTANT c_dp_clk_period : TIME := 5 ns;
+ ---------------------------------------------------------------------------
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+ CONSTANT c_mm_clk_period : TIME := 20 ns;
+ SIGNAL dp_clk : STD_LOGIC := '1';
+ SIGNAL dp_rst : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC := '1';
- SIGNAL mm_clk : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '1';
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL dp_rst : STD_LOGIC;
- SIGNAL dp_clk : STD_LOGIC := '1';
-
-
-
-
----------------------------------------------------------------------------
- -- Streaming Input
+ -- stimuli
----------------------------------------------------------------------------
-
- SIGNAL st_histogram_snk_in : t_dp_sosi;
-
+ SIGNAL stimuli_en : STD_LOGIC := '1';
+
+ SIGNAL stimuli_src_out : t_dp_sosi;
+ SIGNAL stimuli_src_in : t_dp_siso;
+
----------------------------------------------------------------------------
- -- Memory Mapped Input
+ -- st_histogram
----------------------------------------------------------------------------
-
- SIGNAL st_histogram_ram_mosi : t_mem_mosi;
- SIGNAL st_histogram_ram_miso : t_mem_miso;
-
-
+ SIGNAL st_histogram_snk_in_arr : t_dp_sosi_arr(g_nof_instances-1 DOWNTO 0);
+
+ SIGNAL st_histogram_reg_mosi : t_mem_mosi;
+ SIGNAL st_histogram_reg_miso : t_mem_miso;
+
+ SIGNAL st_histogram_ram_mosi : t_mem_mosi;
+ SIGNAL st_histogram_ram_miso : t_mem_miso;
+
+
+ ----------------------------------------------------------------------------
+ -- Readout & verification
+ ----------------------------------------------------------------------------
+ CONSTANT c_ram_dat_w : NATURAL := ceil_log2(g_nof_data_per_sync)+1;
+
+ CONSTANT c_expected_ram_content : NATURAL := g_nof_data_per_sync/g_nof_bins;
+
+ SIGNAL ram_filling : STD_LOGIC;
+
+ SIGNAL ram_rd_word : STD_LOGIC_VECTOR(c_ram_dat_w-1 DOWNTO 0);
+ SIGNAL ram_rd_word_int : NATURAL;
+ SIGNAL ram_rd_word_valid : STD_LOGIC;
+ SIGNAL nxt_ram_rd_word_valid : STD_LOGIC;
+
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
+ dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*10;
+
mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
- mm_rst <= '1', '0' AFTER c_mm_clk_period*c_mm_init_time;
+ mm_rst <= '1', '0' AFTER c_mm_clk_period*10;
+
- dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
- dp_rst <= '1', '0' AFTER c_dp_clk_period*c_dp_inti_time;
-
-
-
-
- ----------------------------------------------------------------------------
- -- Source: counter stimuli
- ----------------------------------------------------------------------------
-
- p_data : PROCESS(dp_rst, dp_clk, st_histogram_snk_in)
- BEGIN
- IF g_snk_in_data_sim_type = "counter" THEN
- IF dp_rst='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
- ELSIF rising_edge(dp_clk) AND st_histogram_snk_in.valid='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), 1);
- END IF;
- ELSIF g_snk_in_data_sim_type = "toggle" THEN
- IF dp_rst='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
- ELSIF rising_edge(dp_clk) AND st_histogram_snk_in.valid='1' THEN
- IF st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) = TO_UVEC(0, g_data_w) THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= TO_UVEC(1, g_data_w);
- ELSE
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= TO_UVEC(0, g_data_w);
- END IF;
- END IF;
- END IF;
- END PROCESS;
-
- p_stimuli : PROCESS
- BEGIN
- IF g_valid_gap = FALSE THEN
--- dp_rst <= '1';
- st_histogram_snk_in.sync <= '0';
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
--- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
--- dp_rst <= '0';
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- st_histogram_snk_in.valid <= '1';
-
-
- FOR I IN 0 TO g_nof_sync-1 LOOP
- st_histogram_snk_in.sync <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.sync <= '0';
- FOR I IN 0 TO g_sync_length-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
-
- END LOOP;
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- tb_end <= '1';
- WAIT;
-
- ELSIF g_valid_gap = TRUE THEN
--- dp_rst <= '1';
- st_histogram_snk_in.sync <= '0';
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
--- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
--- dp_rst <= '0';
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- st_histogram_snk_in.valid <= '1';
-
-
- FOR I IN 0 TO g_nof_sync-2 LOOP
- st_histogram_snk_in.sync <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.sync <= '0';
- FOR I IN 0 TO (g_sync_length/2)-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- --WAIT UNTIL rising_edge(dp_clk);
- --WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.valid <= '1';
- FOR I IN 0 TO (g_sync_length/4)-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- --st_histogram_snk_in.valid <= '0';
- st_histogram_snk_in.sync <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.valid <= '1';
- st_histogram_snk_in.sync <= '0';
- FOR I IN 0 TO (g_sync_length/4)-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
-
- END LOOP;
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- tb_end <= '1';
- WAIT;
- END IF;
- END PROCESS;
-
----------------------------------------------------------------------------
- -- Source: read MM bus stimuli
- ----------------------------------------------------------------------------
-
--- p_mm_stimuli : PROCESS --(st_histogram_snk_in.sync)
--- BEGIN
--- IF mm_rst='1' THEN
--- st_histogram_ram_mosi <= c_mem_mosi_rst; --.address(c_adr_w-1 DOWNTO 0) <= (OTHERS=>'0');
----- ELSIF rising_edge(mm_clk) THEN --AND st_histogram_snk_in.valid='1'
--- ELSE
--- IF first_sync = '0' THEN
--- WAIT UNTIL st_histogram_snk_in.sync = '1';
--- first_sync <= '1';
--- -- wait till one RAM block is written
--- FOR I IN 0 TO (g_sync_length/4) LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
--- -- wait for some more cycles
--- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
----- ELSIF rising_edge(mm_clk) THEN
--- ELSE
--- FOR I IN 0 TO g_nof_bins-1
--- --
--- st_histogram_ram_mosi.rd <= '1';
--- st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0), 1);
--- END IF;
--- END IF;
--- END PROCESS;
-
- p_mm_stimuli : PROCESS --(st_histogram_snk_in.sync)
+ -- DP Stimuli: generate st_histogram input data
+ ----------------------------------------------------------------------------
+ stimuli_src_in <= c_dp_siso_rdy;
+
+ -- Generate g_nof_sync packets of g_nof_data_per_sync words
+ p_generate_packets : PROCESS
+ VARIABLE v_sosi : t_dp_sosi := c_dp_sosi_rst;
BEGIN
- --IF mm_rst='1' THEN
- st_histogram_ram_mosi <= c_mem_mosi_rst; --.address(c_adr_w-1 DOWNTO 0) <= (OTHERS=>'0');
--- ELSIF rising_edge(mm_clk) THEN --AND st_histogram_snk_in.valid='1'
- --ELSE
- --IF first_sync = '0' THEN
- WAIT UNTIL st_histogram_snk_in.sync = '1';
- --first_sync <= '1';
- -- wait till one RAM block is written
- FOR I IN 0 TO (g_sync_length/4) LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
- -- wait for some more cycles
- FOR I IN 0 TO 2 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
--- ELSIF rising_edge(mm_clk) THEN
- --ELSE
- FOR I IN 0 TO g_nof_bins-1 LOOP
- proc_mem_mm_bus_rd(I, mm_clk, st_histogram_ram_mosi);
- proc_common_wait_some_cycles(mm_clk, 11);
- -- miso.rddata arrives
- END LOOP;
- --
- --st_histogram_ram_mosi.rd <= '1';
- --st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_ram_mosi.address(c_adr_w-1 DOWNTO 0), 1);
- --END IF;
- --END IF;
+ stimuli_src_out <= c_dp_sosi_rst;
+ proc_common_wait_until_low(dp_clk, dp_rst);
+ proc_common_wait_some_cycles(dp_clk, 5);
+
+ FOR I IN 0 TO g_nof_sync-1 LOOP
+ v_sosi.sync := '1';
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w-1 DOWNTO 0)); -- wrap when >= 2**g_data_w
+ proc_dp_gen_block_data(g_data_w, TO_UINT(v_sosi.data), g_nof_data_per_sync, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, stimuli_src_in, stimuli_src_out);
+ END LOOP;
+
+ proc_common_wait_some_cycles(dp_clk, 50);
+ tb_end <= '1';
+ WAIT;
END PROCESS;
-
--- -- Read data request to the MM bus
--- -- Use proc_mem_mm_bus_rd_latency() to wait for the MM MISO rd_data signal
--- -- to show the data after some read latency
--- PROCEDURE proc_mem_mm_bus_rd(CONSTANT rd_addr : IN NATURAL;
--- SIGNAL mm_clk : IN STD_LOGIC;
--- SIGNAL mm_miso : IN t_mem_miso;
--- SIGNAL mm_mosi : OUT t_mem_mosi) IS
--- BEGIN
--- mm_mosi.address <= TO_MEM_ADDRESS(rd_addr);
--- proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.rd);
--- END proc_mem_mm_bus_rd;
-
----- Issues a rd or a wr MM access and wait for it to have finished
--- PROCEDURE proc_mm_access(SIGNAL mm_clk : IN STD_LOGIC;
--- SIGNAL mm_waitreq : IN STD_LOGIC;
--- SIGNAL mm_access : OUT STD_LOGIC) IS
--- BEGIN
--- mm_access <= '1';
--- WAIT UNTIL rising_edge(mm_clk);
--- WHILE mm_waitreq='1' LOOP
--- WAIT UNTIL rising_edge(mm_clk);
--- END LOOP;
--- mm_access <= '0';
--- END proc_mm_access;
-
--- proc_mem_mm_bus_rd(0, mm_clk, mm_mosi); -- Read nof_early_syncs
--- proc_common_wait_some_cycles(mm_clk, 1);
--- mm_nof_early_syncs <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
-
+
----------------------------------------------------------------------------
- -- DUT: Device Under Test
+ -- mms_st_histogram
----------------------------------------------------------------------------
-
+ gen_snk_in_arr: FOR i IN 0 TO g_nof_instances-1 GENERATE
+ st_histogram_snk_in_arr(i) <= stimuli_src_out;
+ END GENERATE;
+
u_mms_st_histogram : ENTITY work.mms_st_histogram
GENERIC MAP(
- g_in_data_w => g_data_w,
- g_nof_bins => g_nof_bins,
- g_nof_data => g_nof_data,
- g_str => g_str
+ g_nof_instances => g_nof_instances,
+ g_data_w => g_data_w,
+ g_nof_bins => g_nof_bins,
+ g_nof_data_per_sync => g_nof_data_per_sync
)
PORT MAP (
+ dp_clk => dp_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk,
+
+ mm_clk => mm_clk,
mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- Streaming
- snk_in => st_histogram_snk_in,
-
- -- Memory Mapped
+
+ snk_in_arr => st_histogram_snk_in_arr,
+
+ reg_mosi => st_histogram_reg_mosi,
+ reg_miso => st_histogram_reg_miso,
+
ram_mosi => st_histogram_ram_mosi,
- ram_miso => st_histogram_ram_miso --OPEN
+ ram_miso => st_histogram_ram_miso
);
-
+
+
+ ----------------------------------------------------------------------------
+ -- MM Readout of st_histogram instances
+ ----------------------------------------------------------------------------
+ p_ram_clear : PROCESS
+ BEGIN
+ st_histogram_ram_mosi <= c_mem_mosi_rst;
+ st_histogram_reg_mosi <= c_mem_mosi_rst;
+ ram_filling <= '0';
+ ram_rd_word <= (OTHERS=>'0');
+ -- The first sync indicates start of incoming data - let it pass
+ proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
+ proc_common_wait_some_cycles(mm_clk, 10);
+ FOR i IN 0 TO g_nof_sync-2 LOOP
+ -- Wiat for a full sync period of data
+ proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
+ -- The sync has passed, we can start reading the resulting histogram
+ FOR j IN 0 TO g_nof_instances-1 LOOP
+ -- Select st_histogram instance to read out
+ proc_mem_mm_bus_wr(1, j, mm_clk, st_histogram_reg_mosi);
+ proc_common_wait_some_cycles(mm_clk, 2);
+
+ -- Enable RAM filling
+ proc_mem_mm_bus_wr(2, 1, mm_clk, st_histogram_reg_mosi);
+ proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- Wait until RAM filling is done
+ proc_mem_mm_bus_rd(2, mm_clk, st_histogram_reg_mosi);
+ ram_filling <= st_histogram_reg_miso.rddata(0);
+ proc_common_wait_some_cycles(mm_clk, 2);
+ WHILE ram_filling='1' LOOP
+ -- Read filling status
+ proc_mem_mm_bus_rd(2, mm_clk, st_histogram_reg_mosi);
+ ram_filling <= st_histogram_reg_miso.rddata(0);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ END LOOP;
+
+ -- Read out the RAM contents
+ FOR k IN 0 TO g_nof_bins-1 LOOP
+ proc_mem_mm_bus_rd(k, mm_clk, st_histogram_ram_mosi);
+ ram_rd_word <= st_histogram_ram_miso.rddata(c_ram_dat_w-1 DOWNTO 0);
+ ram_rd_word_int <= TO_UINT(ram_rd_word);
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ END PROCESS;
+
+ -- Register st_histogram_ram_miso.rdval so we read only valid data
+ p_nxt_ram_rd_word_valid : PROCESS(mm_rst, mm_clk)
+ BEGIN
+ IF mm_rst = '1' THEN
+ ram_rd_word_valid <= '0';
+ ELSIF RISING_EDGE(mm_clk) THEN
+ ram_rd_word_valid <= nxt_ram_rd_word_valid;
+ END IF;
+ END PROCESS;
+ nxt_ram_rd_word_valid <= st_histogram_ram_miso.rdval;
+
+
+ ----------------------------------------------------------------------------
+ -- Perform verification of ram_rd_word when ram_rd_word_valid
+ ----------------------------------------------------------------------------
+ p_verify_assert : PROCESS
+ BEGIN
+ FOR i IN 0 TO g_nof_sync-1 LOOP
+ proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
+ proc_common_wait_until_high(dp_clk, ram_rd_word_valid);
+ IF i=0 THEN -- Sync period 0: we expect RAM to contain zeros
+ ASSERT ram_rd_word_int=0 REPORT "RAM contains wrong bin count (expected 0, actual " & INTEGER'IMAGE(ram_rd_word_int) & ")" SEVERITY ERROR;
+ ELSE -- Sync period 1 onwards
+ ASSERT ram_rd_word_int=c_expected_ram_content REPORT "RAM contains wrong bin count (expected " & INTEGER'IMAGE(c_expected_ram_content) & ", actual " & INTEGER'IMAGE(ram_rd_word_int) & ")" SEVERITY ERROR;
+ END IF;
+ END LOOP;
+ WAIT FOR 5 ns;
+ END PROCESS;
+
+
END tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index faad666ee4410b764b11291d621bd29abdc68728..6b4d3eeadd9b5807ab58e9ae606dcd72d3df91c7 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -20,521 +20,201 @@
-------------------------------------------------------------------------------
--
--- Author: J.W.E. Oudman
--- Purpose: Testing the st_histogram component on it's pecularities
--- Description:
--- The st_histogram component is mainly about saving counter data and
--- making the saved data available for the MM master. The working of the
--- RAM blocks has a big influence on this. That is why the testbench is made
--- to generate data that can make related problems with that vissible.
---
--- To know if there can constantly new data be witten to the RAM blocks
--- a counter would be sufficient.
---
--- Because there is a delay between requesting and writing back of data of
--- 3 cycles and it is illegal to read and write on the same adres at the
--- same time, there are 2 special situations that can happen. One where the
--- addresses can toggle (e.g. 0; 1; 0; 1) and one where a simultanious read
--- and write are triggered (e.g. 0; 1; 1; 0). Both would cause incorrect
--- counting as the address count can't be updated (written) before it's
--- address is requested again. Due to this the counter in st_histogram can
--- not be a simple counter that only counts and compares on repeating
--- addresses. It also has to compare on 2 and 3 cycles back - which makes
--- it complicated enough that it requires additional test stimuli.
--- To simulate with the required stimuli the g_snk_in_data_sim_type can be
--- set to 'counter', 'toggle', 'same rw' or a 'mix' of it.
---
--- Only incoming data while snk_in.valid = '1' may be counted. To keep the
--- simulation simple there is the option to let there be some gap's in the
--- valid data (or not) where snk_in.valid = '0' by setting the g_valid_gap
--- to 'true', 'false' or 'custom'.
---
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- . Generate st_histogram input data, verify RAM contents. TB is self checking.
+-- ModelSim usage:
+-- . (open project, compile)
+-- . (load simulation config)
+-- . as 8
+-- . run -a
+-- Description:
+-- . Verification be eye (wave window) - observe that:
+-- . There are 4 sync periods in which 3 packets of 1024 words are generated;
+-- . histogram_snk_in.data = 0..1023, 3 times per sync
+-- . st_histogram has 256 bins so uses the 8 MS bits of snk_in.data
+-- . st_histogram will count 4*0..255 instead of 0..1023 per packet
+-- . st_histogram will count 12 occurences (3 packets * 4 * 0..255) per sync.
+-- . bin_writer_mosi writes bin counts 1..12 per sync interval;
+-- . Both RAMs are used twice: RAM 0, RAM 1, RAM 0, RAM 1;
+-- . RAM clearing completes just before the end of each sync interval.
+-- . Automatic verification:
+-- . In each sync period the RAM contents are read out via ram_mosi/miso and
+-- compared to the expected bin counts.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, mm_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL; -- needed by TO_UNSIGNED
+USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
ENTITY tb_st_histogram IS
GENERIC(
- g_sync_length : NATURAL := 200;
- g_nof_sync : NATURAL := 3;
- g_data_w : NATURAL := 4; --4 ; 1
- g_nof_bins : NATURAL := 8; --8 ; 2
- g_nof_data : NATURAL := 200;
- --g_str : STRING := "freq.density";
- g_valid_gap : STRING := "custom"; -- "false" or "true" or "custom" --BOOLEAN := TRUE
- g_snk_in_data_sim_type : STRING := "same rw" -- "counter" or "toggle" or "same rw" or "mix"
+ g_nof_sync : NATURAL := 4; -- We're simulating at least 4 g_nof_sync so both RAMs are written and cleared twice.
+ g_data_w : NATURAL := 8; -- Determines maximum number of bins (2^g_data_w)
+ g_nof_bins : NATURAL := 256; -- Lower than or equal to 2^g_data_w. Higher is allowed but makes no sense.
+ g_nof_data_per_sync : NATURAL := 1024 -- Determines max required RAM data width. e.g. 11b to store max bin count '1024'.
);
END tb_st_histogram;
ARCHITECTURE tb OF tb_st_histogram IS
-
- CONSTANT c_adr_w : NATURAL := ceil_log2(g_nof_bins);
- CONSTANT c_adr_low_calc : INTEGER := g_data_w-c_adr_w; -- Calculation might yield a negative number
- CONSTANT c_adr_low : NATURAL := largest(0, c_adr_low_calc); -- Override any negative value of c_adr_low_calc
- --SIGNAL position : INTEGER range g_data_w'RANGE;
- CONSTANT c_dp_inti_time : NATURAL := 5;
-
- SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL pre_valid : STD_LOGIC := '0';
- SIGNAL prev_unvalid : STD_LOGIC := '0';
- SIGNAL init_phase : STD_LOGIC := '1';
- SIGNAL toggle_start : STD_LOGIC := '0';
- SIGNAL pre_sync : STD_LOGIC := '0';
-
-
- ----------------------------------------------------------------------------
- -- Same read write test stimuli
- ----------------------------------------------------------------------------
- TYPE t_srw_arr IS ARRAY (NATURAL RANGE <>) OF INTEGER;
- CONSTANT c_srw_arr : t_srw_arr := (0,0,1,1,0,0,1,2,3, 1, 2, 3, 0, 3, 3, 0, 3);
- -- 1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
- --0:1.2. 3.4. 05. 06.
- --1: 1.2. 3. 04.
- --2: 1. 02.
- --3: 1. 02. 03.04. 05.
- --srw: x. x. x. x. x. x. x. u.
-
- SIGNAL srw_index_cnt : NATURAL := 0;
-
-
- ----------------------------------------------------------------------------
- -- Valid stimuli
- ----------------------------------------------------------------------------
- TYPE t_val_arr IS ARRAY (NATURAL RANGE <>) OF INTEGER;
- CONSTANT c_val_arr : t_val_arr := (1,1,1,1,0,1,1,1,1, 1, 1, 1, 1, 0, 1, 1, 1);
- -- 1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
-
- SIGNAL val_index_cnt : NATURAL := 0;
- SIGNAL dbg_valid : NATURAL;
-
-
- ----------------------------------------------------------------------------
+ ---------------------------------------------------------------------------
+ -- Constants derived from generics
+ ---------------------------------------------------------------------------
+ CONSTANT c_expected_ram_content : NATURAL := g_nof_data_per_sync/g_nof_bins;
+
+ CONSTANT c_ram_dat_w : NATURAL := ceil_log2(g_nof_data_per_sync)+1;
+
+ ---------------------------------------------------------------------------
-- Clocks and resets
- ----------------------------------------------------------------------------
+ ---------------------------------------------------------------------------
CONSTANT c_dp_clk_period : TIME := 5 ns;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '1';
-
-
-
-
- ----------------------------------------------------------------------------
- -- Streaming Input
- ----------------------------------------------------------------------------
-
- SIGNAL st_histogram_snk_in : t_dp_sosi;
-
-
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+
----------------------------------------------------------------------------
- -- Streaming Output
+ -- stimuli
----------------------------------------------------------------------------
-
- SIGNAL st_histogram_ram_miso : t_mem_miso;
- SIGNAL st_histogram_dbg_ram_miso : t_mem_miso;
-
-
+ SIGNAL stimuli_en : STD_LOGIC := '1';
+
+ SIGNAL stimuli_src_out : t_dp_sosi;
+ SIGNAL stimuli_src_in : t_dp_siso;
+
----------------------------------------------------------------------------
- -- Self check array
+ -- st_histogram
----------------------------------------------------------------------------
- TYPE t_data_check_arr IS ARRAY (0 TO g_nof_bins) OF INTEGER;
- SIGNAL data_check_arr : t_data_check_arr := (OTHERS=> 0);
-
- SIGNAL check_adr : NATURAL := 0;
- SIGNAL prev_check_adr : NATURAL;
- SIGNAL nxt_check_arr_cnt : NATURAL;
-
- SIGNAL st_histogram_snk_in_ppp : t_dp_sosi;
- SIGNAL st_histogram_snk_in_pppp: t_dp_sosi;
--- SIGNAL dbg_check_adr :STD_LOGIC_VECTOR(g_data_w-1 DOWNTO c_adr_low); -- : NATURAL;
-
- SIGNAL dbg_error_location : STD_LOGIC;
- SIGNAL error_cnt : NATURAL;
- SIGNAL dbg_int_data_miso : NATURAL;
- SIGNAL dbg_int_data_arr : NATURAL;
-
+ SIGNAL st_histogram_snk_in : t_dp_sosi;
+ SIGNAL st_histogram_ram_mosi : t_mem_mosi;
+ SIGNAL st_histogram_ram_miso : t_mem_miso;
+ ----------------------------------------------------------------------------
+ -- Automatic verification of RAM readout
+ ----------------------------------------------------------------------------
+ SIGNAL ram_rd_word : STD_LOGIC_VECTOR(c_ram_dat_w-1 DOWNTO 0);
+ SIGNAL ram_rd_word_int : NATURAL;
+ SIGNAL ram_rd_word_valid : STD_LOGIC;
+ SIGNAL nxt_ram_rd_word_valid : STD_LOGIC;
+
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
- dp_rst <= '1', '0' AFTER c_dp_clk_period*c_dp_inti_time;
-
-
-
-
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*10;
+
+
----------------------------------------------------------------------------
- -- Source: stimuli
- -- st_histogram_snk_in.data counter or toggle or same_rw stimuli
- -- .valid with or without gap's in valid stimuli
- -- .sync sync stimuli
+ -- Stimuli: generate st_histogram input data and clear the RAM
----------------------------------------------------------------------------
-
- init_phase <= '0' WHEN st_histogram_snk_in.sync = '1';
+ stimuli_src_in <= c_dp_siso_rdy;
- p_data : PROCESS(dp_rst, dp_clk, st_histogram_snk_in)
- BEGIN
- IF g_snk_in_data_sim_type = "counter" THEN
- IF dp_rst='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
- ELSIF rising_edge(dp_clk) AND pre_valid='1' THEN -- st_histogram_snk_in.valid='1' THEN -- maybe needs init_cnt_start = '1' instead?
- IF prev_unvalid = '0' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), 1);
- ELSIF prev_unvalid = '1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), -1);
- prev_unvalid <= '0';
- END IF;
- ELSIF rising_edge(dp_clk) AND pre_valid='0' AND init_phase='0' THEN -- st_histogram_snk_in.valid='0' AND init_phase = '0' THEN
- IF prev_unvalid = '0' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), 2);
- prev_unvalid <= '1';
- END IF;
- END IF;
-
- ELSIF g_snk_in_data_sim_type = "toggle" THEN
- IF dp_rst='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
- ELSIF rising_edge(dp_clk) AND st_histogram_snk_in.valid='1' THEN -- maybe needs init_cnt_start = '1' instead?
- IF st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) = TO_UVEC(0, g_data_w) THEN -- c_adr_low
- st_histogram_snk_in.data(c_adr_low) <= '1'; -- TO_UVEC(1, g_data_w); --g_data_w-1 DOWNTO 0
- ELSE
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= TO_UVEC(0, g_data_w);
- END IF;
- END IF;
-
- ELSIF g_snk_in_data_sim_type = "same rw" THEN
- IF dp_rst='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
- ELSIF rising_edge(dp_clk) AND pre_sync='1' THEN -- AND init_phase='0' didn't work
- st_histogram_snk_in.data(g_data_w-1 DOWNTO c_adr_low) <= TO_UVEC(c_srw_arr(srw_index_cnt), c_adr_w); --placeholder !
- IF srw_index_cnt = c_srw_arr'LENGTH -1 THEN
- srw_index_cnt <= 0;
- ELSE
- srw_index_cnt <= srw_index_cnt+1;
- END IF;
- END IF;
-
- ELSIF g_snk_in_data_sim_type = "mix" THEN
- IF toggle_start = '1' THEN
- -- toggle part
- IF dp_rst='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
- ELSIF rising_edge(dp_clk) AND st_histogram_snk_in.valid='1' THEN -- maybe needs init_cnt_start = '1' instead?
- IF st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) = TO_UVEC(0, g_data_w) THEN -- c_adr_low
- st_histogram_snk_in.data(c_adr_low) <= '1'; -- TO_UVEC(1, g_data_w); --g_data_w-1 DOWNTO 0
- ELSE
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= TO_UVEC(0, g_data_w);
- END IF;
- END IF;
- -- end toggle part
- ELSE
- -- counter part
- IF dp_rst='1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= (OTHERS=>'0');
- ELSIF rising_edge(dp_clk) AND pre_valid='1' THEN -- st_histogram_snk_in.valid='1' THEN -- maybe needs init_cnt_start = '1' instead?
- IF prev_unvalid = '0' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), 1);
- ELSIF prev_unvalid = '1' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), -1);
- prev_unvalid <= '0';
- END IF;
- ELSIF rising_edge(dp_clk) AND pre_valid='0' AND init_phase='0' THEN -- st_histogram_snk_in.valid='0' AND init_phase = '0' THEN
- IF prev_unvalid = '0' THEN
- st_histogram_snk_in.data(g_data_w-1 DOWNTO 0) <= INCR_UVEC(st_histogram_snk_in.data(g_data_w-1 DOWNTO 0), 2);
- prev_unvalid <= '1';
- END IF;
- END IF;
- -- end counter part
- END IF;
- END IF;
- END PROCESS;
-
-
- p_stimuli : PROCESS
+ -- Generate g_nof_sync packets of g_nof_data_per_sync words
+ p_generate_packets : PROCESS
+ VARIABLE v_sosi : t_dp_sosi := c_dp_sosi_rst;
BEGIN
- IF g_valid_gap = "false" THEN
-
- -- initializing
- st_histogram_snk_in.sync <= '0';
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- pre_valid <= '1';
- st_histogram_snk_in.valid <= '1';
- -- generating g_nof_sync sync pulses with g_sync_length cycles between
- FOR I IN 0 TO g_nof_sync-1 LOOP
- toggle_start <= '1';
- st_histogram_snk_in.sync <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.sync <= '0';
- proc_common_wait_some_cycles(dp_clk, 2);
- toggle_start <= '0';
- FOR I IN 0 TO g_sync_length-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; -- -4 ipv -1 ?
- END LOOP;
- -- ending
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- tb_end <= '1';
- WAIT;
-
- ELSIF g_valid_gap = "true" THEN
-
- -- initializing
- st_histogram_snk_in.sync <= '0';
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- FOR I IN 0 TO 8 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- pre_sync <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- pre_valid <= '1';
- st_histogram_snk_in.valid <= '1';
- -- generating g_nof_sync-1 sync pulses with gaps in 'valid'
- FOR I IN 0 TO g_nof_sync-2 LOOP
- toggle_start <= '1';
- st_histogram_snk_in.sync <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.sync <= '0';
- proc_common_wait_some_cycles(dp_clk, 2);
- toggle_start <= '0';
- FOR I IN 0 TO (g_sync_length/2)-5 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP; -- -5 ipv -2 ?
- pre_valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.valid <= '0';
- pre_valid <= '1'; -- gap 1 clock cycles
- WAIT UNTIL rising_edge(dp_clk);
- --WAIT UNTIL rising_edge(dp_clk); -- gap 2 clock cycles
- --WAIT UNTIL rising_edge(dp_clk); -- gap 3 clock cycles
- st_histogram_snk_in.valid <= '1';
- FOR I IN 0 TO (g_sync_length/4)-2 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- pre_valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- --st_histogram_snk_in.valid <= '0'; -- gap while sync --should not happen, impossible
- st_histogram_snk_in.sync <= '1';
- pre_valid <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.valid <= '1';
- st_histogram_snk_in.sync <= '0';
- FOR I IN 0 TO (g_sync_length/4)-1 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- END LOOP;
- -- ending
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- tb_end <= '1';
- WAIT;
-
- ELSIF g_valid_gap = "custom" THEN
-
- -- initializing
- st_histogram_snk_in.sync <= '0';
- st_histogram_snk_in.valid <= '0';
- WAIT UNTIL rising_edge(dp_clk);
- FOR I IN 0 TO 8 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- pre_sync <= '1';
- WAIT UNTIL rising_edge(dp_clk);
- pre_valid <= '1';
- -- st_histogram_snk_in.valid <= '1';
- -- generating g_nof_sync-1 sync pulses with gaps in 'valid'
- FOR I IN 0 TO g_nof_sync-2 LOOP
- toggle_start <= '1';
- st_histogram_snk_in.sync <= '1';
- st_histogram_snk_in.valid <= STD_LOGIC( TO_UNSIGNED(c_val_arr(0),1)(0) ); -- TO_UVEC(c_val_arr(0), c_adr_w); --placeholder !
- WAIT UNTIL rising_edge(dp_clk);
- st_histogram_snk_in.sync <= '0';
- FOR I IN 1 TO c_val_arr'LENGTH -1 LOOP
- st_histogram_snk_in.valid <= STD_LOGIC( TO_UNSIGNED( c_val_arr(I) ,1)(0) ); -- TO_UVEC(c_val_arr(J), c_adr_w);
- dbg_valid <= I;
- WAIT UNTIL rising_edge(dp_clk);
- END LOOP;
- proc_common_wait_some_cycles(dp_clk, (g_sync_length - (c_val_arr'LENGTH -2) )); --the -2 has to be ditched as the sync happens 2 cycles to soon
- END LOOP;
- -- ending
- FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
- tb_end <= '1';
- WAIT;
- END IF;
+ stimuli_src_out <= c_dp_sosi_rst;
+ proc_common_wait_until_low(dp_clk, dp_rst);
+ proc_common_wait_some_cycles(dp_clk, 5);
+
+ FOR I IN 0 TO g_nof_sync-1 LOOP
+ v_sosi.sync := '1';
+ v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w-1 DOWNTO 0)); -- wrap when >= 2**g_data_w
+ proc_dp_gen_block_data(g_data_w, TO_UINT(v_sosi.data), g_nof_data_per_sync, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, stimuli_src_in, stimuli_src_out);
+ END LOOP;
+
+ proc_common_wait_some_cycles(dp_clk, 50);
+ tb_end <= '1';
+ WAIT;
END PROCESS;
-
-
-
--- p_mm_stimuli : PROCESS --(st_histogram_snk_in.sync)
--- BEGIN
--- st_histogram_ram_mosi <= c_mem_mosi_rst; --.address(c_adr_w-1 DOWNTO 0) <= (OTHERS=>'0');
--- WAIT UNTIL st_histogram_snk_in.sync = '1';
--- -- wait till one RAM block is written
--- FOR I IN 0 TO (g_sync_length) LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
--- -- wait for some more cycles
--- FOR I IN 0 TO 2 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
--- -- read all bins
--- FOR I IN 0 TO g_nof_bins-1 LOOP
--- proc_mem_mm_bus_rd(I, dp_clk, st_histogram_ram_mosi);
--- proc_common_wait_some_cycles(dp_clk, 1);
--- END LOOP;
--- END PROCESS;
-
+
+
----------------------------------------------------------------------------
- -- DUT: Device Under Test
+ -- st_histogram
----------------------------------------------------------------------------
-
- u_st_histogram : ENTITY work.st_histogram --_8_april
+ st_histogram_snk_in <= stimuli_src_out;
+
+ u_st_histogram : ENTITY work.st_histogram
GENERIC MAP(
- g_in_data_w => g_data_w,
+ g_data_w => g_data_w,
g_nof_bins => g_nof_bins,
- g_nof_data => g_nof_data,
- g_ram_miso_sim_mode => FALSE -- TRUE
+ g_nof_data_per_sync => g_nof_data_per_sync
)
PORT MAP (
+ dp_clk => dp_clk,
dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Streaming
+
snk_in => st_histogram_snk_in,
- -- Memory Mapped
- sla_in_ram_mosi => c_mem_mosi_rst,-- sla_in_
- sla_out_ram_miso => st_histogram_ram_miso, --OPEN -- sla_out_
- dbg_ram_miso => st_histogram_dbg_ram_miso
+ ram_mosi => st_histogram_ram_mosi,
+ ram_miso => st_histogram_ram_miso
);
-
-
-
- ----------------------------------------------------------------------------
- -- Selfcheck:
- -- The selfcheck is done by counting the adresses created from 3 cycles
- -- delayed snk_in data into an address separated array (when in the array,
- -- the data is 4 cycles delayed). This data is used as reference for
- -- comparing it with the data written into a RAM block in st_histogram.
- -- Because the data in st_histogram is written 4 cycles later than it got
- -- in, both data are in sync and can be compared directly.
- -- When the data is valid but is not the same as the reference data the
- -- debug signal dbg_error_location becomes '1' so the location can be
- -- easily spotted in the wave window and a report is made.
+
----------------------------------------------------------------------------
-
-
- u_dp_pipeline_st_histogram_snk_in_3_cycle : ENTITY dp_lib.dp_pipeline
- GENERIC MAP (
- g_pipeline => 3 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => st_histogram_snk_in,
- src_out => st_histogram_snk_in_ppp
- );
-
- u_dp_pipeline_st_histogram_snk_in_4_cycle : ENTITY dp_lib.dp_pipeline
- GENERIC MAP (
- g_pipeline => 4 -- 0 for wires, > 0 for registers,
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => st_histogram_snk_in,
- src_out => st_histogram_snk_in_pppp
- );
-
- ---------------------------------------
- -- create address from the source data
- check_adr <= TO_UINT( st_histogram_snk_in_ppp.data(g_data_w-1 DOWNTO c_adr_low) );
--- dbg_check_adr <= st_histogram_snk_in_ppp.data(g_data_w -1 DOWNTO c_adr_low);
-
- p_prev_check_adr : PROCESS (dp_rst, dp_clk, check_adr)
+ -- Readout and verification of RAM contents
+ -- . The table below shows what RAM we are reading here ('RAM read') via the
+ -- ram_mosi/miso interface, and what the expected RAM contents are.
+ --
+ ---+-------------+-------------+----------+--------------+
+ -- | Sync period | RAM written | RAM read | RAM contents |
+ -- +-------------+-------------+----------+--------------+
+ -- | 0 | 0 | 1 | 256 * 0 |
+ -- | 1 | 1 | 0 | 256 * 12 |
+ -- | 2 | 0 | 1 | 256 * 12 |
+ -- | 3 | 1 | 0 | 256 * 12 |
+ -- +-------------+-------------+----------+--------------+
+ --
+ ----------------------------------------------------------------------------
+ -- Perform MM read and put result in ram_rd_word
+ p_verify_mm_read : PROCESS
BEGIN
- IF dp_rst='1' THEN
- prev_check_adr <= 0;
- ELSIF rising_edge(dp_clk) THEN
- prev_check_adr <= check_adr;
- END IF;
- END PROCESS;
-
- -----------------------------
- -- when valid increase array based on address
- nxt_check_arr_cnt <= data_check_arr(check_adr) + 1 WHEN st_histogram_snk_in_ppp.valid = '1' ELSE data_check_arr(check_adr);
-
-
- --------------------
- -- filling the array
- p_cumulate_testdata : PROCESS (dp_rst, dp_clk, nxt_check_arr_cnt, check_adr, st_histogram_snk_in_ppp.sync) --misses prev_check_adr
- BEGIN
- --PROCESS
- --c_data_check_arr(check_adr) <= nxt_check_arr_cnt;
- IF dp_rst='1' THEN
- data_check_arr(0 TO g_nof_bins) <= (OTHERS => 0);
- ELSIF rising_edge(dp_clk) THEN
- --data_check_arr(prev_check_adr) <= nxt_check_arr_cnt;
- data_check_arr(check_adr) <= nxt_check_arr_cnt; --old timing
- IF st_histogram_snk_in_ppp.sync='1' THEN
- data_check_arr(0 TO g_nof_bins) <= (check_adr => 1, OTHERS => 0 ); -- null except check_adr
- --
- END IF;
- END IF;
+ st_histogram_ram_mosi.wr <= '0';
+ FOR i IN 0 TO g_nof_sync-1 LOOP
+ proc_common_wait_until_high(dp_clk, stimuli_src_out.sync); -- Wait for sync
+ proc_common_wait_some_cycles(dp_clk, 10); -- give it a couple of more cycles
+ FOR j IN 0 TO g_nof_bins-1 LOOP
+ proc_mem_mm_bus_rd(j, dp_clk, st_histogram_ram_mosi);
+ ram_rd_word <= st_histogram_ram_miso.rddata(c_ram_dat_w-1 DOWNTO 0);
+ ram_rd_word_int <= TO_UINT(ram_rd_word);
+ END LOOP;
+ END LOOP;
END PROCESS;
-
- ---------------------
- -- extra dbg signals
- dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
- dbg_int_data_arr <= data_check_arr(prev_check_adr);
-
- ---------------------
- -- selftest
--- p_selfcheck : PROCESS (dp_rst, dp_clk, data_check_arr, prev_check_adr, st_histogram_dbg_ram_miso.rddata)
--- BEGIN
--- --PROCESS
--- -- compare cumulated testdata with ram_mosi
---
--- --dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
--- --dbg_int_data_arr <= data_check_arr(check_adr);
--- IF rising_edge(dp_clk) THEN
--- --dbg_error_location <= '0';
--- --dbg_int_data_miso <= TO_UINT(st_histogram_dbg_ram_miso.rddata);
--- --dbg_int_data_arr <= data_check_arr(check_adr);
--- IF data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_dbg_ram_miso.rddata) AND st_histogram_snk_in_pppp.valid='1' THEN
--- dbg_error_location <= '1';
--- REPORT "The value written to the RAM is not what it should be. See signal 'dbg_int_data_arr'. The failure concerns the bin (and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
--- error_cnt <= error_cnt + 1;
--- ELSE
--- dbg_error_location <= '0';
--- END IF;
--- END IF;
---
----- IF dp_rst='1' THEN
----- data_check_arr(0 TO g_nof_bins) <= (OTHERS => 0);
----- ELSIF rising_edge(dp_clk) THEN
----- data_check_arr(check_adr) <= nxt_check_arr_cnt;
----- END IF;
--- END PROCESS;
-
-
- -- show the location of an error after a small delay (to prevent spikes) when the data written is not the same as the reference and only when the data was initially valid. Do not allow to be triggered at the testbench end.
- dbg_error_location <= '1' AFTER c_dp_clk_period/5 WHEN ( (data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_dbg_ram_miso.rddata) ) AND st_histogram_snk_in_pppp.valid='1' AND tb_end='0' ) ELSE '0';
- ASSERT dbg_error_location='0' REPORT "The value written to the RAM is not what it should be. Comparison failed on (bin and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
-
- --error count
- p_count_total_error_cnt : PROCESS (dp_clk, dbg_error_location)
+ -- Register st_histogram_ram_miso.rdval so we read only valid ram_rd_word
+ p_nxt_ram_rd_word_valid : PROCESS(dp_rst, dp_clk)
BEGIN
- IF dp_rst='1' THEN
- error_cnt <= 0;
- ELSIF dbg_error_location='1' AND tb_end='0' AND rising_edge(dp_clk) THEN
- error_cnt <= error_cnt + 1;
+ IF dp_rst = '1' THEN
+ ram_rd_word_valid <= '0';
+ ELSIF RISING_EDGE(dp_clk) THEN
+ ram_rd_word_valid <= nxt_ram_rd_word_valid;
END IF;
END PROCESS;
+ nxt_ram_rd_word_valid <= st_histogram_ram_miso.rdval;
- p_view_total_error_cnt : PROCESS (tb_end, error_cnt)
+ -- Perform verification of ram_rd_word when ram_rd_word_valid
+ p_verify_assert : PROCESS
BEGIN
- IF tb_end='1' AND error_cnt>0 THEN
- REPORT "When comparing there were " &integer'image(error_cnt) &" cycles where the value in the RAM address was not the value expected" SEVERITY ERROR;
- END IF;
+ FOR i IN 0 TO g_nof_sync-1 LOOP
+ proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
+ proc_common_wait_until_high(dp_clk, ram_rd_word_valid);
+ IF i=0 THEN -- Sync period 0: we expect RAM to contain zeros
+ ASSERT ram_rd_word_int=0 REPORT "RAM contains wrong bin count (expected 0, actual " & INTEGER'IMAGE(ram_rd_word_int) & ")" SEVERITY ERROR;
+ ELSE -- Sync period 1 onwards
+ ASSERT ram_rd_word_int=c_expected_ram_content REPORT "RAM contains wrong bin count (expected " & INTEGER'IMAGE(c_expected_ram_content) & ", actual " & INTEGER'IMAGE(ram_rd_word_int) & ")" SEVERITY ERROR;
+ END IF;
+ END LOOP;
+ WAIT FOR 5 ns;
END PROCESS;
END tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
index 15c4f2fddae29e9d2f00dd172de76c904ecff142..12b4b26876a53513ce6aff00a12b0ab19d15f05f 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
@@ -18,12 +18,14 @@
--
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
---
--- Author: J.W.E. Oudman
+-- Author:
+-- . Daniel van der Schuur
-- Purpose:
--- Description:
--- .
+-- . Test tb_st_histogram in with several parameter sets
+-- Usage
+-- . as 8
+-- . run -all
+-- . Testbenches are self-checking
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
@@ -34,30 +36,17 @@ END tb_tb_st_histogram;
ARCHITECTURE tb OF tb_tb_st_histogram IS
SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
BEGIN
+
+-- g_nof_sync : NATURAL := 4;
+-- g_data_w : NATURAL := 8;
+-- g_nof_bins : NATURAL := 256;
+-- g_nof_data : NATURAL := 1024;
+
+u_tb_st_histogram_0 : ENTITY work.tb_st_histogram GENERIC MAP ( 7, 8, 256, 1024); -- Incoming data wraps (repeats) 1024/ 256= 4 times: Bin count = 4
+u_tb_st_histogram_1 : ENTITY work.tb_st_histogram GENERIC MAP ( 6, 10, 256, 4096); -- Incoming data wraps (repeats) 4096/ 256=16 times: Bin count = 16
+u_tb_st_histogram_2 : ENTITY work.tb_st_histogram GENERIC MAP ( 5, 12, 512, 4096); -- Incoming data wraps (repeats) 4096/ 512= 8 times: Bin count = 8
+u_tb_st_histogram_3 : ENTITY work.tb_st_histogram GENERIC MAP ( 4, 13, 1024, 8192); -- Incoming data wraps (repeats) 8192/1024= 8 times: Bin count = 8
+u_tb_st_histogram_4 : ENTITY work.tb_st_histogram GENERIC MAP (40, 6, 64, 128); -- Incoming data wraps (repeats) 128/ 64= 2 times: Bin count = 2
--- Usage
--- > as 8
--- > run -all
--- > Testbenches are self-checking
-
---
--- g_sync_length : NATURAL := 200;
--- g_nof_sync : NATURAL := 3;
--- g_data_w : NATURAL := 4;
--- g_nof_bins : NATURAL := 8;
--- g_nof_data : NATURAL := 200;
--- --g_str : STRING := "freq.density";
--- g_valid_gap : STRING := "custom"; -- "false" or "true" or "custom"
--- g_snk_in_data_sim_type : STRING := "same rw" -- "counter" or "toggle" or "same rw" or "mix"
---
-
--- do test for different number of bins
-u_tb_st_histogram_counter_nof_2 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 1, 2, 200, "true" , "counter" );
-u_tb_st_histogram_counter_nof_4 : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 2, 4, 200, "true" , "counter" );
-u_tb_st_histogram_counter : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true" , "counter" );
-
--- do tests for RAM delay issues
-u_tb_st_histogram_toggle : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "true" , "toggle" );
-u_tb_st_histogram_same_rw : ENTITY work.tb_st_histogram GENERIC MAP (200, 3, 4, 8, 200, "custom", "same rw" );
END tb;
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 67d65dac3c7cb640832ca576997c8cf46634ec0f..e63d1860dc244929c83b99be41d886fefff7c7cf 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -365,24 +365,26 @@ entity wpfb_unit_dev is
g_use_prefilter : boolean := TRUE;
g_stats_ena : boolean := TRUE; -- Enables the statistics unit
g_use_bg : boolean := FALSE;
- g_coefs_file_prefix : string := "data/coefs_wide" -- File prefix for the coefficients files.
+ g_coefs_file_prefix : string := "data/coefs_wide"; -- File prefix for the coefficients files.
+ g_restart_on_valid : boolean := TRUE
);
port (
- dp_rst : in std_logic := '0';
- dp_clk : in std_logic;
- mm_rst : in std_logic;
- mm_clk : in std_logic;
- ram_fil_coefs_mosi : in t_mem_mosi := c_mem_mosi_rst;
- ram_fil_coefs_miso : out t_mem_miso;
- ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Subband statistics registers
- ram_st_sst_miso : out t_mem_miso;
- reg_bg_ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
- reg_bg_ctrl_miso : out t_mem_miso;
- ram_bg_data_mosi : in t_mem_mosi := c_mem_mosi_rst;
- ram_bg_data_miso : out t_mem_miso;
- in_sosi_arr : in t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- fil_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- out_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0)
+ dp_rst : in std_logic := '0';
+ dp_clk : in std_logic;
+ mm_rst : in std_logic;
+ mm_clk : in std_logic;
+ ram_fil_coefs_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ ram_fil_coefs_miso : out t_mem_miso;
+ ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Subband statistics registers
+ ram_st_sst_miso : out t_mem_miso;
+ reg_bg_ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ reg_bg_ctrl_miso : out t_mem_miso;
+ ram_bg_data_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ ram_bg_data_miso : out t_mem_miso;
+ in_sosi_arr : in t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ fil_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ out_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ dp_bsn_source_restart : in std_logic := '0'
);
end entity wpfb_unit_dev;
@@ -447,13 +449,12 @@ architecture str of wpfb_unit_dev is
signal fft_out_im_arr_pipe : t_fft_slv_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
signal fft_out_val_arr : std_logic_vector(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- signal fft_out_sosi : t_dp_sosi;
- signal fft_out_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0) := (others => c_dp_sosi_rst);
-
signal pfb_out_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0) := (others => c_dp_sosi_rst);
+ signal ctrl_pfb_out_sosi : t_dp_sosi := c_dp_sosi_rst;
type reg_type is record
in_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ bsn_source_restart : STD_LOGIC;
end record;
signal r, rin : reg_type;
@@ -464,9 +465,14 @@ begin
comb : process(r, in_sosi_arr)
variable v : reg_type;
begin
- v := r;
- v.in_sosi_arr := in_sosi_arr;
- rin <= v;
+ v := r;
+ v.in_sosi_arr := in_sosi_arr;
+ IF g_restart_on_valid THEN
+ v.bsn_source_restart := (NOT r.in_sosi_arr(0).valid) AND in_sosi_arr(0).valid;
+ ELSE
+ v.bsn_source_restart := dp_bsn_source_restart;
+ END IF;
+ rin <= v;
end process comb;
regs : process(dp_clk)
@@ -620,36 +626,29 @@ begin
-- Capture input BSN at input sync and pass the captured input BSN it on to PFB output sync.
-- The FFT output valid defines PFB output sync, sop, eop.
- fft_out_sosi.sync <= r.in_sosi_arr(0).sync;
- fft_out_sosi.bsn <= r.in_sosi_arr(0).bsn;
- fft_out_sosi.valid <= fft_out_val_arr(0);
-
- wire_fft_out_sosi_arr : for I in 0 to g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 generate
- fft_out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(fft_out_re_arr(I));
- fft_out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(fft_out_im_arr(I));
- fft_out_sosi_arr(I).valid <= fft_out_val_arr(I);
- end generate;
-
- u_dp_block_gen_valid_arr : ENTITY dp_lib.dp_block_gen_valid_arr
- GENERIC MAP (
- g_nof_streams => g_wpfb.nof_wb_streams*g_wpfb.wb_factor,
- g_nof_data_per_block => c_nof_valid_per_block,
- g_nof_blk_per_sync => g_wpfb.nof_blk_per_sync,
- g_check_input_sync => false,
- g_nof_pages_bsn => 1,
- g_restore_global_bsn => true
+ u_dp_sync_recover : ENTITY dp_lib.dp_sync_recover
+ GENERIC MAP(
+ g_nof_data_per_block => c_nof_valid_per_block
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- -- Streaming sink
- snk_in => fft_out_sosi,
- snk_in_arr => fft_out_sosi_arr,
- -- Streaming source
- src_out_arr => pfb_out_sosi_arr,
- -- Control
- enable => '1'
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_sosi => r.in_sosi_arr(0),
+ recover_val => fft_out_val_arr(0),
+ restart => r.bsn_source_restart,
+ out_sosi => ctrl_pfb_out_sosi
);
+
+ wire_pfb_out_sosi_arr : for I in 0 to g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 generate
+ pfb_out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(fft_out_re_arr(I));
+ pfb_out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(fft_out_im_arr(I));
+ pfb_out_sosi_arr(I).valid <= ctrl_pfb_out_sosi.valid;
+ pfb_out_sosi_arr(I).sync <= ctrl_pfb_out_sosi.sync;
+ pfb_out_sosi_arr(I).bsn <= ctrl_pfb_out_sosi.bsn;
+ pfb_out_sosi_arr(I).sop <= ctrl_pfb_out_sosi.sop;
+ pfb_out_sosi_arr(I).eop <= ctrl_pfb_out_sosi.eop;
+ end generate;
end generate;
----------------------------------------------------------------------------
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index cc5285d65f13cb922e06d09bbee6c2fecf80c9e8..d385e8f7cfe41cbcfee9ae6e1713c7d263d71383 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -804,4 +804,4 @@ begin
out_val => open
);
-end tb;
\ No newline at end of file
+end tb;
diff --git a/libraries/io/aduh/aduh.peripheral.yaml b/libraries/io/aduh/aduh.peripheral.yaml
index 5f19809c1d61f2637f413ce97ce5adae7f62935b..24f0150d78ddbba37e7aaa590eda209944691133 100644
--- a/libraries/io/aduh/aduh.peripheral.yaml
+++ b/libraries/io/aduh/aduh.peripheral.yaml
@@ -15,24 +15,21 @@ peripherals:
# MM port for mms_aduh_monitor_arr.vhd / aduh_monitor_reg.vhd
- mm_port_name: REG_ADUH_MON
mm_port_type: REG
+ mm_port_span: 4 * MM_BUS_SIZE
mm_port_description: "Sum of samples and sample powers during a sync interval."
number_of_mm_ports: g_nof_streams
fields:
- - - field_name: mean_sum_lo
- field_description: "Mean sum[31:0] of samples during a sync interval."
+ - - field_name: mean_sum
+ field_description: "Mean sum of samples during a sync interval."
address_offset: 0x0
+ user_width: 64
+ radix: int64
access_mode: RO
- - - field_name: mean_sum_hi
- field_description: "Mean sum[63:32] of samples during a sync interval."
- address_offset: 0x4
- access_mode: RO
- - - field_name: power_sum_lo
- field_description: "Power sum[31:0] of sample powers during a sync interval."
+ - - field_name: power_sum
+ field_description: "Power sum of samples during a sync interval."
address_offset: 0x8
- access_mode: RO
- - - field_name: power_sum_hi
- field_description: "Power sum[63:32] of sample powers during a sync interval."
- address_offset: 0xC
+ user_width: 64
+ radix: int64
access_mode: RO
- peripheral_name: aduh_mon_data_buffer # pi_aduh_monitor.py
@@ -48,6 +45,7 @@ peripherals:
# MM port for mms_aduh_monitor_arr.vhd
- mm_port_name: RAM_ADUH_MON
mm_port_type: RAM
+ mm_port_span: ceil_pow2(g_buffer_nof_symbols / g_nof_symbols_per_data) * MM_BUS_SIZE
mm_port_description: "Data buffer memory, gets filled after the sync when g_buffer_use_sync = True, else after the last word was read."
number_of_mm_ports: g_nof_streams
fields:
diff --git a/libraries/io/eth/src/vhdl/eth_checksum.vhd b/libraries/io/eth/src/vhdl/eth_checksum.vhd
index bfe6208f70468f77e50c6310d951bb0b882de2d1..aead4db3f1fa2b1d8d07ca5f448bef5d9b97d09c 100644
--- a/libraries/io/eth/src/vhdl/eth_checksum.vhd
+++ b/libraries/io/eth/src/vhdl/eth_checksum.vhd
@@ -150,7 +150,7 @@ BEGIN
sum;
-- Accumulate the last carry
- last_dat <= sum(c_halfword_w-1 DOWNTO 0) + sum_cin;
+ last_dat <= sum(c_halfword_w-1 DOWNTO 0) + sum_cin + word_sum_cin; -- Also add word_sum_cin in the case that the last word has a carry.
-- Checksum is 1-complement of the sum
nxt_checksum <= NOT(STD_LOGIC_VECTOR(last_dat)) WHEN prev_in_eop_dly='1' ELSE i_checksum;