diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..55e0af625cc4394681a6002faa68592fc2d60209
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -0,0 +1,107 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_full
+hdl_library_clause_name = lofar2_unb2b_sdp_station_full_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_full.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9c68eacf0efe37d9d6c49d1945b839a57d940487
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -0,0 +1,177 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station full design
+-- Description:
+-- Unb2b version for lab testing
+-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB and BF
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_sdp_station_full IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_full";
+ g_design_note : STRING := "Lofar2 SDP station full design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers (note only 6 are used in unb2b)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (2 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ );
+END lofar2_unb2b_sdp_station_full;
+
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_full IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+ JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+ JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+ JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+ JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+ JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+ JESD204B_SERIAL_DATA(6) <= '0';
+ JESD204B_SERIAL_DATA(7) <= '0';
+ JESD204B_SERIAL_DATA(8) <= '0';
+ JESD204B_SERIAL_DATA(9) <= '0';
+ JESD204B_SERIAL_DATA(10) <= '0';
+ JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 9f8ecfbddf90215cb723d7c0cb500d708250ddba..29c92527389b90f758c4c2a15dbcb167e52cd2e5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright 2020
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -118,32 +118,9 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
CONSTANT c_lofar2_sample_clk_freq : NATURAL := c_sdp_f_adc_MHz * 10**6; -- fixed 200 MHz for LOFAR2.0 stage 1
-- 10 GbE Interface
- CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * c_quad;
- CONSTANT c_nof_qsfp_bus : NATURAL := 1;
- CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
- CONSTANT c_nof_blocks_per_packet : NATURAL := 4;
- CONSTANT c_nof_beamlets_per_block : NATURAL := c_sdp_N_pol * c_sdp_S_sub_bf;
- CONSTANT c_10GbE_block_size : NATURAL := c_nof_blocks_per_packet * c_nof_beamlets_per_block / 4; -- 4 beamlets fit in 1 64bit longword
- CONSTANT c_fifo_tx_fill : NATURAL := c_10GbE_block_size;
- CONSTANT c_fifo_tx_size : NATURAL := c_fifo_tx_fill + 11; -- Make fifo size large enough for adding header.
+ CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * c_quad;
- -- Address widths of a single MM instance
- CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
- CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
- CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
- CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
-
- --
- CONSTANT c_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
-
- -- Read only sdp_info values
- CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
- CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
-
SIGNAL gn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
- SIGNAL gn_index : NATURAL := 0;
-- System
SIGNAL cs_sim : STD_LOGIC;
@@ -319,38 +296,26 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Beamlet Subband Select
SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_ss_ss_wide_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Local BF bf weights
SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- mms_dp_scale Scale Beamlets
SIGNAL reg_bf_scale_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_bf_scale_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Data Output header fields
SIGNAL reg_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Data Output xonoff
SIGNAL reg_dp_xonoff_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_xonoff_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Statistics (BST)
SIGNAL ram_st_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_st_bst_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
----------------------------------------------
-- SST
@@ -380,20 +345,16 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Statistics Enable
SIGNAL reg_stat_enable_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_stat_enable_bst_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Statistics header info
SIGNAL reg_stat_hdr_dat_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_stat_hdr_dat_bst_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
----------------------------------------------
-- UDP Offload
----------------------------------------------
- SIGNAL udp_tx_sosi_arr : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL udp_tx_siso_arr : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
----------------------------------------------
-- 10 GbE
@@ -404,57 +365,23 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso := c_mem_miso_rst;
- ----------------------------------------------
-
- SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
-
- SIGNAL dp_bsn_source_restart : STD_LOGIC;
-
- SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
-
-- 10GbE
- SIGNAL tr_ref_clk_312 : STD_LOGIC;
- SIGNAL tr_ref_clk_156 : STD_LOGIC;
- SIGNAL tr_ref_rst_156 : STD_LOGIC;
-
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL nw_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL nw_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- SIGNAL nw_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL nw_10gbe_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-
- SIGNAL nw_10GbE_hdr_fields_in_arr : t_slv_1024_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
-
SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0);
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0);
- SIGNAL cep_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL cep_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- SIGNAL cep_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL stat_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL stat_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- SIGNAL sst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL bst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL xst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
-
- SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
-
-- QSFP LEDS
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL unb2b_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL unb2b_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL unb2b_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL unb2_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
BEGIN
@@ -723,65 +650,59 @@ BEGIN
ram_st_xsq_miso => ram_st_xsq_miso
);
- -----------------------------------------------------------------------------
- -- SDP Info register
- -----------------------------------------------------------------------------
- gn_id <= ID(c_sdp_W_gn_id-1 DOWNTO 0);
- gn_index <= TO_UINT(gn_id);
- -- derive MAC, IP and UDP Port
- cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
- cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
-
- stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
- sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
- bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & ID;
- xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & ID;
-
- u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
- PORT MAP(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
-
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
-
- -- sdp info
- sdp_info => sdp_info
- );
+ gn_id <= ID(c_sdp_W_gn_id-1 DOWNTO 0);
-----------------------------------------------------------------------------
- -- node_adc_input_and_timing (AIT)
- -- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
+ -- sdp nodes
-----------------------------------------------------------------------------
- u_ait: ENTITY lofar2_sdp_lib.node_sdp_adc_input_and_timing
- GENERIC MAP(
- g_technology => g_technology,
- g_sim => g_sim,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
+ u_sdp_station : ENTITY lofar2_sdp_lib.sdp_station
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_P_sq => c_revision_select.P_sq
)
- PORT MAP(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
+ PORT MAP (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
+ reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
+ reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
+ reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+
+ -- AIT
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
reg_dp_shiftram_miso => reg_dp_shiftram_miso,
reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
@@ -800,341 +721,75 @@ BEGIN
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart
+
+ -- FSUB
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+
+ -- SDP Info
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+
+ -- XSUB
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ -- BF
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ reg_bf_scale_mosi => reg_bf_scale_mosi,
+ reg_bf_scale_miso => reg_bf_scale_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso,
+ ram_st_bst_mosi => ram_st_bst_mosi,
+ ram_st_bst_miso => ram_st_bst_miso,
+
+ -- SST
+ reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
+ reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
+ reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+
+ -- XST
+ reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
+
+ -- BST
+ reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
+ reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
+ reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
+ reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
);
- -----------------------------------------------------------------------------
- -- node_sdp_filterbank (FSUB)
- -----------------------------------------------------------------------------
- gen_use_fsub : IF c_revision_select.use_fsub GENERATE
- u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank
- GENERIC MAP(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_sst_mosi,
- reg_enable_miso => reg_stat_enable_sst_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- node_sdp_correlator (XSUB)
- -----------------------------------------------------------------------------
- gen_use_xsub : IF c_revision_select.use_xsub GENERATE
- u_xsub : ENTITY lofar2_sdp_lib.node_sdp_correlator
- GENERIC MAP(
- g_sim => g_sim,
- g_P_sq => c_revision_select.P_sq
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
-
- xst_udp_sosi => udp_tx_sosi_arr(1),
- xst_udp_siso => udp_tx_siso_arr(1),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
-
- reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => xst_udp_src_port
- );
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- nof beamsets node_sdp_beamformers (BF)
- -----------------------------------------------------------------------------
- gen_use_bf : IF c_revision_select.use_bf GENERATE
- -- Beamformers
- gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
- u_bf : ENTITY lofar2_sdp_lib.node_sdp_beamformer
- GENERIC MAP(
- g_sim => g_sim,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => udp_tx_sosi_arr(2+ beamset_id),
- bst_udp_siso => udp_tx_siso_arr(2+ beamset_id),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_bst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_bst_miso => ram_st_bst_miso_arr(beamset_id),
- reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
- reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => cep_eth_src_mac,
- ip_src_addr => cep_ip_src_addr,
- udp_src_port => cep_udp_src_port,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => bst_udp_src_port,
-
- hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
- );
-
- END GENERATE;
-
- -- MM multiplexing
- u_mem_mux_ram_ss_ss_wide : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- PORT MAP (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
-
- u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- PORT MAP (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
- );
-
- u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- PORT MAP (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
- );
-
- u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- PORT MAP (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
-
- u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- PORT MAP (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
- );
-
- u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- PORT MAP (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
- );
-
- u_mem_mux_reg_stat_enable_bst : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
- )
- PORT MAP (
- mosi => reg_stat_enable_bst_mosi,
- miso => reg_stat_enable_bst_miso,
- mosi_arr => reg_stat_enable_bst_mosi_arr,
- miso_arr => reg_stat_enable_bst_miso_arr
- );
-
- u_mem_mux_reg_stat_hdr_dat_bst : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
- )
- PORT MAP (
- mosi => reg_stat_hdr_dat_bst_mosi,
- miso => reg_stat_hdr_dat_bst_miso,
- mosi_arr => reg_stat_hdr_dat_bst_mosi_arr,
- miso_arr => reg_stat_hdr_dat_bst_miso_arr
- );
-
- -----------------------------------------------------------------------------
- -- DP MUX
- -----------------------------------------------------------------------------
- -- Assign hdr_fields to nw_10GbE for ARP/PING functionality. Only the fields:
- -- eth_src_mac, ip_src_addr and ip_dst_addr are used. Which are identical for
- -- both beamsets.
- nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
-
- u_dp_mux : ENTITY dp_lib.dp_mux
- GENERIC MAP (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => TRUE,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), --no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) --no FIFO used but must match g_nof_input
- )
- PORT MAP (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
-
- src_out => nw_10gbe_snk_in_arr(0),
- src_in => nw_10gbe_snk_out_arr(0)
- );
-
- ---------------
- -- nw_10GbE
- ---------------
- u_nw_10GbE: ENTITY nw_10GbE_lib.nw_10GbE
- GENERIC MAP (
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_offload_streams,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size,
- g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr
-
- )
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_mac_miso => reg_nw_10GbE_mac_miso,
-
- reg_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_eth10g_miso => reg_nw_10GbE_eth10g_miso,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
-
- src_out_arr => nw_10gbe_src_out_arr,
- src_in_arr => nw_10gbe_src_in_arr,
-
- snk_out_arr => nw_10gbe_snk_out_arr,
- snk_in_arr => nw_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
- serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
-
- hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
- );
- END GENERATE;
-
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
@@ -1161,29 +816,9 @@ BEGIN
QSFP_LED => QSFP_LED
);
- ---------
- -- PLL
- ---------
- u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
- GENERIC MAP (
- g_technology => g_technology
- )
- PORT MAP (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => OPEN
- );
-
------------
-- LEDs
------------
- unb2b_board_qsfp_leds_tx_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_out_arr;
- unb2b_board_qsfp_leds_tx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_in_arr;
- unb2b_board_qsfp_leds_rx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_src_out_arr;
-
u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
@@ -1197,11 +832,9 @@ BEGIN
green_led_arr => qsfp_green_led_arr,
red_led_arr => qsfp_red_led_arr,
- tx_siso_arr => unb2b_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2b_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2b_board_qsfp_leds_rx_sosi_arr
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
);
-
-
END str;
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index c4922d48959a7f833f7a037362781c0d9727b380..3ffb4a50f6bc0119df4d202cf2ebfe4c5fd688b4 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = lofar2_sdp
hdl_library_clause_name = lofar2_sdp_lib
-hdl_lib_uses_synth = common dp wpfb rTwoSDF filter si st reorder technology mm dp diag aduh tech_jesd204b tr_10GbE
+hdl_lib_uses_synth = common dp wpfb rTwoSDF filter si st reorder technology tech_pll mm dp diag aduh tech_jesd204b nw_10GbE eth
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -19,6 +19,7 @@ synth_files =
src/vhdl/node_sdp_filterbank.vhd
src/vhdl/node_sdp_beamformer.vhd
src/vhdl/node_sdp_correlator.vhd
+ src/vhdl/sdp_station.vhd
test_bench_files =
tb/vhdl/tb_sdp_info.vhd
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 2e91a934c938690dde3903307c6b116a6be76d3d..2230fc9de38c167edaad6b14bfd35c27a28f4560 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -114,7 +114,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_marker_xst : NATURAL := 88; -- = 0x58 = 'X'
--CONSTANT c_sdp_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
- CONSTANT c_sdp_offload_time : NATURAL := 600000; .
+ CONSTANT c_sdp_offload_time : NATURAL := 600000;
-- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7c32b4775b7cd35ca1e2db4ed53382f9fe5472e6
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -0,0 +1,796 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose:
+-- Core design for Lofar2 SDP station
+-- Description:
+-- Combines sdp nodes.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE work.sdp_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+
+ENTITY sdp_station IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_arria10_e1sg;
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
+ g_bsn_nof_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M, overide for short simulation
+ g_scope_selected_subband : NATURAL := 0;
+ g_use_fsub : BOOLEAN := TRUE;
+ g_use_xsub : BOOLEAN := TRUE;
+ g_use_bf : BOOLEAN := TRUE;
+ g_P_sq : NATURAL := 1
+ );
+ PORT (
+ -- System
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC := '0';
+
+ dp_pps : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- ID
+ gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ this_bck_id : IN STD_LOGIC_VECTOR(6-1 DOWNTO 0);
+ this_chip_id : IN STD_LOGIC_VECTOR(2-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- back transceivers (Note: numbered from 0)
+ JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
+ -- Connect to the BCK_RX pins in the top wrapper
+ JESD204B_REFCLK : IN STD_LOGIC; -- Connect to BCK_REF_CLK pin in the top level wrapper
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
+
+
+ ----------------------------------------------
+ -- UDP Offload
+ ----------------------------------------------
+ udp_tx_sosi_arr : OUT t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ udp_tx_siso_arr : IN t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ ----------------------------------------------
+ -- 10 GbE
+ ----------------------------------------------
+ reg_nw_10GbE_mac_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_nw_10GbE_mac_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ reg_nw_10GbE_eth10g_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_nw_10GbE_eth10g_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- AIT
+ ----------------------------------------------
+ -- JESD
+ jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ jesd204b_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- JESD control
+ jesd_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ jesd_ctrl_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Shiftram (applies per-antenna delay)
+ reg_dp_shiftram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- bsn source
+ reg_bsn_source_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_source_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- bsn scheduler
+ reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- WG
+ reg_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- BSN MONITOR
+ reg_bsn_monitor_input_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_monitor_input_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Data buffer bsn
+ ram_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Aduh statistics monitor
+ reg_aduh_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_aduh_monitor_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- FSUB
+ ----------------------------------------------
+ -- Subband statistics
+ ram_st_sst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_sst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Spectral Inversion
+ reg_si_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_si_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Filter coefficients
+ ram_fil_coefs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_fil_coefs_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_equalizer_gains_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- DP Selector
+ reg_dp_selector_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_selector_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- SDP Info
+ ----------------------------------------------
+ reg_sdp_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_sdp_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- XSUB
+ ----------------------------------------------
+ -- dp_sync_insert_v2
+ reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_sync_insert_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- crosslets_info
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- bsn_scheduler_xsub
+ reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- st_xsq
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- BF
+ ----------------------------------------------
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_ss_ss_wide_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Local BF bf weights
+ ram_bf_weights_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_bf_weights_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bf_scale_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_xonoff_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- SST
+ ----------------------------------------------
+ -- Statistics Enable
+ reg_stat_enable_sst_mosi : IN t_mem_mosi;
+ reg_stat_enable_sst_miso : OUT t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_mosi : IN t_mem_mosi;
+ reg_stat_hdr_dat_sst_miso : OUT t_mem_miso;
+
+ ----------------------------------------------
+ -- XST
+ ----------------------------------------------
+ -- Statistics Enable
+ reg_stat_enable_xst_mosi : IN t_mem_mosi;
+ reg_stat_enable_xst_miso : OUT t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_xst_mosi : IN t_mem_mosi;
+ reg_stat_hdr_dat_xst_miso : OUT t_mem_miso;
+
+ ----------------------------------------------
+ -- BST
+ ----------------------------------------------
+ -- Statistics Enable
+ reg_stat_enable_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr : OUT STD_LOGIC_VECTOR(6 * c_quad-1 DOWNTO 0) := (OTHERS => '0');
+ unb2_board_front_io_serial_rx_arr : IN STD_LOGIC_VECTOR(6 * c_quad-1 DOWNTO 0) := (OTHERS => '0');
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr : OUT t_dp_sosi_arr(6 * c_quad-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ unb2_board_qsfp_leds_tx_siso_arr : OUT t_dp_siso_arr(6 * c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ unb2_board_qsfp_leds_rx_sosi_arr : OUT t_dp_sosi_arr(6 * c_quad-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst)
+ );
+END sdp_station;
+
+
+ARCHITECTURE str OF sdp_station IS
+
+ -- 10 GbE Interface
+ CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
+ CONSTANT c_nof_blocks_per_packet : NATURAL := 4;
+ CONSTANT c_nof_beamlets_per_block : NATURAL := c_sdp_N_pol * c_sdp_S_sub_bf;
+ CONSTANT c_10GbE_block_size : NATURAL := c_nof_blocks_per_packet * c_nof_beamlets_per_block / 4; -- 4 beamlets fit in 1 64bit longword
+ CONSTANT c_fifo_tx_fill : NATURAL := c_10GbE_block_size;
+ CONSTANT c_fifo_tx_size : NATURAL := c_fifo_tx_fill + 11; -- Make fifo size large enough for adding header.
+
+ -- Address widths of a single MM instance
+ CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
+ CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
+ CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+
+ -- Read only sdp_info values
+ CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
+ CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
+
+ SIGNAL gn_index : NATURAL := 0;
+
+ ----------------------------------------------
+ -- BF
+ ----------------------------------------------
+ -- Beamlet Subband Select
+ SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Local BF bf weights
+ SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- mms_dp_scale Scale Beamlets
+ SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Beamlet Data Output header fields
+ SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Beamlet Data Output xonoff
+ SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Beamlet Statistics (BST)
+ SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ ----------------------------------------------
+ -- BST
+ ----------------------------------------------
+ -- Statistics Enable
+ SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Statistics header info
+ SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ ----------------------------------------------
+
+ SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
+ SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+
+ SIGNAL dp_bsn_source_restart : STD_LOGIC;
+
+ SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+
+ -- 10GbE
+ SIGNAL tr_ref_clk_312 : STD_LOGIC;
+ SIGNAL tr_ref_clk_156 : STD_LOGIC;
+ SIGNAL tr_ref_rst_156 : STD_LOGIC;
+
+
+ SIGNAL nw_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL nw_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL nw_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL nw_10gbe_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ SIGNAL nw_10GbE_hdr_fields_in_arr : t_slv_1024_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+
+
+ SIGNAL cep_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL cep_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL cep_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL stat_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL stat_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL sst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL bst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL xst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+
+ SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- SDP Info register
+ -----------------------------------------------------------------------------
+ gn_index <= TO_UINT(gn_id);
+ -- derive MAC, IP and UDP Port
+ cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+ bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+ xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+
+ u_sdp_info : ENTITY work.sdp_info
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
+
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
+
+ -- sdp info
+ sdp_info => sdp_info
+ );
+
+ -----------------------------------------------------------------------------
+ -- node_adc_input_and_timing (AIT)
+ -- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
+ -----------------------------------------------------------------------------
+ u_ait: ENTITY work.node_sdp_adc_input_and_timing
+ GENERIC MAP(
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
+ )
+ PORT MAP(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart
+ );
+
+ -----------------------------------------------------------------------------
+ -- node_sdp_filterbank (FSUB)
+ -----------------------------------------------------------------------------
+ gen_use_fsub : IF g_use_fsub GENERATE
+ u_fsub : ENTITY work.node_sdp_filterbank
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_sst_mosi,
+ reg_enable_miso => reg_stat_enable_sst_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- node_sdp_correlator (XSUB)
+ -----------------------------------------------------------------------------
+ gen_use_xsub : IF g_use_xsub GENERATE
+ u_xsub : ENTITY work.node_sdp_correlator
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_P_sq => g_P_sq
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
+ );
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- nof beamsets node_sdp_beamformers (BF)
+ -----------------------------------------------------------------------------
+ gen_use_bf : IF g_use_bf GENERATE
+ -- Beamformers
+ gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
+ u_bf : ENTITY work.node_sdp_beamformer
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => udp_tx_sosi_arr(2+ beamset_id),
+ bst_udp_siso => udp_tx_siso_arr(2+ beamset_id),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_mosi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_miso_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => bst_udp_src_port,
+
+ hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ );
+
+ END GENERATE;
+
+ -- MM multiplexing
+ u_mem_mux_ram_ss_ss_wide : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ PORT MAP (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
+
+ u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ PORT MAP (
+ mosi => ram_bf_weights_mosi,
+ miso => ram_bf_weights_miso,
+ mosi_arr => ram_bf_weights_mosi_arr,
+ miso_arr => ram_bf_weights_miso_arr
+ );
+
+ u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ PORT MAP (
+ mosi => reg_bf_scale_mosi,
+ miso => reg_bf_scale_miso,
+ mosi_arr => reg_bf_scale_mosi_arr,
+ miso_arr => reg_bf_scale_miso_arr
+ );
+
+ u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ PORT MAP (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
+
+ u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ PORT MAP (
+ mosi => reg_dp_xonoff_mosi,
+ miso => reg_dp_xonoff_miso,
+ mosi_arr => reg_dp_xonoff_mosi_arr,
+ miso_arr => reg_dp_xonoff_miso_arr
+ );
+
+ u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ PORT MAP (
+ mosi => ram_st_bst_mosi,
+ miso => ram_st_bst_miso,
+ mosi_arr => ram_st_bst_mosi_arr,
+ miso_arr => ram_st_bst_miso_arr
+ );
+
+ u_mem_mux_reg_stat_enable_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
+ )
+ PORT MAP (
+ mosi => reg_stat_enable_bst_mosi,
+ miso => reg_stat_enable_bst_miso,
+ mosi_arr => reg_stat_enable_bst_mosi_arr,
+ miso_arr => reg_stat_enable_bst_miso_arr
+ );
+
+ u_mem_mux_reg_stat_hdr_dat_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
+ )
+ PORT MAP (
+ mosi => reg_stat_hdr_dat_bst_mosi,
+ miso => reg_stat_hdr_dat_bst_miso,
+ mosi_arr => reg_stat_hdr_dat_bst_mosi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_miso_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- DP MUX
+ -----------------------------------------------------------------------------
+ -- Assign hdr_fields to nw_10GbE for ARP/PING functionality. Only the fields:
+ -- eth_src_mac, ip_src_addr and ip_dst_addr are used. Which are identical for
+ -- both beamsets.
+ nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
+
+ u_dp_mux : ENTITY dp_lib.dp_mux
+ GENERIC MAP (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => TRUE,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), --no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) --no FIFO used but must match g_nof_input
+ )
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
+
+ src_out => nw_10gbe_snk_in_arr(0),
+ src_in => nw_10gbe_snk_out_arr(0)
+ );
+
+ ---------------
+ -- nw_10GbE
+ ---------------
+ u_nw_10GbE: ENTITY nw_10GbE_lib.nw_10GbE
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_offload_streams,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size,
+ g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr
+
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_nw_10GbE_mac_mosi,
+ reg_mac_miso => reg_nw_10GbE_mac_miso,
+
+ reg_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
+ reg_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+
+ src_out_arr => nw_10gbe_src_out_arr,
+ src_in_arr => nw_10gbe_src_in_arr,
+
+ snk_out_arr => nw_10gbe_snk_out_arr,
+ snk_in_arr => nw_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
+
+ hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
+ );
+ END GENERATE;
+
+ ---------
+ -- PLL
+ ---------
+ u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+ ------------
+ -- LEDs
+ ------------
+ unb2_board_qsfp_leds_tx_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_out_arr;
+ unb2_board_qsfp_leds_tx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_in_arr;
+ unb2_board_qsfp_leds_rx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_src_out_arr;
+
+
+END str;