diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5fbed189707c6bc4de62fa1af3b00b176dfb1bc5
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -0,0 +1,104 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_xsub_one
+hdl_library_clause_name = lofar2_unb2b_sdp_station_xsub_one_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_xsub_one.vhd
+
+test_bench_files =
+ tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+
+regression_test_vhdl =
+ tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_one/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..409aaeb380a0b8e09fcd0b72c0248590fd7a9320
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -0,0 +1,162 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station filterbank design
+-- Description:
+-- Unb2b version for lab testing
+-- Contains complete AIT input stage with 12 ADC streams and FSUB
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_sdp_station_xsub_one IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_xsub_one";
+ g_design_note : STRING := "Lofar2 SDP station filterbank design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers (note only 6 are used in unb2b)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (2 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ );
+END lofar2_unb2b_sdp_station_xsub_one;
+
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_xsub_one IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+ JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+ JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+ JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+ JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+ JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+ JESD204B_SERIAL_DATA(6) <= '0';
+ JESD204B_SERIAL_DATA(7) <= '0';
+ JESD204B_SERIAL_DATA(8) <= '0';
+ JESD204B_SERIAL_DATA(9) <= '0';
+ JESD204B_SERIAL_DATA(10) <= '0';
+ JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..54c38eeba048167511998e269bb29cabfa1ad421
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -0,0 +1,371 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_xsub_one using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- freq = 19.921875MHz
+-- ampl = 0.5 * 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Read subband statistics (SST) via ram_st_sst and verify with
+-- c_exp_subband_power_sp_0 at c_subband_sp_0.
+-- View sp_subband_power_0 in Wave window
+--
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_xsub_one IS
+END tb_lofar2_unb2b_sdp_station_xsub_one;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 32;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
+ CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
+ CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
+
+ -- WG
+ CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
+ CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
+
+ -- WPFB
+ CONSTANT c_nof_pfb : NATURAL := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
+ CONSTANT c_wb_leakage_bin : NATURAL := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
+ CONSTANT c_exp_sp_subband_power_ratio : REAL := 1.0/8.0; -- depends on internal WPFB quantization and FIR coefficients
+ CONSTANT c_exp_sp_subband_power_sum_ratio : REAL := c_exp_sp_subband_power_ratio; -- because all sinus power is expected in one subband
+ CONSTANT c_exp_subband_power_sp_0 : REAL := c_exp_wg_power_sp_0 * c_exp_sp_subband_power_ratio;
+
+ TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+ CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
+ CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB";
+ CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+
+ -- WG
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- WPFB
+ SIGNAL xsub_stats_arr : t_slv_64_arr(0 TO c_nof_complex * c_sdp_S_pn**2 -1);
+
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_xsub_one : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => NATURAL(c_subband_sp_0)
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_C, v_A, v_X, v_B, v_A_even, v_B_even : NATURAL; -- array indicies
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ -- wait for pps
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ ----------------------------------------------------------------------------
+ -- Enable BSN
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
+
+ ----------------------------------------------------------------------------
+ -- Crosslets Info
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, INTEGER(c_subband_sp_0), tb_clk); -- offset
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk); -- stepsize
+
+ ----------------------------------------------------------------------------
+ -- Enable WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 2, INTEGER((c_subband_sp_0+c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I*4 + 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+ END LOOP;
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ -- bsn_scheduler_xsub
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ -- Wait for enough WG data and start of sync interval
+
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ ---------------------------------------------------------------------------
+ -- Read crosslet statistics
+ ---------------------------------------------------------------------------
+ FOR I IN 0 TO c_nof_complex * 144 * 2 -1 LOOP
+ v_W := I MOD 2;
+ v_B := I / 2;
+ IF v_W=0 THEN
+ -- low part
+ mmf_mm_bus_rd(c_mm_file_ram_st_xsq, I, rd_data, tb_clk);
+ xsub_stats_arr(v_B)(31 DOWNTO 0) <= rd_data;
+ ELSE
+ -- high part
+ mmf_mm_bus_rd(c_mm_file_ram_st_xsq, I, rd_data, tb_clk);
+ xsub_stats_arr(v_B)(63 DOWNTO 32) <= rd_data;
+ END IF;
+ END LOOP;
+
+
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ ---------------------------------------------------------------------------
+ -- Verify crosslet statistics
+ ---------------------------------------------------------------------------
+ -- With all WGs having the same input all crosslets should be identical. Due to the filterbank
+ -- the two signals in the output pairs per P_pfb differ slightly, therefore 3 slightly different
+ -- correlation values are expected. 1 for each correlation between even indexed signals, 1 for
+ -- odd indexed signals and 1 for correlations between even and odd indexed signals. This is verified by
+ -- checking if these values are the same.
+ FOR I IN 0 TO c_nof_complex * c_sdp_S_pn **2 -1 LOOP
+ v_C := I MOD 2;
+ v_X := I /c_nof_complex;
+ v_A := v_X MOD c_sdp_S_pn;
+ v_B := v_X / c_sdp_S_pn;
+ v_A_even := v_A MOD 2;
+ v_B_even := v_B MOD 2;
+
+ -- Check real values of even indices
+ IF v_C=0 AND v_A_even=0 AND v_B_even=0 THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr(0)) REPORT "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check real values of odd indices
+ IF v_C=0 AND v_A_even=1 AND v_B_even=1 THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) REPORT "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check real values of even correlated with odd indices
+ IF v_C=0 AND (v_A_even=0 XOR v_B_even=0) THEN
+ ASSERT SIGNED(xsub_stats_arr(I)) = SIGNED(xsub_stats_arr(1 * c_nof_complex)) REPORT "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
+ -- Check im values of even indices
+ IF v_C=1 AND v_A_even=0 AND v_B_even=0 THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr(1))) REPORT "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check im values of odd indices
+ IF v_C=1 AND v_A_even=1 AND v_B_even=1 THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) REPORT "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check im values of even correlated with odd indices
+ IF v_C=1 AND (v_A_even=0 XOR v_B_even=0) THEN
+ ASSERT ABS(SIGNED(xsub_stats_arr(I))) = ABS(SIGNED(xsub_stats_arr(1 * c_nof_complex + 1))) REPORT "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+
+ -- Check if values are > 0
+ IF v_C=0 THEN ASSERT (SIGNED(xsub_stats_arr(I)) > TO_SIGNED(0, c_longword_w)) REPORT "correlation is 0 which is unexpected! at I = " & int_to_str(I) SEVERITY ERROR; END IF;
+ END LOOP;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 1793c7e65cbf4ca8dd410329816b608b2f1e520f..55d56fe1992e4da559138d298c64ed381341b902 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -266,7 +266,7 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------
- -- FUSB
+ -- FSUB
----------------------------------------------
-- Subband statistics
SIGNAL ram_st_sst_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -294,6 +294,25 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_sdp_info_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_sdp_info_miso : t_mem_miso := c_mem_miso_rst;
+ ----------------------------------------------
+ -- XSUB
+ ----------------------------------------------
+ -- dp_sync_insert_v2
+ SIGNAL reg_dp_sync_insert_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dp_sync_insert_v2_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- crosslets_info
+ SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- bsn_scheduler_xsub
+ SIGNAL reg_bsn_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_bsn_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+
+ -- st_xsq
+ SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+
----------------------------------------------
-- BF
----------------------------------------------
@@ -379,6 +398,8 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
+
-- 10GbE
SIGNAL tr_ref_clk_312 : STD_LOGIC;
SIGNAL tr_ref_clk_156 : STD_LOGIC;
@@ -675,7 +696,15 @@ BEGIN
reg_stat_enable_bst_1_mosi => reg_stat_enable_bst_mosi_arr(1),
reg_stat_enable_bst_1_miso => reg_stat_enable_bst_miso_arr(1),
reg_stat_hdr_dat_bst_1_mosi => reg_stat_hdr_dat_bst_mosi_arr(1),
- reg_stat_hdr_dat_bst_1_miso => reg_stat_hdr_dat_bst_miso_arr(1)
+ reg_stat_hdr_dat_bst_1_miso => reg_stat_hdr_dat_bst_miso_arr(1),
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso
);
-----------------------------------------------------------------------------
@@ -814,6 +843,39 @@ BEGIN
);
END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- node_sdp_correlator (XSUB)
+ -----------------------------------------------------------------------------
+ gen_use_xsub : IF c_revision_select.use_xsub GENERATE
+ u_xsub : ENTITY lofar2_sdp_lib.node_sdp_correlator
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_P_sq => c_revision_select.P_sq
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ out_crosslets_info => out_crosslets_info
+
+ );
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- nof beamsets node_sdp_beamformers (BF)
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index 339ec50a03a9f8a7ce3fb4089d80ed6e44971fa1..a51d1ab304fcdd594f6938950980950ec68e180c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -35,12 +35,15 @@ PACKAGE lofar2_unb2b_sdp_station_pkg IS
no_jesd : BOOLEAN;
use_fsub : BOOLEAN;
use_bf : BOOLEAN;
+ use_xsub : BOOLEAN;
+ P_sq : NATURAL;
END RECORD;
- CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE);
- CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE);
- CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE);
- CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE);
+ CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, 0);
+ CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, 0);
+ CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, 0);
+ CONSTANT c_xsub_one : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, 1);
+ CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, 1);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config;
@@ -53,9 +56,10 @@ PACKAGE BODY lofar2_unb2b_sdp_station_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config IS
BEGIN
- IF g_design_name = "lofar2_unb2b_sdp_station_adc" THEN RETURN c_ait;
- ELSIF g_design_name = "lofar2_unb2b_sdp_station_fsub" THEN RETURN c_fsub;
- ELSIF g_design_name = "lofar2_unb2b_sdp_station_bf" THEN RETURN c_bf;
+ IF g_design_name = "lofar2_unb2b_sdp_station_adc" THEN RETURN c_ait;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_fsub" THEN RETURN c_fsub;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_bf" THEN RETURN c_bf;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_xsub_one" THEN RETURN c_xsub_one;
ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 1021899a027b7b34c3f577bc7a70f2c46a1db693..d6824efd58137577733eaea074e5f183eaad01e7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -206,6 +206,22 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_stat_hdr_dat_bst_1_mosi : OUT t_mem_mosi;
reg_stat_hdr_dat_bst_1_miso : IN t_mem_miso;
+ -- dp_sync_insert_v2
+ reg_dp_sync_insert_v2_mosi : OUT t_mem_mosi;
+ reg_dp_sync_insert_v2_miso : IN t_mem_miso;
+
+ -- crosslets_info
+ reg_crosslets_info_mosi : OUT t_mem_mosi;
+ reg_crosslets_info_miso : IN t_mem_miso;
+
+ -- bsn_scheduler_xsub
+ reg_bsn_scheduler_xsub_mosi : OUT t_mem_mosi;
+ reg_bsn_scheduler_xsub_miso : IN t_mem_miso;
+
+ -- st_xsq (XST)
+ ram_st_xsq_mosi : OUT t_mem_mosi;
+ ram_st_xsq_miso : IN t_mem_miso;
+
-- 10 GbE mac
reg_nw_10GbE_mac_mosi : OUT t_mem_mosi;
reg_nw_10GbE_mac_miso : IN t_mem_miso;
@@ -349,6 +365,18 @@ BEGIN
u_mm_file_reg_stat_hdr_info_bst_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST_1")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_1_mosi, reg_stat_hdr_dat_bst_1_miso);
+ u_mm_file_reg_dp_sync_insert_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SYNC_INSERT_V2")
+ PORT MAP(mm_rst, mm_clk, reg_dp_sync_insert_v2_mosi, reg_dp_sync_insert_v2_miso);
+
+ u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
+
+ u_mm_file_reg_bsn_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_xsub_mosi, reg_bsn_scheduler_xsub_miso);
+
+ u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
+ PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
+
u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
@@ -749,6 +777,38 @@ BEGIN
reg_stat_hdr_dat_bst_1_read_export => reg_stat_hdr_dat_bst_1_mosi.rd,
reg_stat_hdr_dat_bst_1_readdata_export => reg_stat_hdr_dat_bst_1_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_sync_insert_v2_clk_export => OPEN,
+ reg_dp_sync_insert_v2_reset_export => OPEN,
+ reg_dp_sync_insert_v2_address_export => reg_dp_sync_insert_v2_mosi.address(c_sdp_reg_dp_sync_insert_v2_addr_w-1 DOWNTO 0),
+ reg_dp_sync_insert_v2_write_export => reg_dp_sync_insert_v2_mosi.wr,
+ reg_dp_sync_insert_v2_writedata_export => reg_dp_sync_insert_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_sync_insert_v2_read_export => reg_dp_sync_insert_v2_mosi.rd,
+ reg_dp_sync_insert_v2_readdata_export => reg_dp_sync_insert_v2_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_crosslets_info_clk_export => OPEN,
+ reg_crosslets_info_reset_export => OPEN,
+ reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_mosi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_scheduler_xsub_clk_export => OPEN,
+ reg_bsn_scheduler_xsub_reset_export => OPEN,
+ reg_bsn_scheduler_xsub_address_export => reg_bsn_scheduler_xsub_mosi.address(c_sdp_reg_bsn_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_scheduler_xsub_write_export => reg_bsn_scheduler_xsub_mosi.wr,
+ reg_bsn_scheduler_xsub_writedata_export => reg_bsn_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_xsub_read_export => reg_bsn_scheduler_xsub_mosi.rd,
+ reg_bsn_scheduler_xsub_readdata_export => reg_bsn_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ ram_st_xsq_clk_export => OPEN,
+ ram_st_xsq_reset_export => OPEN,
+ ram_st_xsq_address_export => ram_st_xsq_mosi.address(c_sdp_ram_st_xsq_addr_w-1 DOWNTO 0),
+ ram_st_xsq_write_export => ram_st_xsq_mosi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_read_export => ram_st_xsq_mosi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_nw_10GbE_mac_clk_export => OPEN,
reg_nw_10GbE_mac_reset_export => OPEN,
reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index f4f915592f2f5676e97b63d237e533e52fab2c98..0a35a58be6f9fa1c4c6aea50c36021a2ada706e3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -329,6 +329,34 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_stat_hdr_dat_bst_1_reset_export : out std_logic; -- export
reg_stat_hdr_dat_bst_1_write_export : out std_logic; -- export
reg_stat_hdr_dat_bst_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_sync_insert_v2_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_sync_insert_v2_clk_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_read_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_sync_insert_v2_reset_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_write_export : out std_logic; -- export
+ reg_dp_sync_insert_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_xsub_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_si_address_export : out std_logic_vector(0 downto 0); -- export
reg_si_clk_export : out std_logic; -- export
reg_si_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 1a28839eecb89d4fec64d3176b3d0bed61bb06d9..cdeb290bef11bc5446e7225bc071794d900562f3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -60,8 +60,8 @@ ENTITY node_sdp_correlator IS
reg_crosslets_info_miso : OUT t_mem_miso;
reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso;
--sdp_info : IN t_sdp_info;
--gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -126,8 +126,8 @@ BEGIN
u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
GENERIC MAP (
g_nof_streams => c_sdp_P_pfb,
- g_nof_blk_per_sync => 200000,
- g_nof_blk_per_sync_min => 19530
+ g_nof_blk_per_sync => c_sdp_dp_sync_insert_nof_blk_per_sync,
+ g_nof_blk_per_sync_min => c_sdp_dp_sync_insert_nof_blk_per_sync_min
)
PORT MAP (
dp_rst => dp_rst,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 00b4b5ed89099bea08523565cf334bf162088f70..44d3cdf688ecd7b598e57f5f5d6bea4ebd9bc31a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -186,6 +186,14 @@ PACKAGE sdp_pkg is
init_sl => '0');
CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w;
+ CONSTANT c_sdp_dp_sync_insert_nof_blk_per_sync : NATURAL := 200000;
+ CONSTANT c_sdp_dp_sync_insert_nof_blk_per_sync_min : NATURAL := 19530;
+
+ -- XSUB MM adderss widths
+ CONSTANT c_sdp_reg_dp_sync_insert_v2_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
+ CONSTANT c_sdp_reg_bsn_scheduler_xsub_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_S_pn**2 * 2);
-- 10GbE offload (cep = central processor)
CONSTANT c_sdp_cep_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 7f2fd8aed81aba0ee3dd2924874cd8fb3afe0fc0..2520c398666f8fa545c8e61c4cb38b375f29aee6 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -68,7 +68,7 @@ BEGIN
address <= start_address + r.word_index + r.step_index;
mm_mosi.address <= TO_MEM_ADDRESS(address);
mm_mosi.wrdata <= RESIZE_MEM_DATA(in_sosi.data);
- mm_mosi.wr <= r.wr;
+ mm_mosi.wr <= d.wr;
p_reg : PROCESS(rst, clk)
BEGIN
@@ -104,4 +104,4 @@ BEGIN
END IF;
END PROCESS;
-END rtl;
\ No newline at end of file
+END rtl;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index 6e001091967a2795a22b90992d61109e0418a1af..b924263f39b412d409da0a0dadcbec09d2ee2926 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -248,6 +248,7 @@ BEGIN
out_sosi_arr(I).sop <= in_sosi_arr_pipe_ctrl(I).sop;
out_sosi_arr(I).eop <= in_sosi_arr_pipe_ctrl(I).eop;
out_sosi_arr(I).sync <= in_sosi_arr_pipe_ctrl(I).sync;
+ out_sosi_arr(I).bsn <= in_sosi_arr_pipe_ctrl(I).bsn;
END PROCESS;
END GENERATE gen_real_multiply;
@@ -301,6 +302,7 @@ BEGIN
out_sosi_arr(I).sop <= in_sosi_arr_pipe_ctrl(I).sop;
out_sosi_arr(I).eop <= in_sosi_arr_pipe_ctrl(I).eop;
out_sosi_arr(I).sync <= in_sosi_arr_pipe_ctrl(I).sync;
+ out_sosi_arr(I).bsn <= in_sosi_arr_pipe_ctrl(I).bsn;
END PROCESS;
END GENERATE gen_complex_multiply;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
index c12b28090198fd721d9e5f2610f28b6db06b378e..7b67d8e2083c598fa3645c48d5ddc7032bb9869c 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
@@ -60,14 +60,15 @@ ARCHITECTURE rtl OF st_xsq_dp_to_mm IS
SIGNAL reg_sosi_info : t_dp_sosi := c_dp_sosi_rst;
SIGNAL in_sosi_rewired : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL next_page : STD_LOGIC;
BEGIN
p_in_sosi : PROCESS(in_sosi)
BEGIN
in_sosi_rewired <= in_sosi;
- in_sosi_rewired.data( g_dsp_data_w -1 DOWNTO 0) <= in_sosi.re(g_dsp_data_w-1 DOWNTO 0);
- in_sosi_rewired.data(c_nof_complex * g_dsp_data_w -1 DOWNTO 0) <= in_sosi.im(g_dsp_data_w-1 DOWNTO 0);
+ in_sosi_rewired.data( g_dsp_data_w -1 DOWNTO 0) <= in_sosi.re(g_dsp_data_w-1 DOWNTO 0);
+ in_sosi_rewired.data(c_nof_complex * g_dsp_data_w -1 DOWNTO g_dsp_data_w) <= in_sosi.im(g_dsp_data_w-1 DOWNTO 0);
END PROCESS;
u_dp_block_to_mm : ENTITY dp_lib.dp_block_to_mm
@@ -111,16 +112,19 @@ BEGIN
IF rst='1' THEN
out_sosi_info <= c_dp_sosi_rst;
reg_sosi_info <= c_dp_sosi_rst;
+ next_page <= '0';
ELSIF rising_edge(clk) THEN
IF in_sosi.sop = '1' THEN
reg_sosi_info <= in_sosi;
END IF;
IF in_sosi.eop = '1' THEN
+ next_page <= '1';
out_sosi_info <= reg_sosi_info;
out_sosi_info.eop <= '1';
out_sosi_info.err <= in_sosi.err;
ELSE
out_sosi_info <= c_dp_sosi_rst;
+ next_page <= '0';
END IF;
END IF;
END PROCESS;