diff --git a/libraries/dsp/rTwoSDF/hdllib.cfg b/libraries/dsp/rTwoSDF/hdllib.cfg
index 2a0b2fbbe5fb2b1d331b0fda42042f3944c38f01..5db2c8d73b7f208fb774f3a030d73a6e62fdfdb4 100644
--- a/libraries/dsp/rTwoSDF/hdllib.cfg
+++ b/libraries/dsp/rTwoSDF/hdllib.cfg
@@ -21,8 +21,7 @@ test_bench_files =
tb/vhdl/tb_rTwoOrder.vhd
regression_test_vhdl =
- tb/vhdl/tb_rTwoSDF.vhd
-
+ tb/vhdl/tb_tb_rTwoSDF.vhd
[modelsim_project_file]
modelsim_copy_files = tb/data data
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
index 5cb8dee3fb649a8817dfef7e3b71e374f8559bba..7e113d74d9c937224097f155c7357cf846f2b092 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
@@ -50,10 +50,9 @@
--
-- Usage:
-- > vsim -vopt -voptargs=+acc work.tb_rtwosdf (double click tb_rtwosdf icon)
--- > do wave_rTwoSDF.do
-- > run -all
--- . it may be necessary to rescale the analogue formats in the Wave
--- window after running the simulation.
+-- > observe the *_re and *_im as radix decimal, format analogue format
+-- signals in the Wave window
--
-- Remarks:
-- . The tb uses LRM 1076-1987 style for file IO. This implies that only
@@ -62,10 +61,6 @@
-- file is modified even if the contents is not changed. Only after closing
-- the simulation (> quit -sim) does the SVN file icon indicate the true
-- state. Next time we better use LRM 1076-1993 style for file IO.
---
--- . The generic g_post_sim can be used to switch between functional simulation
--- and timing simulation. Note that the entity name of the timing model from
--- the .vho file must be changed to rTwoSDF_t.
library ieee, common_lib;
use IEEE.std_logic_1164.all;
@@ -84,9 +79,8 @@ entity tb_rTwoSDF is
-- generics for tb
g_use_uniNoise_file : boolean := true;
g_in_en : natural := 1; -- 1 = always active, others = random control
- g_post_sim : boolean := false;
-- generics for rTwoSDF
- g_use_reorder : boolean := true;
+ g_use_reorder : boolean := false; -- tb supports both true and false
g_nof_points : natural := 1024;
g_in_dat_w : natural := 8;
g_out_dat_w : natural := 14;
@@ -114,7 +108,7 @@ architecture tb of tb_rTwoSDF is
constant c_clk_period : time := 20 ns;
-
+ constant c_nof_points_w : natural := ceil_log2(g_nof_points);
-- input/output data width
constant c_stage_dat_w : natural := sel_a_b(g_out_dat_w > c_dsp_mult_w, g_out_dat_w, c_dsp_mult_w); -- number of bits used between the stages
@@ -167,7 +161,9 @@ architecture tb of tb_rTwoSDF is
signal gold_file_sync : std_logic_vector(0 to c_file_len-1):= (others=>'0');
signal gold_file_val : std_logic_vector(0 to c_file_len-1):= (others=>'0');
+ signal gold_index_max : natural := c_file_len - 2*g_nof_points;
signal gold_index : natural;
+ signal flip_index : natural;
signal gold_sync : std_logic;
signal gold_re : integer;
signal gold_im : integer;
@@ -264,51 +260,29 @@ begin
end if;
end process;
-
- gen_func_dut : if g_post_sim = FALSE generate
- -- DUT = Device Under Test
- u_rTwoSDF : entity work.rTwoSDF
- generic map(
- -- generics for the FFT
- g_use_reorder => g_use_reorder,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_stage_dat_w => c_stage_dat_w,
- g_guard_w => g_guard_w,
- g_nof_points => g_nof_points,
- -- generics for rTwoSDFStage
- g_pipeline => g_pipeline
- )
- port map(
- clk => clk,
- rst => rst,
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val
- );
- end generate;
-
--- In case a timing simulation should be made the next code
--- should be un-commented. And the name of the timing varina entity
--- in the .vho file must be renamed to rTwoSDF_t.
-
--- gen_time_dut : if g_post_sim = TRUE generate
--- -- DUT = Device Under Test
--- u_rTwoSDF_t : entity work.rTwoSDF_t
--- port map(
--- clk => clk,
--- rst => rst,
--- in_re => in_re,
--- in_im => in_im,
--- in_val => in_val,
--- out_re => out_re,
--- out_im => out_im,
--- out_val => out_val
--- );
--- end generate;
+ -- DUT = Device Under Test
+ u_rTwoSDF : entity work.rTwoSDF
+ generic map(
+ -- generics for the FFT
+ g_use_reorder => g_use_reorder,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_stage_dat_w => c_stage_dat_w,
+ g_guard_w => g_guard_w,
+ g_nof_points => g_nof_points,
+ -- generics for rTwoSDFStage
+ g_pipeline => g_pipeline
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val
+ );
-- Read golden file with the expected DUT output
p_read_golden_file : process
@@ -354,16 +328,17 @@ begin
-- Show read data in Wave Window for debug purposes
gold_index <= gold_index + 1 when rising_edge(clk) and out_val='1';
+ flip_index <= (gold_index / g_nof_points) * g_nof_points + flip(gold_index mod g_nof_points, c_nof_points_w);
gold_sync <= gold_file_sync(gold_index);
- gold_re <= gold_file_data(gold_index,1);
- gold_im <= gold_file_data(gold_index,2);
+ gold_re <= gold_file_data(gold_index,1) when g_use_reorder=true else gold_file_data(flip_index,1);
+ gold_im <= gold_file_data(gold_index,2) when g_use_reorder=true else gold_file_data(flip_index,2);
-- Verify the output of the DUT with the expected output from the golden reference file
p_verify_output : process(clk)
begin
-- Compare
if rising_edge(clk) then
- if out_val='1' then
+ if out_val='1' and gold_index <= gold_index_max then
-- only write when out_val='1', because then the file is independent of cycles with invalid out_dat
assert out_sync = gold_sync report "Output sync error" severity error;
assert TO_SINT(out_re) = gold_re report "Output real data error" severity error;
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
index a51e8063af53c265ae65e2febf96c4155604bd77..8734636a2db1dc11d0432cc332f454d14a267b8b 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
@@ -38,19 +38,40 @@ use work.rTwoSDFPkg.all;
entity tb_tb_rTwoSDF is
end entity tb_tb_rTwoSDF;
-architecture str of tb_tb_rTwoSDF is
+architecture tb of tb_tb_rTwoSDF is
+ signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
begin
- gen_nof_points : for N in 2 to 12 generate
- gen_in_dat_w : for W in 4 to 16 generate
- u_tb_rTwoSDF: entity work.tb_rTwoSDF
- generic map
- (
- g_in_dat_w => W,
- g_nof_points => pow2(N)
- );
- end generate;
- end generate;
-
-end str;
+-- -- generics for tb
+-- g_use_uniNoise_file : boolean := true;
+-- g_in_en : natural := 0; -- 1 = always active, others = random control
+-- -- generics for rTwoSDF
+-- g_use_reorder : boolean := true;
+-- g_nof_points : natural := 1024;
+-- g_in_dat_w : natural := 8;
+-- g_out_dat_w : natural := 14;
+-- g_guard_w : natural := 2; -- guard bits are used to avoid overflow in single FFT stage.
+--
+-- -- Internal pipeline settings for rTwoSDF
+-- g_pipeline : t_fft_pipeline := (1, 1, 3, 1, 1, 0, 0, 1) -- type t_rtwo_sdf_stage_pipeline is record
+-- -- -- generics for rTwoSDFStage
+-- -- stage_lat : natural; -- = 1
+-- -- weight_lat : natural; -- = 1
+-- -- mul_lat : natural; -- = 3
+-- -- -- generics for rTwoBFStage
+-- -- bf_lat : natural; -- = 1
+-- -- -- generics for rTwoBF
+-- -- bf_use_zdly : natural; -- = 1
+-- -- bf_in_a_zdly : natural; -- = 0
+-- -- bf_out_d_zdly : natural; -- = 0
+-- -- sep_lat : natural; -- = 1
+-- -- end record;
+
+ --u_act_impulse_16p_16i_16o : entity work.tb_rTwoSDF generic map (false, 1, true, 16, 16, 16, 2, (1, 1, 3, 1, 1, 0, 0, 1));
+ u_act_noise_1024p_8i_14o : entity work.tb_rTwoSDF generic map (true, 1, true, 1024, 8, 14, 2, (1, 1, 3, 1, 1, 0, 0, 1));
+ u_rnd_noise_1024p_8i_14o : entity work.tb_rTwoSDF generic map (true, 0, true, 1024, 8, 14, 2, (1, 1, 3, 1, 1, 0, 0, 1));
+ u_rnd_noise_1024p_8i_14o_flipped : entity work.tb_rTwoSDF generic map (true, 0, false, 1024, 8, 14, 2, (1, 1, 3, 1, 1, 0, 0, 1));
+
+end tb;