From 3ac8fbe454df41162ea698c40aa350096e628cd9 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 23 Jan 2015 10:51:39 +0000
Subject: [PATCH] Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4
IP) rd burst accesses of g_tech_ddr.maxburstsize each.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 63bff7f5db..1d853ab889 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -41,6 +41,14 @@
-- DDR write access can start on the next valid, sop or sync dependent on
-- g_wr_flush_mode.
--
+-- The g_rd_fifo_af_margin needs to be large enough to fit a number of read
+-- bursts that may be pending in the DDR controller command queue depth.
+-- A new rd access can start when ctlr_rd_src_in.ready indicates that there
+-- is sufficient space in the read FIFO to store g_tech_ddr.maxburstsize
+-- words. Due to the DDR controller command queue there can be more rd
+-- bursts already be pending. Therefore the g_rd_fifo_af_margin needs to be
+-- large enough to fit a number of read bursts.
+
-- In simulation use g_sim=TRUE to also include the DDR memory model that is
-- internally available within tech_ddr. This avoids having to connect a DDR
-- memory model at top level in the test bench.
@@ -54,7 +62,7 @@
-- . The dvr interface could be connected to a DP sequencer that can write
-- blocks to DDR and read back from DDR. The DP sequencer uses signals
-- from its input DP interface. For write access the dvr_en could relate
--- to teh sop and the dvr_nof_data then equals the nof data from sop to eop.
+-- to the sop and the dvr_nof_data then equals the nof data from sop to eop.
-- The dvr_done can be treated as xon. The dvr_wr_not_rd selects between
-- the write stream to DDR access or the read stream from DDR access. For a
-- read access the sequencer needs to generate the dvr signals itself.
@@ -156,8 +164,9 @@ ENTITY io_ddr IS
g_cross_domain_dvr_ctlr : BOOLEAN := TRUE;
g_cross_domain_delay_len : NATURAL := c_meta_delay_len;
g_wr_data_w : NATURAL := 32;
- g_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
- g_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+ g_wr_fifo_depth : NATURAL := 256; -- >=16 , defined at DDR side of the FIFO, default 256 because 32b*256 fits in 1 M9K
+ g_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO, default 256 because 32b*256 fits in 1 M9K
+ g_rd_fifo_af_margin : NATURAL := 4 + 1*64; -- < g_rd_fifo_depth and sufficient to fit one or more rd burst accesses of g_tech_ddr.maxburstsize each
g_rd_data_w : NATURAL := 32;
g_wr_flush_mode : STRING := "VAL"; -- "VAL", "SOP", "SYN"
g_wr_flush_use_channel : BOOLEAN := FALSE;
@@ -218,7 +227,6 @@ ARCHITECTURE str OF io_ddr IS
CONSTANT c_wr_fifo_depth : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w); -- get FIFO depth at write side
CONSTANT c_wr_fifo_af_margin : NATURAL := 4 + 1; -- use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
- CONSTANT c_rd_fifo_af_margin : NATURAL := 4 + g_tech_ddr.maxburstsize; -- use ctlr_rd_src_in.ready to only start new rd access when there is sufficient space in the read FIFO
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
@@ -369,7 +377,7 @@ BEGIN
g_rd_data_w => g_rd_data_w,
g_use_ctrl => FALSE,
g_wr_fifo_size => g_rd_fifo_depth,
- g_wr_fifo_af_margin => c_rd_fifo_af_margin, -- >=4 (required by dp_fifo)
+ g_wr_fifo_af_margin => g_rd_fifo_af_margin, -- >=4 (required by dp_fifo)
g_rd_fifo_rl => 1
)
PORT MAP (
--
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