From 3abe4b65adc885f48e663e339b97f719475258ff Mon Sep 17 00:00:00 2001 From: donker <donker@astron.nl> Date: Fri, 30 Oct 2020 23:53:40 +0100 Subject: [PATCH] LsSDp-180: first commit of common_variable_delay --- .../common/src/vhdl/common_variable_delay.vhd | 110 +++++++++++++++++ .../tb/vhdl/tb_common_variable_delay.vhd | 116 ++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 libraries/base/common/src/vhdl/common_variable_delay.vhd create mode 100644 libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd new file mode 100644 index 0000000000..c5be42f723 --- /dev/null +++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd @@ -0,0 +1,110 @@ +-- -------------------------------------------------------------------------- +-- Copyright 2020 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- -------------------------------------------------------------------------- + +-- -------------------------------------------------------------------------- +-- Author: +-- . Pieter Donker +-- Purpose: +-- . Delay input pulse by number of given delay cycles +-- Description: +-- . delay input pulse by nof_cycles_delay +-- . output pulse is derived form low-high transition of input pulse. +-- . during delay other input pulses are ignored +-- -------------------------------------------------------------------------- + +LIBRARY IEEE, technology_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE work.common_pkg.ALL; + + +ENTITY common_variable_delay IS + --GENERIC ( + --); + PORT ( + rst : IN STD_LOGIC; + clk : IN STD_LOGIC; + + delay : IN NATURAL := 0; + enable : IN STD_LOGIC := '0'; + in_val : IN STD_LOGIC; + out_val : OUT STD_LOGIC + ); +END common_variable_delay; + + +ARCHITECTURE rtl OF common_variable_delay IS + + SIGNAL i_out_val : STD_LOGIC; + SIGNAL nxt_i_out_val : STD_LOGIC; + SIGNAL delay_cnt : NATURAL; + SIGNAL nxt_delay_cnt : NATURAL; + SIGNAL in_val_hold : STD_LOGIC; + SIGNAL nxt_in_val_hold : STD_LOGIC; + +BEGIN + out_val <= i_out_val AND enable; + + p_delay: PROCESS(delay, in_val, i_out_val, delay_cnt, in_val_hold) + BEGIN + nxt_i_out_val <= i_out_val; + nxt_delay_cnt <= delay_cnt; + nxt_in_val_hold <= in_val_hold; + + IF delay = 0 THEN + nxt_i_out_val <= in_val; + ELSE + IF RISING_EDGE(in_val) AND in_val_hold = '0' THEN + nxt_in_val_hold <= '1'; + nxt_delay_cnt <= 1; + END IF; + + IF in_val_hold = '1' AND i_out_val = '1' THEN + nxt_in_val_hold <= '0'; + END IF; + + IF in_val_hold = '1' THEN + nxt_delay_cnt <= delay_cnt + 1; + END IF; + + IF i_out_val = '1' THEN + nxt_i_out_val <= '0'; + END IF; + + IF delay_cnt = delay THEN + nxt_i_out_val <= '1'; + nxt_in_val_hold <= '0'; + --nxt_delay_cnt <= 0; + END IF; + END IF; + END PROCESS; + + p_clk : PROCESS(rst, clk) + BEGIN + IF rst = '1' THEN + i_out_val <= '0'; + delay_cnt <= 0; + in_val_hold <= '0'; + ELSIF rising_edge(clk) THEN + i_out_val <= nxt_i_out_val; + delay_cnt <= nxt_delay_cnt; + in_val_hold <= nxt_in_val_hold; + END IF; + END PROCESS; + + +END rtl; diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd new file mode 100644 index 0000000000..d25232b835 --- /dev/null +++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2011 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE work.common_pkg.ALL; +USE work.tb_common_pkg.ALL; + +ENTITY tb_common_variable_delay IS +END tb_common_variable_delay; + +ARCHITECTURE tb OF tb_common_variable_delay IS + + CONSTANT clk_period : TIME := 10 ns; + CONSTANT max_delay : NATURAL := 5; + + SIGNAL tb_end : STD_LOGIC := '0'; + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC := '0'; + + SIGNAL delay : NATURAL := 0; + SIGNAL enable : STD_LOGIC := '0'; + SIGNAL trigger : STD_LOGIC; + SIGNAL trigger_dly : STD_LOGIC; +BEGIN + + clk <= (NOT clk) OR tb_end AFTER clk_period/2; + rst <= '1', '0' AFTER clk_period*3; + + -- run 1 us + p_in_stimuli : PROCESS + BEGIN + delay <= 0; + enable <= '0'; + trigger <= '0'; + + WAIT UNTIL rst = '0'; + WAIT UNTIL rising_edge(clk); + + -- Start counting + enable <= '0'; + proc_common_wait_some_cycles(clk, 50); + FOR i IN 0 TO 10 LOOP + trigger <= '1'; + proc_common_wait_some_cycles(clk, 4); + trigger <= '0'; + proc_common_wait_some_cycles(clk, 4); + END LOOP; + + enable <= '1'; + FOR i IN 0 TO 10 LOOP + trigger <= '1'; + proc_common_wait_some_cycles(clk, 4); + trigger <= '0'; + proc_common_wait_some_cycles(clk, 4); + END LOOP; + + delay <= 1; + FOR i IN 0 TO 10 LOOP + trigger <= '1'; + proc_common_wait_some_cycles(clk, 4); + trigger <= '0'; + proc_common_wait_some_cycles(clk, 4); + END LOOP; + + delay <= 12; + FOR i IN 0 TO 10 LOOP + trigger <= '1'; + proc_common_wait_some_cycles(clk, 4); + trigger <= '0'; + proc_common_wait_some_cycles(clk, 4); + END LOOP; + + + tb_end <= '1'; + WAIT; + END PROCESS; + + -- device under test + u_dut : ENTITY work.common_variable_delay + GENERIC MAP ( + g_max_delay => max_delay + ) + PORT MAP ( + rst => rst, + clk => clk, + + delay => delay, + enable => enable, + in_val => trigger, + out_val => trigger_dly + ); + +END tb; + + -- GitLab