diff --git a/libraries/base/mm/src/vhdl/mm_bus.vhd b/libraries/base/mm/src/vhdl/mm_bus.vhd
index f87ae906eba7d56abf134ab27ac92c16efe0f8ca..75e5fdb98f91ec73e48e377923e3873a22a784dd 100644
--- a/libraries/base/mm/src/vhdl/mm_bus.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus.vhd
@@ -22,74 +22,17 @@
--
-- Author: E. Kooistra
-- Purpose: Connect a single MM master interface to a list of MM slave
--- interfaces
+-- interfaces using mm_bus_pipe.
-- Description:
--- * MM bus
--- The mm_bus creates a memory mapped (MM) bus that connects read
--- and write accesses from the master interface to the addressed slave
--- interface. There is one master that controls the bus and there are
--- g_nof_slaves on the bus. Per slave the start address and address span
--- have to be specified via g_base_arr and g_width_arr.
---
--- * Slave allocation
--- The slaves have to be located on the bus such that the MSbits of the
--- global address can be used to select the slave and the LSbits of the
--- global address can directly be used to select the address within the
--- slave. Therefore:
--- . The width of a slave is the power of 2 that fits the address range of
--- the slave.
--- . The span of a slave is 2**width.
--- . The base address of a slave has to be a power of 2 multiple of the
--- slave span.
---
--- * The mm_clk is only used when there is a slave with read latency > 0 or
--- when the MM bus uses pipelining.
+-- In addition to mm_bus_pipe this mm_bus takes care of:
+-- - not connected slaves
+-- - slaves that do not need flow control
+--
+-- * MM bus --> see mm_bus_comb
+-- * Slave allocation --> see mm_bus_comb
+-- * Read latency --> see mm_bus_comb
+-- * Pipelining --> see mm_bus_pipe
--
--- * Read latency
--- For read accesses a slave will typically have a read latency > 0, which
--- means that when the rd and address are active, then it takes read
--- latency number of clock cycles until the rddata becomes available. The
--- read latency can be specified per slave via g_rd_latency_arr.
--- The index_pipeline is used to support that a new wr access or rd access
--- can already start, while a current rd access still has to finish with
--- a rdval. Without the index_pipeline the master would have to wait with
--- a new rd or wr access to another slave until the read response from the
--- current slave has finished.
--- ________
--- | pipe |
--- master_mosi.address[h:w] = index --+-->| line |--\
--- | |______| |
--- | |
--- v |
--- master_mosi --> slave_mosi_arr.wr[ ]----------------> slave_mosi_arr
--- rd |
--- v
--- master_miso <--------------------slave_miso_arr[ ]<-- slave_miso_arr
---
--- * Pipelining
--- Default the common_mm_bus is combinatorial, so there is no pipelining
--- between the master interface and the slave interfaces. If possible do not
--- use pipelining of mosi and miso to avoid increasing the read latency and
--- achieve timing closure by lower clock rate for the MM bus. Pipelining the
--- MM bus can be necessary to achieve timing closure:
--- . g_pipeline_mosi
--- Pipelining mosi write accesses introduces an extra latency from master
--- to slave, which is typically not a problem. Pipelining mosi read
--- accesses increases the read latency between accessing the slave and
--- getting the rddata. Using a different pipelining for the wr and the rd
--- pulse would yield a different pipelining of the address for write and
--- for read, which is akward. Therefore assume that both mosi write and
--- mosi read have the same pipelining.
--- . g_pipeline_miso_rdval
--- Pipelining the miso read data increases the read latency.
--- . g_pipeline_miso_wait
--- Pipelining the miso waitrequest increases the write and read latency
--- for slaves that need MM flow control.
--- The total write latency from master to slave is c_pipeline_mosi.
--- The total read latency from master via slave back to master is
--- c_pipeline_mosi + g_rd_latency_arr of the selected slave +
--- c_pipeline_miso_rdval.
---
-- Usage:
-- The ascii drawing shows how this mm_bus can be used in combination
-- with other MM bus components to create an memory mapped bus:
@@ -122,36 +65,15 @@
-- based on a set of MM slave ports described in YAML configuration
-- files.
--
--- Limitations:
--- * A limitation is that if one slave has a read latency of 2 and another
--- slave has a read latency of 1 then it is not possible to access them
--- without a gap of 1 mm_clk cycle, because the rdval will then be active
--- simultaneously from both slaves. Therefore the master can only use
--- random read access between slaves if all slaves have the same read
--- latency. For slaves that have larger read latency the master must
--- insert an gap, before it can read a slave that has less read latency.
--- An alternative workaround would be to use the same read latency for all
--- slaves on the bus, by pipelining the miso.rd, rddata for MM slaves that
--- have a smaller read latency.
--- * No support yet for g_pipeline_miso_wait = TRUE. This requires an MM
--- latency adapter for the mosi dependent on the miso.waitrequest.
+-- Limitations --> see mm_bus_comb
--
-- Todo:
-- * The mm_bus assumes that the MM slave will pull miso.waitrequest low.
-- To avoid that the MM bus accesss will stall, a MM slave port that uses
--- mosi flow control should also support an waitrequest timeout mechanism.
+-- mosi flow control should also support a waitrequest timeout mechanism.
-- The master can then be informed about the failing mosi access using
--- the miso.response field of the Avalon bus.
---
--- Remarks:
--- . The mm_bus resembles common_mem_mux, but the difference is that
--- with common_mem_mux all slaves have the same address range and are
--- spaced without address gaps. It is possible to use common_mem_mux in
--- series with mm_bus to provide hierarchy by reprensenting an array
--- of slave ports via a single slave port on the MM bus.
--- . In simulation selecting an unused element address will cause a simulation
--- failure. Therefore the element index is only accepted when it is in the
--- 0 TO g_nof_slaves-1 range.
+-- the miso.response field of the Avalon bus. Such a timeout mechanism
+-- could also be supported via mm_slave_enable.
--
-------------------------------------------------------------------------------
@@ -167,11 +89,13 @@ ENTITY mm_bus IS
g_base_arr : t_nat_natural_arr; -- Address base per slave
g_width_arr : t_nat_natural_arr; -- Address width per slave
g_rd_latency_arr : t_nat_natural_arr; -- Read latency per slave
+ g_waitrequest_arr : t_nat_boolean_arr; -- Enable waitrequest flow control per slave, else fixed '0'
g_pipeline_mosi : BOOLEAN := FALSE; -- Pipeline MM access (wr, rd)
g_pipeline_miso_rdval : BOOLEAN := FALSE; -- Pipeline MM read (rdval)
g_pipeline_miso_wait : BOOLEAN := FALSE -- Pipeline MM access flow control (waitrequest)
);
PORT (
+ mm_rst : IN STD_LOGIC := '0';
mm_clk : IN STD_LOGIC := '0';
master_mosi : IN t_mem_mosi;
master_miso : OUT t_mem_miso;
@@ -180,117 +104,53 @@ ENTITY mm_bus IS
);
END mm_bus;
-ARCHITECTURE rtl OF mm_bus IS
-
- -- Determine the address range of all slaves on the MM bus.
- FUNCTION func_derive_mm_bus_addr_w(g_base_arr, g_width_arr : t_nat_natural_arr) RETURN NATURAL IS
- VARIABLE v_base : NATURAL := 0;
- VARIABLE v_width : NATURAL;
- VARIABLE v_mm_bus_addr_max : NATURAL;
- BEGIN
- FOR I IN g_base_arr'RANGE LOOP
- IF g_base_arr(I) > v_base THEN
- v_base := g_base_arr(I);
- v_width := g_width_arr(I);
- END IF;
- END LOOP;
- -- Largest base address + the width of the slave at this address - 1. The
- -- -1 is because the addresses count from 0 to N-1.
- v_mm_bus_addr_max := v_base + 2**v_width - 1;
- -- Return number of bits to represent the largest address that will be used
- -- on the MM bus
- RETURN ceil_log2(v_mm_bus_addr_max);
- END;
+ARCHITECTURE str OF mm_bus IS
- CONSTANT c_mm_bus_addr_w : NATURAL := func_derive_mm_bus_addr_w(g_base_arr, g_width_arr);
- CONSTANT c_pipeline_mosi : NATURAL := sel_a_b(g_pipeline_mosi, 1, 0);
- CONSTANT c_pipeline_miso_rdval : NATURAL := sel_a_b(g_pipeline_miso_rdval, 1, 0);
- CONSTANT c_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_miso_wait, 1, 0);
- CONSTANT c_index_latency_max : NATURAL := c_pipeline_mosi + largest(g_rd_latency_arr);
-
- SIGNAL index_pipeline : t_nat_natural_arr(0 TO c_index_latency_max) := (OTHERS=>0);
- SIGNAL slave_mosi_arr_comb : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
- SIGNAL slave_mosi_arr_reg : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
- SIGNAL master_miso_comb : t_mem_miso := c_mem_miso_rst;
- SIGNAL master_miso_reg : t_mem_miso := c_mem_miso_rst;
+ SIGNAL bus_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1);
+ SIGNAL bus_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1);
BEGIN
- gen_single : IF g_nof_slaves=1 GENERATE
- slave_mosi_arr(0) <= master_mosi;
- master_miso <= slave_miso_arr(0);
+ -- MM bus
+ u_mm_bus_pipe : ENTITY work.mm_bus_pipe
+ GENERIC MAP (
+ g_nof_slaves => g_nof_slaves,
+ g_base_arr => g_base_arr,
+ g_width_arr => g_width_arr,
+ g_rd_latency_arr => g_rd_latency_arr,
+ g_waitrequest_arr => g_waitrequest_arr,
+ g_pipeline_mosi => g_pipeline_mosi,
+ g_pipeline_miso_rdval => g_pipeline_miso_rdval,
+ g_pipeline_miso_wait => g_pipeline_miso_wait
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+ slave_mosi_arr => bus_mosi_arr,
+ slave_miso_arr => bus_miso_arr
+ );
+
+ -- The MM bus interface with the MM slaves
+ gen_slave_ports : FOR I IN 0 TO g_nof_slaves-1 GENERATE
+ -- Rewire not connected slaves and slave that do not need mosi flow control via miso.waitrequest
+ u_slave_enable : ENTITY work.mm_slave_enable
+ GENERIC MAP (
+ g_enable => TRUE,
+ g_waitrequest => g_waitrequest_arr(I),
+ g_rd_latency => g_rd_latency_arr(I)
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ -- MM input RL = 1
+ in_mosi => bus_mosi_arr(I),
+ in_miso => bus_miso_arr(I),
+ -- MM output RL = 0
+ out_mosi => slave_mosi_arr(I),
+ out_miso => slave_miso_arr(I)
+ );
END GENERATE;
-
- gen_multiple : IF g_nof_slaves>1 GENERATE
- -- Detect which slave in the array is addressed
- p_index : PROCESS(master_mosi)
- VARIABLE v_base : NATURAL;
- BEGIN
- index_pipeline(0) <= g_nof_slaves; -- default index of none existing slave
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- v_base := TO_UINT(master_mosi.address(c_mm_bus_addr_w-1 DOWNTO g_width_arr(I)));
- ASSERT g_base_arr(I) MOD 2**g_width_arr(I) = 0 REPORT "Slave base address must be a multiple of the slave width." SEVERITY FAILURE;
- IF v_base = g_base_arr(I) / 2**g_width_arr(I) THEN
- index_pipeline(0) <= I; -- return index of addressed slave
- EXIT;
- END IF;
- END LOOP;
- END PROCESS;
-
- index_pipeline(1 TO c_index_latency_max) <= index_pipeline(0 TO c_index_latency_max-1) WHEN rising_edge(mm_clk);
-
- -- Master access, can be write or read
- p_slave_mosi_arr : PROCESS(master_mosi, index_pipeline)
- BEGIN
- slave_mosi_arr_comb <= (OTHERS=>master_mosi); -- default assign to all, to avoid latches
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- slave_mosi_arr_comb(I).rd <= '0';
- slave_mosi_arr_comb(I).wr <= '0';
- IF I = index_pipeline(0) THEN -- check index for read or write access
- slave_mosi_arr_comb(I).rd <= master_mosi.rd;
- slave_mosi_arr_comb(I).wr <= master_mosi.wr;
- END IF;
- END LOOP;
- END PROCESS;
- -- FIX ME: g_pipeline_mosi in combination with g_pipeline_miso_wait
- slave_mosi_arr_reg <= slave_mosi_arr_comb WHEN rising_edge(mm_clk);
-
- slave_mosi_arr <= slave_mosi_arr_comb WHEN g_pipeline_mosi = FALSE ELSE slave_mosi_arr_reg;
-
-
- -- Slave response to read access after read latency mm_clk cycles
- p_master_miso_comb : PROCESS(slave_miso_arr, index_pipeline)
- VARIABLE v_rd_latency : NATURAL;
- BEGIN
- master_miso_comb <= c_mem_miso_rst; -- default clear, to avoid latches
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- v_rd_latency := c_pipeline_mosi + g_rd_latency_arr(I);
- IF I = index_pipeline(v_rd_latency) THEN -- check index for read response
- master_miso_comb <= slave_miso_arr(I);
- END IF;
- END LOOP;
- FOR I IN 0 TO g_nof_slaves-1 LOOP
- IF I = index_pipeline(0) THEN -- check index for waitrequest
- master_miso_comb.waitrequest <= slave_miso_arr(I).waitrequest;
- END IF;
- END LOOP;
- END PROCESS;
-
- master_miso_reg <= master_miso_comb WHEN rising_edge(mm_clk);
-
- p_master_miso : PROCESS(master_miso_comb, master_miso_reg)
- BEGIN
- master_miso <= master_miso_comb; -- default no miso pipelining
- IF g_pipeline_miso_rdval THEN
- master_miso.rddata <= master_miso_reg.rddata;
- master_miso.rdval <= master_miso_reg.rdval;
- END IF;
- IF g_pipeline_miso_wait THEN
- master_miso.waitrequest <= master_miso_reg.waitrequest;
- END IF;
- END PROCESS;
-
- END GENERATE;
-
-END rtl;
+END str;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
index 0f2004618996296869492ed7badca472b843b59a..45028964164cbee349a948af00b4e3baaf046640 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
@@ -54,7 +54,7 @@ USE common_lib.tb_common_mem_pkg.ALL;
ENTITY tb_mm_bus IS
GENERIC (
- g_nof_slaves : POSITIVE := 2; -- Number of slave memory interfaces on the MM bus array.
+ g_nof_slaves : POSITIVE := 1; -- Number of slave memory interfaces on the MM bus array.
g_base_offset : NATURAL := 0; -- Address of first slave on the MM bus
g_width_w : POSITIVE := 4; -- Address width of each slave memory in the MM bus array.
g_rd_latency : NATURAL := 1; -- Read latency of the slaves
@@ -79,14 +79,13 @@ ARCHITECTURE tb OF tb_mm_bus IS
CONSTANT c_base_arr : t_nat_natural_arr := array_init(g_base_offset, g_nof_slaves, c_slave_span); -- Address base per slave
CONSTANT c_width_arr : t_nat_natural_arr := array_init( g_width_w, g_nof_slaves); -- Address width per slave
CONSTANT c_rd_latency_arr : t_nat_natural_arr := array_init( g_rd_latency, g_nof_slaves); -- Read latency per slave
+ CONSTANT c_waitrequest_arr : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_slaves); -- Flow control per slave
CONSTANT c_bus_pipelining : BOOLEAN := g_pipeline_mosi OR g_pipeline_miso_rdval OR g_pipeline_miso_wait;
CONSTANT c_pipeline_mosi : NATURAL := sel_a_b(g_pipeline_mosi, 1, 0);
CONSTANT c_pipeline_miso_rdval : NATURAL := sel_a_b(g_pipeline_miso_rdval, 1, 0);
CONSTANT c_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_miso_wait, 1, 0);
CONSTANT c_read_latency : NATURAL := c_pipeline_mosi + g_rd_latency + c_pipeline_miso_rdval;
-
- CONSTANT c_adapt_waitrequest : BOOLEAN := g_waitrequest AND g_pipeline_miso_wait;
CONSTANT c_data_w : NATURAL := 32;
CONSTANT c_test_ram : t_c_mem := (latency => g_rd_latency,
@@ -98,15 +97,12 @@ ARCHITECTURE tb OF tb_mm_bus IS
SIGNAL mm_clk : STD_LOGIC := '1';
SIGNAL tb_end : STD_LOGIC;
+ SIGNAL cnt_rd : NATURAL := 0;
+ SIGNAL cnt_rdval : NATURAL := 0;
+
-- MM bus
SIGNAL master_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL master_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL bus_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
- SIGNAL bus_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst);
- -- MM slaves with waitrequest latency adapters for ports that have pipelined flow control
- SIGNAL busw_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
- SIGNAL busw_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst);
- -- MM slaves with waitrequest for ports that are enabled and NC for ports that are not connected
SIGNAL slave_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
SIGNAL slave_miso_arr : t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst);
SIGNAL ram_mosi_arr : t_mem_mosi_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_mosi_rst);
@@ -119,8 +115,6 @@ ARCHITECTURE tb OF tb_mm_bus IS
BEGIN
- ASSERT NOT(g_nof_slaves=1 AND c_bus_pipelining=TRUE) REPORT "No support for MM bus pipelining with g_nof_slaves=1, because then the mm_bus reduces to wires." SEVERITY FAILURE;
-
mm_clk <= NOT mm_clk OR tb_end AFTER mm_clk_period/2;
mm_rst <= '1', '0' AFTER mm_clk_period*5;
@@ -131,7 +125,7 @@ BEGIN
VARIABLE v_wrdata : INTEGER; -- write data
BEGIN
tb_end <= '0';
- master_mosi <= c_mem_mosi_rst;
+ master_mosi <= c_mem_mosi_rst;
-- Wait until reset is released
proc_common_wait_until_low(mm_clk, mm_rst);
@@ -154,12 +148,18 @@ BEGIN
FOR vJ IN 0 TO c_slave_span-1 LOOP
proc_mem_mm_bus_rd(g_base_offset + vI*c_slave_span + vJ, mm_clk, master_miso, master_mosi);
--proc_common_wait_some_cycles(mm_clk, c_read_latency); -- not needed, see p_verify
+ cnt_rd <= cnt_rd + 1;
END LOOP;
proc_common_wait_some_cycles(mm_clk, 10);
END LOOP;
END LOOP;
proc_common_wait_some_cycles(mm_clk, 10);
+
+ -- Verify that test has indeed ran
+ WAIT FOR 1 ns; -- wait 1 ns to ensure that assert report appears at end of transcript log
+ ASSERT cnt_rdval = cnt_rd AND cnt_rdval > 0 REPORT "Wrong number of rdval" SEVERITY ERROR;
+
tb_end <= '1';
WAIT;
END PROCESS;
@@ -176,6 +176,7 @@ BEGIN
BEGIN
WAIT UNTIL rising_edge(mm_clk);
IF master_miso.rdval = '1' THEN
+ cnt_rdval <= cnt_rdval + 1;
v_rddata := TO_UINT(master_miso.rddata(c_data_w-1 DOWNTO 0));
IF v_rddata /= v_expdata THEN
REPORT "Error! Readvalue is not as expected" SEVERITY ERROR;
@@ -184,7 +185,6 @@ BEGIN
END IF;
END PROCESS;
-
-----------------------------------------------------------------------------
-- The MM bus
-----------------------------------------------------------------------------
@@ -194,57 +194,20 @@ BEGIN
g_base_arr => c_base_arr,
g_width_arr => c_width_arr,
g_rd_latency_arr => c_rd_latency_arr,
+ g_waitrequest_arr => c_waitrequest_arr,
g_pipeline_mosi => g_pipeline_mosi,
g_pipeline_miso_rdval => g_pipeline_miso_rdval,
g_pipeline_miso_wait => g_pipeline_miso_wait
)
PORT MAP (
+ mm_rst => mm_rst,
mm_clk => mm_clk,
master_mosi => master_mosi,
master_miso => master_miso,
- slave_mosi_arr => bus_mosi_arr,
- slave_miso_arr => bus_miso_arr
+ slave_mosi_arr => slave_mosi_arr,
+ slave_miso_arr => slave_miso_arr
);
- -----------------------------------------------------------------------------
- -- The MM bus interface with the MM slaves
- -----------------------------------------------------------------------------
- gen_slave_ports : FOR I IN 0 TO g_nof_slaves-1 GENERATE
- -- Adapt the miso.waitrequest for slaves that use mosi flow control if the miso.waitrequest is pipelined in the mm_bus
- u_slave_latency_adapter : ENTITY work.mm_latency_adapter
- GENERIC MAP (
- g_adapt => c_adapt_waitrequest
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- -- MM input RL = 1
- in_mosi => bus_mosi_arr(I),
- in_miso => bus_miso_arr(I),
- -- MM output RL = 0
- out_mosi => busw_mosi_arr(I),
- out_miso => busw_miso_arr(I)
- );
-
- -- Rewire not connected slaves and slave that do not need mosi flow control via miso.waitrequest
- u_slave_enable : ENTITY work.mm_slave_enable
- GENERIC MAP (
- g_enable => TRUE,
- g_waitrequest => g_waitrequest,
- g_rd_latency => c_rd_latency_arr(I)
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- -- MM input RL = 1
- in_mosi => busw_mosi_arr(I),
- in_miso => busw_miso_arr(I),
- -- MM output RL = 0
- out_mosi => slave_mosi_arr(I),
- out_miso => slave_miso_arr(I)
- );
- END GENERATE;
-
-----------------------------------------------------------------------------
-- Model the MM slaves
-----------------------------------------------------------------------------
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
index 5902094761e95e346e6fcdcf7d52886ff9cd4e12..a741aeaba467b45c61398b85083c9211c75157ff 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
@@ -77,6 +77,7 @@ ARCHITECTURE tb OF tb_mm_master_mux IS
CONSTANT c_bus_pipeline_miso_wait : NATURAL := sel_a_b(g_pipeline_bus_miso_wait, 1, 0);
CONSTANT c_ram_rd_latency : NATURAL := 1;
CONSTANT c_ram_rd_latency_arr : t_nat_natural_arr := array_init(c_ram_rd_latency, g_nof_masters);
+ CONSTANT c_waitrequest_arr : t_nat_boolean_arr := array_init(g_waitrequest, g_nof_masters);
CONSTANT c_read_latency : NATURAL := c_bus_pipeline_mosi + c_ram_rd_latency + c_bus_pipeline_miso_rdval;
@@ -161,6 +162,7 @@ BEGIN
g_base_arr => g_base_arr,
g_width_arr => g_width_arr,
g_rd_latency_arr => c_ram_rd_latency_arr,
+ g_waitrequest_arr => c_waitrequest_arr,
g_pipeline_mosi => g_pipeline_bus_mosi,
g_pipeline_miso_rdval => g_pipeline_bus_miso_rdval,
g_pipeline_miso_wait => g_pipeline_bus_miso_wait
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
index 9e40c5da110607506f608ff4cef1dabe609dafae..9614cff4f5f2cf9a0a0caeaba7c769c13d1ed39f 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
@@ -48,17 +48,17 @@ BEGIN
-- g_pipeline_miso_rdval : BOOLEAN := TRUE;
-- g_pipeline_miso_wait : BOOLEAN := FALSE
- u_no_pipe : ENTITY work.tb_mm_bus GENERIC MAP (16, 0, 3, 1, FALSE, FALSE, FALSE, FALSE);
- u_no_pipe_base_offset : ENTITY work.tb_mm_bus GENERIC MAP (16, 3*2**4, 4, 1, FALSE, FALSE, FALSE, FALSE);
- u_pipe_mosi : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, FALSE, TRUE, FALSE, FALSE);
- u_pipe_mosi_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, FALSE, TRUE, TRUE, FALSE);
- u_waitrequest_no_pipe : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, FALSE, FALSE, FALSE);
- u_waitrequest_pipe_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, FALSE, TRUE, FALSE);
- u_waitrequest_pipe_miso_rdval2 : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 2, TRUE, FALSE, TRUE, FALSE);
- u_waitrequest_pipe_miso_wait : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, FALSE, FALSE, TRUE);
+ --u_no_pipe : ENTITY work.tb_mm_bus GENERIC MAP (16, 0, 3, 1, FALSE, FALSE, FALSE, FALSE);
+ --u_no_pipe_base_offset : ENTITY work.tb_mm_bus GENERIC MAP (16, 3*2**4, 4, 1, FALSE, FALSE, FALSE, FALSE);
+ --u_pipe_mosi : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, FALSE, TRUE, FALSE, FALSE);
+ --u_pipe_mosi_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, FALSE, TRUE, TRUE, FALSE);
+ --u_waitrequest_no_pipe : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, FALSE, FALSE, FALSE);
+ --u_waitrequest_pipe_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 1, TRUE, FALSE, TRUE, FALSE);
+ --u_waitrequest_pipe_miso_rdval2 : ENTITY work.tb_mm_bus GENERIC MAP ( 3, 0, 4, 2, TRUE, FALSE, TRUE, FALSE);
+ --u_waitrequest_pipe_miso_wait : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, FALSE, FALSE, TRUE);
-- To do:
- -- . supporting waitrequest with pipelined mosi may require a component similar to dp_pipeline
+ u_waitrequest_pipe_mosi : ENTITY work.tb_mm_bus GENERIC MAP ( 1, 0, 4, 1, TRUE, TRUE, FALSE, FALSE);
--u_waitrequest_pipe_mosi : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, FALSE, FALSE);
--u_waitrequest_pipe_mosi_miso_rdval : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, TRUE, FALSE);
--u_waitrequest_pipe_mosi_miso_wait : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, FALSE, TRUE);