From 39ee6fdb794474e6bfa125281a92d5818ab5e40b Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 26 Sep 2014 13:48:56 +0000
Subject: [PATCH] Added the compile IP scripts specified by key
'modelsim_compile_ip_files' to the project files in the mpf.
---
tools/oneclick/base/modelsim_config.py | 42 ++++++++++++++++++++------
1 file changed, 32 insertions(+), 10 deletions(-)
diff --git a/tools/oneclick/base/modelsim_config.py b/tools/oneclick/base/modelsim_config.py
index 11efb4b03c..62a9758eea 100644
--- a/tools/oneclick/base/modelsim_config.py
+++ b/tools/oneclick/base/modelsim_config.py
@@ -114,8 +114,10 @@ class ModelsimConfig(hdl_config.HdlConfig):
filePathName = os.path.join(file_path, file_name)
with open(filePathName, 'w') as fp:
for fpn in compile_ip_files:
- fn = os.path.basename(fpn)
- fp.write('%s ' % fn) # write the file name without the full path to it
+ # Write the expanded file path name for <lib_name>_lib_compile_ip.txt so that it can be executed directly from its location in SVN using the Modelsim "do"-command in the commands.do.
+ # An alternative would be to write the basename, so only <lib_name>_lib_compile_ip.txt, but that would require copying the basename file to the mpf build directory
+ efpn = os.path.expandvars(fpn)
+ fp.write('%s ' % efpn)
def create_modelsim_project_file(self, technologyNames, lib_names=None):
"""Create the Modelsim project file for all technology libraries and RTL HDL libraries.
@@ -157,36 +159,55 @@ class ModelsimConfig(hdl_config.HdlConfig):
# . others modelsim default libs
model_tech_dir = os.path.expandvars(self.tool.get_key_values('model_tech_dir'))
fp.write('others = %s\n' % os.path.join(model_tech_dir, 'modelsim.ini'))
+
# Write [Project] section for all used libraries
fp.write('[Project]\n')
fp.write('Project_Version = 6\n') # must be >= 6 to fit all
fp.write('Project_DefaultLib = work\n')
fp.write('Project_SortMethod = unused\n')
- # - hdl files
+
+ # - project files
synth_files = lib_dict['synth_files'].split()
test_bench_files = lib_dict['test_bench_files'].split()
- sim_files = synth_files + test_bench_files
- fp.write('Project_Files_Count = %d\n' % len(sim_files))
+ project_files = synth_files + test_bench_files
+ if 'modelsim_compile_ip_files' in lib_dict:
+ compile_ip_files = lib_dict['modelsim_compile_ip_files'].split()
+ project_files += compile_ip_files
+ fp.write('Project_Files_Count = %d\n' % len(project_files))
lib_path = self.libs.get_filePath(lib_dict)
- for i, fn in enumerate(sim_files):
+ for i, fn in enumerate(project_files):
filePathName = cm.expand_file_path_name(fn, lib_path)
fp.write('Project_File_%d = %s\n' % (i, filePathName))
- project_file_p_defaults = 'vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 vlog_1995compat 0 last_compile 0 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn3 1 vlog_vopt {} cover_optlevel 3 voptflow 1 vhdl_options {} vhdl_warn4 1 toggle - ood 0 vhdl_warn5 1 cover_noshort 0 compile_to work cover_nosub 0 dont_compile 0 vhdl_use93 2002 cover_stmt 1'
+ project_file_p_defaults_vhdl = 'vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 vlog_1995compat 0 last_compile 0 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn3 1 vlog_vopt {} cover_optlevel 3 voptflow 1 vhdl_options {} vhdl_warn4 1 toggle - ood 0 vhdl_warn5 1 cover_noshort 0 compile_to work cover_nosub 0 dont_compile 0 vhdl_use93 2002 cover_stmt 1'
+ project_file_p_defaults_tcl = 'last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1'
project_folders = []
+ offset = 0
nof_synth_files = len(synth_files)
if nof_synth_files>0:
project_folders.append('synth_files')
for i in range(nof_synth_files):
- fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (i, project_folders[-1], i, project_file_p_defaults))
+ fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_vhdl))
+ offset = nof_synth_files
nof_test_bench_files = len(test_bench_files)
if nof_test_bench_files>0:
project_folders.append('test_bench_files')
- for j in range(nof_test_bench_files):
- fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (nof_synth_files+j, project_folders[-1], nof_synth_files+j, project_file_p_defaults))
+ for i in range(nof_test_bench_files):
+ fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_vhdl))
+ offset += nof_test_bench_files
+ if 'modelsim_compile_ip_files' in lib_dict:
+ nof_compile_ip_files = len(compile_ip_files)
+ if nof_compile_ip_files>0:
+ project_folders.append('compile_ip_files')
+ for i in range(nof_compile_ip_files):
+ fp.write('Project_File_P_%d = folder %s compile_order %d %s\n' % (offset+i, project_folders[-1], offset+i, project_file_p_defaults_tcl))
+ offset += nof_compile_ip_files
+
+ # - project folders
fp.write('Project_Folder_Count = %d\n' % len(project_folders))
for i, fd in enumerate(project_folders):
fp.write('Project_Folder_%d = %s\n' % (i, fd))
fp.write('Project_Folder_P_%d = folder {Top Level}\n' % i)
+
# - simulation configurations
fp.write('Project_Sim_Count = %d\n' % len(test_bench_files))
project_sim_p_defaults = 'Generics {} timing default -std_output {} -nopsl 0 +notimingchecks 0 -L {} selected_du {} -hazards 0 -sdf {} ok 1 -0in 0 -nosva 0 +pulse_r {} -absentisempty 0 -multisource_delay {} +pulse_e {} vopt_env 1 -coverage 0 -sdfnoerror 0 +plusarg {} -vital2.2b 0 -t default -memprof 0 is_vopt_flow 0 -noglitch 0 -nofileshare 0 -wlf {} -assertdebug 0 +no_pulse_msg 0 -0in_options {} -assertfile {} -sdfnowarn 0 -Lf {} -std_input {}'
@@ -203,6 +224,7 @@ class ModelsimConfig(hdl_config.HdlConfig):
fName = os.path.basename(fn)
tbName = os.path.splitext(fName)[0]
fp.write('Project_Sim_P_%d = folder {Top Level} additional_dus work.%s %s %s %s\n' % (i, tbName, project_sim_p_defaults, project_sim_p_otherargs, project_sim_p_optimization))
+
# Write [vsim] section
fp.write('[vsim]\n')
fp.write('RunLength = 0 ps\n')
--
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