diff --git a/applications/compaan/libraries/ipcore_trace/.project b/applications/compaan/libraries/ipcore_trace/.project
deleted file mode 100644
index fca12b0437712675fc7dbc47da97dcc2f918ecbe..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/.project
+++ /dev/null
@@ -1,12 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>ipcore_trace</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- </buildSpec>
- <natures>
- <nature>com.compaandesign.compiler.resource.natures.CompaanProjectNature</nature>
- </natures>
-</projectDescription>
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg
deleted file mode 100644
index 59e31486a09b20141c17d8efd131375996cc3369..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-hdl_lib_name = compaandesign_com_common_altera_1
-hdl_library_clause_name = compaandesign_com_common_altera_1_lib
-hdl_lib_uses_synth = common dp
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/fsl_v20.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd
deleted file mode 100644
index e407c5df5c15c6e42904a18b55a2e4b2151e03b5..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd
+++ /dev/null
@@ -1,187 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- fsl_v20.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: fsl_v20.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2003-02-13 First Version
--- satish 2004-03-03 New Version
--- rolandp 2006-08-20 BRAM in asynch mode
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library ieee,common_lib,dp_lib;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-use ieee.math_real.all;
-
-entity fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end entity fsl_v20;
-
-architecture IMP of fsl_v20 is
-
- signal sl_full : std_logic;
- signal FSL_S_Empty : std_logic;
- signal snk_out : t_dp_siso;
- signal snk_in : t_dp_sosi;
- signal src_in : t_dp_siso;
- signal src_out : t_dp_sosi;
-
-begin
-
- FSL_M_Full <= not snk_out.ready;
- --FSL_S_Exists <= not FSL_S_Empty and src_out.valid;
- FSL_S_Exists <= src_out.valid;
- snk_in.data(C_FSL_DWIDTH-1 downto 0) <= FSL_M_Data;
- FSL_S_Data <= src_out.data(C_FSL_DWIDTH-1 downto 0);
- snk_in.valid <= FSL_M_Write;
- src_in.ready <= FSL_S_Read;
-
- u_dp_fifo_core : ENTITY dp_lib.dp_fifo_sc
- GENERIC MAP (
- g_data_w => C_FSL_DWIDTH, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_bsn_w => 1,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_bsn => FALSE,
- g_use_empty => FALSE,
- g_use_channel => FALSE,
- g_use_error => FALSE,
- g_use_sync => FALSE,
- g_use_ctrl => FALSE, -- sop & eop
- g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => C_FSL_DEPTH, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin => 4, -- >=4, Nof words below max (full) at which fifo is considered almost full
- g_fifo_rl => 0
- )
- PORT MAP (
- rst => SYS_Rst,
- clk => FSL_Clk,
- -- Monitor FIFO filling
- wr_ful => sl_full,
- usedw => open,
- rd_emp => FSL_S_Empty,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
-
-end architecture IMP;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd.bak b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd.bak
deleted file mode 100644
index 096f7ef40195318da53d7267cc9750a4129784d5..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/src/vhdl/fsl_v20.vhd.bak
+++ /dev/null
@@ -1,187 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- fsl_v20.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: fsl_v20.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2003-02-13 First Version
--- satish 2004-03-03 New Version
--- rolandp 2006-08-20 BRAM in asynch mode
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library ieee,common_lib,dp_lib;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-use ieee.math_real.all;
-
-entity fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end entity fsl_v20;
-
-architecture IMP of fsl_v20 is
-
- signal sl_full : std_logic;
- signal FSL_S_Empty : std_logic;
- signal snk_out : t_dp_siso;
- signal snk_in : t_dp_sosi;
- signal src_in : t_dp_siso;
- signal src_out : t_dp_sosi;
-
-begin
-
- FSL_M_Full <= not snk_out.ready;
- --FSL_S_Exists <= not FSL_S_Empty and src_out.valid;
- FSL_S_Exists <= src_out.valid;
- snk_in.data(C_FSL_DWIDTH-1 downto 0) <= FSL_M_Data;
- FSL_S_Data <= src_out.data(C_FSL_DWIDTH-1 downto 0);
- snk_in.valid <= FSL_M_Write;
- src_in.ready <= FSL_S_Read;
-
- u_dp_fifo_core : ENTITY dp_lib.dp_fifo_sc
- GENERIC MAP (
- g_data_w => C_FSL_DWIDTH, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_bsn_w => 1,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_bsn => FALSE,
- g_use_empty => FALSE,
- g_use_channel => FALSE,
- g_use_error => FALSE,
- g_use_sync => FALSE,
- g_use_ctrl => FALSE, -- sop & eop
- g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => C_FSL_DEPTH, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin => 1, -- >=4, Nof words below max (full) at which fifo is considered almost full
- g_fifo_rl => 0
- )
- PORT MAP (
- rst => SYS_Rst,
- clk => FSL_Clk,
- -- Monitor FIFO filling
- wr_ful => sl_full,
- usedw => open,
- rd_emp => FSL_S_Empty,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
-
-end architecture IMP;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg
deleted file mode 100644
index 9a26746e59ebc710762f1f6374bd0b69f1dfaaed..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-hdl_lib_name = compaandesign_com_common_common_1
-hdl_library_clause_name = compaandesign_com_common_common_1_lib
-hdl_lib_uses_synth =
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/hw_node_pkg.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd
deleted file mode 100644
index 6a61da397792225e436fc6271b5df1b279e95292..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/src/vhdl/hw_node_pkg.vhd
+++ /dev/null
@@ -1,126 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
---
--- This file, or parts of it, or modified versions of it, may not be
--- copied, reproduced or transmitted in any form, including
--- reprinting, translation, photocopying or microfilming, or by any
--- means, electronic, mechanical or otherwise, or stored in a
--- retrieval system, or used for any purpose, without the prior
--- written permission of all Owners unless it is explicitly marked as
--- having Classification `Public'.
---
--- Classification: Restricted.
---
--- Owners of this file give notice:
--- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
--- All rights, including copyrights, reserved.
---
--- This file contains or may contain restricted information and is
--- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
--- Notice(s) above do not evidence any actual or intended publication
--- of such source code. This file is additionally subject to the
--- conditions listed in the RESTRICTIONS file and is with NOWARRANTY.
---
--- END OF COPYRIGHT NOTICE
---
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
---USE IEEE.numeric_std.all;
-
---library nodepack;
-package hw_node_pkg is
- type t_counter_step is array (0 to 10) of natural range 1 to 32;
- type t_counter_width is array (0 to 10) of natural range 1 to 32; -- each number represents the bit-width of a counter
- --
- --type t_par_values is array (0 to 10) of integer; -- each number represents the default value of a parameter
- type t_par is record
- val_min : integer;
- val_max : integer;
- val_def : integer;
- bitwidth : natural;
- end record;
-
- type t_par_vector is array (natural range<>) of t_par;
-
-
- Function b2std(b : boolean) return std_logic;
- function int2slv(int_value : integer; size: integer) return std_logic_vector;
- function slv2int(vect : std_logic_vector; size : integer) return integer;
- --Function modulo2(a:integer; b:integer) return integer;
- Function maxf(left: integer; right: integer) return integer;
- Function minf(left: integer; right: integer) return integer;
-
-end hw_node_pkg;
-
-package body hw_node_pkg is
-
- Function b2std(b : boolean) return std_logic is
- begin
- if b then
- return '1';
- else
- return '0';
- end if;
- end b2std;
-
------------------------------------------------------------------------------------
-
- Function int2slv(int_value : integer; size : integer) return std_logic_vector is
- variable result : std_logic_vector(size-1 downto 0);
- begin
- for i in 0 to size-1 loop
- if ((int_value/(2**i)) rem 2) = 0 then
- result(i) := '0';
- else
- result(i) := '1';
- end if;
- end loop;
- return result;
- end int2slv;
-
------------------------------------------------------------------------------------
-
- function slv2int(vect : std_logic_vector; size : integer) return integer is
-
- variable result : integer range (2**size)-1 downto 0;
- begin
- result := 0;
- for i in 0 to size-1 loop
-
- if( vect(i) = '1' ) then
- result := result + 2**i;
- end if;
-
- end loop;
- return result;
- end slv2int;
-
------------------------------------------------------------------------------------
-
- --Function modulo2(a:integer; b:integer) return integer is
- --variable eval :std_logic_vector(7 downto 0);
- --begin
- -- eval := (int2slv(a, 8) and int2slv(1, 8)) xor int2slv(b,8);
- -- return slv2int(eval,8);
- --end modulo2;
-
------------------------------------------------------------------------------------
-
- Function maxf(left: integer; right:integer) return integer is
- begin
- if left > right then return left;
- else return right;
- end if;
- end maxf;
-
------------------------------------------------------------------------------------
-
- Function minf(left: integer; right:integer) return integer is
- begin
- if left < right then return left;
- else return right;
- end if;
- end minf;
-
-end hw_node_pkg;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg
deleted file mode 100644
index 0e619a305d96c350893596fb4c43a7be05dc0dfa..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-hdl_lib_name = compaandesign_com_common_const_connector_1
-hdl_library_clause_name = compaandesign_com_common_const_connector_1_lib
-hdl_lib_uses_synth =
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/const_connector.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd
deleted file mode 100644
index 0bcbf3ecc6ace7d13aa14222cb5af91d9ccace99..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/src/vhdl/const_connector.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
-
-------------------------------------------------------------------------------
--- Filename: fsl_const
--- Version: 1.00.a
--- Description: Example FSL core (VHDL).
--- Date: Mon May 24 13:16:55 2010 (by Create and Import Peripheral Wizard)
--- VHDL Standard: VHDL'93
-------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port: "*_i"
--- device pins: "*_pin"
--- ports: "- Names begin with Uppercase"
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>"
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-------------------------------------------------------------------------------
--- Entity Section
-------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------
--- Entity Section
-------------------------------------------------------------------------------
-
-entity common_const_connector is
- generic (
- C_FSL_CONST : integer := 0;
- C_FSL_DWIDTH : integer := 31
- );
- port
- (
- FSL_M_CLK : out std_logic;
- FSL_M_Wr : out std_logic;
- FSL_M_Dout : out std_logic_vector(C_FSL_DWIDTH downto 0);
- FSL_M_CTRL : out std_logic;
- FSL_M_Full : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
-
- );
-end common_const_connector;
-
-------------------------------------------------------------------------------
--- Architecture Section
-------------------------------------------------------------------------------
-
-architecture RTL of common_const_connector is
-begin
- FSL_M_CLK <= '0';
- FSL_M_Dout <= STD_LOGIC_VECTOR(TO_SIGNED(C_FSL_CONST,C_FSL_DWIDTH+1));
- FSL_M_CTRL <= '0';
- FSL_M_Wr <= '1';
-end architecture RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg
deleted file mode 100644
index a0dfc627c1e5e6ffcfaa949c93632b1dca4cb3b2..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-hdl_lib_name = compaandesign_com_common_extern_connector_1
-hdl_library_clause_name = compaandesign_com_common_extern_connector_1_lib
-hdl_lib_uses_synth =
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/extern_connector.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd
deleted file mode 100644
index fe6367988ad45e5dcdffd3ff72c8146cae2a009c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/src/vhdl/extern_connector.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
---
--- This file, or parts of it, or modified versions of it, may not be
--- copied, reproduced or transmitted in any form, including
--- reprinting, translation, photocopying or microfilming, or by any
--- means, electronic, mechanical or otherwise, or stored in a
--- retrieval system, or used for any purpose, without the prior
--- written permission of all Owners unless it is explicitly marked as
--- having Classification `Public'.
---
--- Classification: Restricted.
---
--- Owners of this file give notice:
--- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
--- All rights, including copyrights, reserved.
---
--- This file contains or may contain restricted information and is
--- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
--- Notice(s) above do not evidence any actual or intended publication
--- of such source code. This file is additionally subject to the
--- conditions listed in the RESTRICTIONS file and is with NOWARRANTY.
---
--- END OF COPYRIGHT NOTICE
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity extern_connector is
- generic (
- RESET_HIGH : natural := 1;
- C_FSL_DWIDTH : natural := 31
- );
- port (
- CLK : in std_logic;
- RST : in std_logic;
- --
- -- ============================================
- -- = External Connector interface (INPUT)
- -- ============================================
- -- SRC (FSL_S Interface)
- FSL_S_Din : in STD_LOGIC_VECTOR(C_FSL_DWIDTH downto 0);
- FSL_S_CTRL : in STD_LOGIC;
- FSL_S_Rd : out STD_LOGIC;
- FSL_S_Exist : in STD_LOGIC;
- FSL_S_CLK : out std_logic;
- --
- -- SINK (FSL_M Interface)
- FSL_M_Dout : out STD_LOGIC_VECTOR(C_FSL_DWIDTH downto 0);
- FSL_M_CTRL : out STD_LOGIC;
- FSL_M_Wr : out STD_LOGIC;
- FSL_M_Full : in STD_LOGIC;
- FSL_M_CLK : out std_logic
- );
-end extern_connector;
-
-architecture STRUCTURE of extern_connector is
-
- signal ready : std_logic;
-
-begin
- ready <= FSL_S_Exist and not FSL_M_Full;
- FSL_S_Rd <= ready;
- FSL_M_Wr <= ready;
- FSL_M_CTRL <= FSL_S_CTRL;
- FSL_M_Dout <= FSL_S_Din;
-end architecture STRUCTURE;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg
deleted file mode 100644
index cea759101756a09041a0b1a27edd8e859795f8b6..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = compaandesign_com_common_fifo_1
-hdl_library_clause_name = compaandesign_com_common_fifo_1_lib
-hdl_lib_uses_synth = compaandesign_com_common_altera_1
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/async_fifo_bram.vhd
- src/vhdl/async_fifo.vhd
- src/vhdl/fsl_v20.vhd
- src/vhdl/gen_srlfifo.vhd
- src/vhdl/gen_sync_bram.vhd
- src/vhdl/gen_sync_dpram.vhd
- src/vhdl/sync_fifo.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/async_fifo.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/async_fifo.vhd
deleted file mode 100644
index b24bdb7814319255cf045ca608208ad591d05abc..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/async_fifo.vhd
+++ /dev/null
@@ -1,573 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: async_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- Async_FIFO.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: Async_FIFO.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- Async_FIFO.vhd
---
--------------------------------------------------------------------------------
--- Author: goran
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- goran 2003-10-27 First Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.Std_Logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Async_FIFO is
- generic (
- WordSize : Integer := 8;
- MemSize : Integer := 16;
- Protect : Boolean := False
- );
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic
- );
-end Async_FIFO;
-
-architecture VHDL_RTL of ASync_FIFO is
-
- -----------------------------------------------------------------------------
- -- A function which tries to calculate the best Mem_Size and by that the best
- -- counting scheme
- -----------------------------------------------------------------------------
- function Calculate_Right_Mem_Size (Mem_Size : in Natural) return Integer is
- begin -- Calculate_Right_Mem_Size
- case Mem_Size is
- when 0 to 3 =>
- assert false report "To small FIFO" severity failure;
- return 0;
- when 4 to 16 => return 16;
- when 17 to 32 => return 32;
- when 33 to 64 => return 64;
- when 65 to 128 =>
- -- Do not yet need to check if to use the up/down counting scheme since
- -- there is not true 7-bit counter implemented yet
- return ((MemSize+15)/16)*16;
- when others =>
- assert false
- report "Unsupported FIFO Depth (Not yet implemented)"
- severity failure;
- return 0;
- end case;
- end Calculate_Right_Mem_Size;
-
- -----------------------------------------------------------------------------
- -- Create a resolved Boolean type (rboolean)
- -----------------------------------------------------------------------------
-
- -- Create a Boolean array type
- type boolean_array is array (natural range <>) of boolean;
-
- -- Function for resolved boolean
- -- If any boolean in the array is false, then the result is false
- function resolve_boolean( values: in boolean_array ) return boolean is
- variable result: boolean := TRUE;
- begin
- if (values'length = 1) then
- result := values(values'low);
- else
- -- coverage off
- for index in values'range loop
- if values(index) = FALSE then
- result := FALSE;
- end if;
- end loop;
- -- coverage on
- end if;
- return result;
- end function resolve_boolean;
-
- subtype rboolean is resolve_boolean boolean;
-
-
- -- Convert the FIFO memsize to memsizes in steps of 16
- constant True_Mem_Size : Integer := Calculate_Right_Mem_Size(MemSize);
-
--- component Gen_DpRAM
--- generic (
--- Use_Muxes : Boolean := False;
--- Mem_Size : Integer := 36;
--- Addr_Size : Integer := 6;
--- Data_Size : Integer := 16
--- );
--- port (
--- Reset : in Std_Logic;
--- -- Read/Write port 1
--- Addr1 : in Std_Logic_Vector(Addr_Size-1 downto 0);
--- WrClk : in Std_Logic;
--- WE : in Std_Logic;
--- DataIn : in Std_Logic_Vector(Data_Size-1 downto 0);
--- DataOut1 : out Std_Logic_Vector(Data_Size-1 downto 0);
--- -- Read port 2
--- Addr2 : in Std_Logic_Vector(Addr_Size-1 downto 0);
--- DataOut2 : out Std_Logic_Vector(Data_Size-1 downto 0)
--- );
--- end component;
-
- ----------------------------------------------------------------------
- -- Returns the vector size needed to represent the X
- -- The result is > 0
- ----------------------------------------------------------------------
- function Vec_Size( X : in Natural) return Natural is
- variable I : Natural := 1;
- begin
- while (2**I) < X loop
- I := I + 1;
- end loop;
- return I;
- end function Vec_Size;
-
- -- Declare the types and constant counting schemes
- subtype Count_Word is Std_Logic_Vector(3 downto 0);
- type Count_Array_Type is array (integer range <>) of Count_Word;
-
- -- Even if there is four bits for the Cnt8, the fourth bit will never be used
- constant Cnt8 : Count_Array_Type(0 to 7) := ( "0000","0001","0011","0010",
- "0110","0111","0101","0100");
- constant Cnt10 : Count_Array_Type(0 to 9) := ( "0000","1000","1001","0001",
- "0011","0010","0110","0111",
- "0101","0100" );
- constant Cnt12 : Count_Array_Type(0 to 11) := ( "0000","1000","1001","1011",
- "1010","0010","0011","0001",
- "0101","0111","0110","0100" );
- constant Cnt14 : Count_Array_Type(0 to 13) := ( "0000","1000","1100","1101",
- "1001","1011","1010","0010",
- "0011","0001","0101","0111",
- "0110","0100");
- constant Cnt16 : Count_Array_Type(0 to 15) := ( "0000","0001","0011","0010",
- "0110","0100","0101","0111",
- "1111","1110","1100","1101",
- "1001","1011","1010","1000");
-
- -----------------------------------------------------------------------------
- -- A function that do all the boolean equations for a counting scheme
- -- given as a parameter
- -- The synthesis tool will unroll the loops and then do the boolean equation
- -- minimization (hopefully the optimimal).
- -- At present it only handles counting scheme with 4 bits due to the
- -- Count_Array_Type definition
- -----------------------------------------------------------------------------
- function Gen_Counter(Count_Scheme : in Count_Array_Type;
- Up : in Boolean;
- Count : in Std_Logic_Vector)
- return Std_Logic_Vector is
- variable Temp : Std_Logic;
- variable L : Integer range Count_Scheme'Range;
- variable Q : Std_Logic_Vector(Count'Length-1 downto 0);
- variable Q_Temp : Std_Logic_Vector(Count'Length-1 downto 0);
- begin -- Gen_Counter
- Q := Count;
- for G in Q'Range loop
- Q_Temp(G) := '0';
- for I in Count_Scheme'range loop
- if Count_Scheme(I)(G) = '1' then
- if Up then
- L := I - 1;
- else
- if I /= Count_Scheme'High then
- L := I + 1;
- else
- L := Count_Scheme'Low;
- end if;
- end if;
- Temp := '1';
- for J in Q'Range loop
- if Count_Scheme(L)(J) = '1' then
- Temp := Temp and Q(J);
- else
- Temp := Temp and not Q(J);
- end if;
- end loop;
- Q_Temp(G) := Q_Temp(G) or Temp;
- end if;
- end loop; -- I
- end loop; -- G
- return Q_Temp;
- end Gen_Counter;
-
- ----------------------------------------------------------------------
- -- Generate the Address counter for FIFO handling
- -- generates different counters depending of the counter size
- ----------------------------------------------------------------------
- Procedure FIFO_Count( Count : inout Std_Logic_Vector;
- Incr : in Boolean;
- Up : inout Boolean;
- Change : inout Boolean) is
- variable Cnt : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- begin
- if True_Mem_Size = 16 then
- if Incr then
- Res := Gen_Counter(Cnt16,True,Cnt);
- end if;
- elsif True_Mem_Size = 32 then
- if Incr then
- if not Change and
- (( (Cnt(2 downto 0) = "100") and Up) or
- ( (Cnt(2 downto 0) = "000") and not Up)) then
- Res(4) := Cnt(3);
- Res(3) := not Cnt(4);
- Res(2 downto 0) := Cnt(2 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(4 downto 3) := Cnt(4 downto 3);
- Res(2 downto 0) := Gen_Counter(Cnt8,Up,Cnt(2 downto 0));
- end if;
- end if;
- elsif True_Mem_Size = 64 then
- if Incr then
- if not Change and
- (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
- ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
- Res(5) := Cnt(4);
- Res(4) := not Cnt(5);
- Res(3 downto 0) := Cnt(3 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(5 downto 4) := Cnt(5 downto 4);
- Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
- end if;
- end if;
- elsif True_Mem_Size = 128 then
- -- Do a 3-bit grey counter + a 4-bit grey counter
- if Incr then
- if not Change and
- (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
- ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
- Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
- Res(3 downto 0) := Cnt(3 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(6 downto 4) := Cnt(6 downto 4);
- Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
- end if;
- end if;
- else
- assert false
- report "To BIG FIFO (not yet supported)"
- severity failure;
- end if;
- Count := Res;
- end FIFO_Count;
-
- Procedure FIFO_Counter( signal Count : inout Std_Logic_Vector;
- Incr : in Boolean;
- Up : inout Boolean;
- Change : inout Boolean) is
- variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- begin
- FIFO_Count(Res,Incr,Up,Change);
- Count <= Res;
- end FIFO_Counter;
-
- constant Log2_Mem_Size : Integer := Vec_Size(True_Mem_Size);
-
- -- The read and write pointers
- subtype Pointer_Type is Std_Logic_Vector(Log2_Mem_Size-1 downto 0);
- signal Write_Ptr : Pointer_Type;
- signal Read_Ptr : Pointer_Type;
- signal Write_Addr : Pointer_Type;
- signal Read_Addr : Pointer_Type;
-
- signal DataOut1 : Std_Logic_Vector(WordSize-1 downto 0); -- NOT USED
-
- signal Dir_Latched : Boolean;
- signal Direction : Boolean;
- signal Equal : Boolean;
- signal Full_I : Boolean;
- signal Empty_I : Boolean;
- signal Full_Out : Boolean;
- signal Empty_Out : Boolean;
-
- signal Read : rboolean;
- signal Write : rboolean;
-
- -----------------------------------------------------------------------------
- -- Implement the RAM with pure RTL
- -----------------------------------------------------------------------------
- type RAM_TYPE is array (natural range 0 to MemSize-1) of std_logic_vector(WordSize-1 downto 0);
- signal Memory : RAM_TYPE := (others => (others => '0'));
-
-begin
-
- -----------------------------------------------------------------------------
- -- Change the Read and Write pointer to get the FIFO addresses
- -- This will get the four lowest bits from the Read/Write pointers to be the
- -- higest bits in FIFO addresses. This assures that when the FIFO depth is
- -- not a power of 2, that the FIFO addresses is within the FIFO depth range
- -----------------------------------------------------------------------------
- Do_FIFO_Addr : process (Write_Ptr, Read_Ptr)
- begin -- process Do_FIFO_Addr
- Write_Addr(Write_Addr'High downto Write_Addr'High-3) <=
- Write_Ptr(3 downto 0);
- if Write_Ptr'Length > 4 then
- Write_Addr(Write_Addr'High-4 downto Write_Addr'Low) <=
- Write_Ptr(Write_Ptr'High downto 4);
- end if;
- Read_Addr(Read_Addr'High downto Read_Addr'High-3) <=
- Read_Ptr(3 downto 0);
- if Read_Ptr'Length > 4 then
- Read_Addr(Read_Addr'High-4 downto Read_Addr'Low) <=
- Read_Ptr(Read_Ptr'High downto 4);
- end if;
- end process Do_FIFO_Addr;
-
- ----------------------------------------------------------------------
- -- Instansiate the Dual Port memory
- ----------------------------------------------------------------------
- Write_To_Memory: process (WrClk) is
- begin -- process Write_To_Memory
- if WrClk'event and WrClk = '1' then -- rising clock edge
- if WE = '1' then
- Memory(to_integer(unsigned(Write_Addr))) <= DataIn;
- end if;
- end if;
- end process Write_To_Memory;
-
- DataOut1 <= Memory(to_integer(unsigned(Write_Addr)));
- DataOut <= Memory(to_integer(unsigned(Read_Addr)));
-
--- FIFO_MEM : Gen_DpRAM
--- generic map(
--- Use_Muxes => true,
--- Mem_Size => MemSize,
--- Addr_Size => Log2_Mem_Size,
--- Data_Size => WordSize
--- )
--- port map (
--- Reset => Reset,
--- Addr1 => Write_Addr,
--- WrClk => WrClk,
--- WE => WE,
--- DataIn => DataIn,
--- DataOut1 => DataOut1,
--- Addr2 => Read_Addr,
--- DataOut2 => DataOut
--- );
-
- Protect_FIFO : if Protect generate
- Read <= (Rd = '1') and not Empty_Out;
- Write <= (We = '1') and not Full_Out;
- end generate Protect_FIFO;
-
- Non_Protect_FIFO : if not Protect generate
- Read <= (Rd = '1');
- Write <= (We = '1');
- end generate Non_Protect_FIFO;
- ----------------------------------------------------------------------
- -- Read Pointer
- ----------------------------------------------------------------------
- Read_Ptr_Counter : process(Reset,RdClk)
- variable Up : Boolean;
- variable Change : Boolean;
- begin
- if (Reset = '1') then
- Read_Ptr <= (others => '0');
- Up := True;
- Change := False;
- elsif RdClk'Event and RdClk = '1' then
- FIFO_Counter(Read_Ptr,Read,Up,Change);
- end if;
- end process Read_Ptr_Counter;
-
- ----------------------------------------------------------------------
- -- Write Pointer
- ----------------------------------------------------------------------
- Write_Ptr_Counter : process(Reset,WrClk)
- variable Up : Boolean;
- variable Change : Boolean;
- begin
- if (Reset = '1') then
- Write_Ptr <= (others => '0');
- Up := True;
- Change := False;
- elsif WrClk'Event and WrClk = '1' then
- FIFO_Counter(Write_Ptr,Write,Up,Change);
- end if;
- end process Write_Ptr_Counter;
-
- ----------------------------------------------------------------------
- -- Flag handling
- ----------------------------------------------------------------------
-
- -------------------------------------------------------------------------
- -- Dir_Latched is false after reset and then true after the first write
- ---------------------------------------------------------------------------
- Direction_Latch : process(Reset,WE,WrClk)
- begin
- if (Reset = '1') then
- Dir_Latched <= False;
- elsif WrClk'Event and WrClk = '1' then
- Dir_Latched <= Dir_Latched or (WE = '1');
- end if;
- end process Direction_Latch;
-
- -----------------------------------------------------------------------------
- -- Trying to see if the read pointer is catching up the write pointer or
- -- vice verse
- -- The top two bits of the pointers always counts as follows
- -- 00
- -- 01
- -- 11
- -- 10
- -- 00
- -- ..
- -- So if read pointer is one step behind the write pointer => Reset = True
- -- And if write pointer is one step behind the read pointer => Set = True
- -----------------------------------------------------------------------------
- Direction_Proc : process(Read_Ptr, Write_Ptr, Dir_Latched, Direction)
- variable Set : Boolean;
- variable Clear : Boolean;
- variable Read_MSB : Std_Logic_Vector(1 downto 0);
- variable Write_MSB : Std_Logic_Vector(1 downto 0);
- begin
- Read_MSB := Read_Ptr(Read_Ptr'Left) & Read_Ptr(Read_Ptr'Left-1);
- Write_MSB := Write_Ptr(Write_Ptr'Left) & Write_Ptr(Write_Ptr'Left-1);
- if (Read_MSB = "00" and Write_MSB = "01") or
- (Read_MSB = "01" and Write_MSB = "11") or
- (Read_MSB = "11" and Write_MSB = "10") or
- (Read_MSB = "10" and Write_MSB = "00") then
- Clear := True;
- else
- Clear := False;
- end if;
- if (Write_MSB = "00" and Read_MSB = "01") or
- (Write_MSB = "01" and Read_MSB = "11") or
- (Write_MSB = "11" and Read_MSB = "10") or
- (Write_MSB = "10" and Read_MSB = "00") then
- Set := True;
- else
- Set := False;
- end if;
- Direction <= not ((not Dir_Latched) or Clear or not(Set or Direction));
- end process Direction_Proc;
-
- Equal <= (Read_Ptr = Write_Ptr);
- Full_I <= Equal and Direction;
- Empty_I <= Equal and not Direction;
-
- -- Allow Empty to go active directly since the change is due to a read
- -- which means that the Empty_I is synchronized with RdClk.
- -- But is only allow to go inactive when RdClk is High since the transaction
- -- is due to a Write and Empty_I is NOT synchronized with RdClk.
- -- By this way the Empty is not changed state just before rising edge of RdClk
- Empty_DFF : process(Empty_I,RdClk)
- begin
- if Empty_I then
- Empty_Out <= True;
- elsif RdClk'Event and RdClk = '1' then
- Empty_Out <= Empty_I;
- end if;
- end process Empty_DFF;
-
- Exists <= '0' when Empty_Out else '1';
-
- -- See above but for Full and WrClk
- Full_DFF : process(Full_I,WrClk)
- begin
- if Full_I then
- Full_Out <= True;
- elsif WrClk'Event and WrClk = '1' then
- Full_Out <= Full_I;
- end if;
- end process Full_DFF;
-
- Full <= '1' when Full_Out else '0';
-
-end VHDL_RTL;
-
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/async_fifo_bram.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/async_fifo_bram.vhd
deleted file mode 100644
index 3d6d982460490214dbe6aa09350994d7144ad803..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/async_fifo_bram.vhd
+++ /dev/null
@@ -1,429 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: async_fifo_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_bram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: rolandp
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- rolandp 2006 New Versionuse IEEE.std_logic_unsigned.all;
-
---
--- Description:
--- Code to infer asynchronous dual port bram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity Async_FIFO_BRAM is
- generic (
- WordSize : integer := 8;
- MemSize : integer := 16;
- Protect : boolean := false
- );
- port (
- Reset : in std_logic;
- -- Clock region WrClk
- WrClk : in std_logic;
- WE : in std_logic;
- DataIn : in std_logic_vector(WordSize-1 downto 0);
- Full : out std_logic;
- -- Clock region RdClk
- RdClk : in std_logic;
- RD : in std_logic;
- DataOut : out std_logic_vector(WordSize-1 downto 0);
- Exists : out std_logic
- );
-end entity Async_FIFO_BRAM;
-
-architecture IMP of Async_FIFO_BRAM is
-
- attribute ram_style : string;
-
- function Bin2Gray(constant bin : std_logic_vector)
- return std_logic_vector is
- variable gray : std_logic_vector(bin'range);
- begin
- gray(bin'high) := bin(bin'high);
- for I in bin'high - 1 downto bin'low loop
- gray(I) := bin(I + 1) xor bin(I);
- end loop;
- return gray;
- end function Bin2Gray;
-
- function Log2(x : integer) return integer is
- variable i : integer := 0;
- begin
- -- coverage off
- if x = 0 then return 0;
- -- coverage on
- else
- while 2**i < x loop
- i := i+1;
- end loop;
- return i;
- end if;
- end function Log2;
-
- type ram_type is array (2**Log2(MemSize)-1 downto 0) of std_logic_vector(WordSize-1 downto 0);
-
- signal ram_mem : ram_type;
- attribute ram_style of ram_mem : signal is "block";
-
- signal read_enable : std_logic;
- signal write_enable : std_logic;
-
- signal read_allow : std_logic;
- signal write_allow : std_logic;
-
- signal empty_allow : std_logic;
- signal full_allow : std_logic;
-
- signal full_i : std_logic;
- signal empty : std_logic;
-
- signal emptyg : std_logic;
- signal fullg : std_logic;
-
- signal read_addr_next : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_lastgray : std_logic_vector(Log2(MemSize)-1 downto 0);
-
- signal write_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal write_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal write_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
-
- signal ecomp : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal fcomp : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal emuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
- signal fmuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
-
-begin
-
- -- Assign local signals from ports
- read_enable <= RD;
- write_enable <= WE;
-
- -- Memory array
- WritePort : process (WrClk)
- begin
- if (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- ram_mem(To_integer(unsigned(write_addr))) <= DataIn;
- end if;
- end if;
- end process WritePort;
-
- ReadPort : process (RdClk)
- begin
- if (RdClk'event and RdClk = '1') then
- DataOut <= ram_mem(To_integer(unsigned(read_addr_next)));
- end if;
- end process ReadPort;
-
- ----------------------------------------------------------------
- -- Allow flags determine whether FIFO control logic can --
- -- operate. If read_enable is driven high, and the FIFO is --
- -- not Empty, then Reads are allowed. Similarly, if the --
- -- write_enable signal is high, and the FIFO is not Full, --
- -- then Writes are allowed. --
- ----------------------------------------------------------------
-
- read_allow <= (read_enable and not empty);
- write_allow <= (write_enable and not full_i);
-
- ---------------------------------------------------------------
- -- Empty flag is set on Reset (initial), or when gray --
- -- code counters are equal, or when there is one word in --
- -- the FIFO, and a Read operation is about to be performed. --
- ---------------------------------------------------------------
-
- empty_allow <= (empty or read_enable); -- Is empty or possibly going to be empty
-
- EmptyFlag : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- empty <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (empty_allow = '1') then
- empty <= emptyg;
- end if;
- end if;
- end process EmptyFlag;
-
- Exists <= not empty;
-
- ---------------------------------------------------------------
- -- Full flag is set on Reset (initial, but it is cleared --
- -- on the first valid write_clock edge after Reset is --
- -- de-asserted), or when Gray-code counters are one away --
- -- from being equal (the Write Gray-code address is equal --
- -- to the Last Read Gray-code address), or when the Next --
- -- Write Gray-code address is equal to the Last Read Gray- --
- -- code address, and a Write operation is about to be --
- -- performed. --
- ---------------------------------------------------------------
-
- full_allow <= (full_i or write_enable); -- Is full or possibly going to be full
-
- FullFlag : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- full_i <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (full_allow = '1') then
- full_i <= fullg;
- end if;
- end if;
- end process FullFlag;
-
- Full <= full_i;
-
- ----------------------------------------------------------------
- -- Generation of Read address pointers. The primary one is --
- -- binary (read_addr), and the Gray-code derivatives are --
- -- generated via pipelining the binary-to-Gray-code result. --
- -- The initial values are important, so they're in sequence. --
- -- --
- -- Grey-code addresses are used so that the registered --
- -- Full and Empty flags are always clean, and never in an --
- -- unknown state due to the asynchonous relationship of the --
- -- Read and Write clocks. In the worst case scenario, Full --
- -- and Empty would simply stay active one cycle longer, but --
- -- it would not generate an error or give false values. --
- ----------------------------------------------------------------
-
- read_addr_next <= std_logic_vector(unsigned(read_addr) + 1) when read_allow = '1' else read_addr;
-
- ReadAddrCnt : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_addr <= (others => '0');
- elsif (RdClk'event and RdClk = '1') then
- read_addr <= read_addr_next;
- end if;
- end process ReadAddrCnt;
-
- ReadNextGray : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_nextgray(read_nextgray'high-1 downto 0) <= (others => '0');
- read_nextgray(read_nextgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_nextgray <= Bin2Gray(read_addr);
- end if;
- end if;
- end process ReadNextGray;
-
- ReadAddrGray : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_addrgray(read_addrgray'high-1 downto 1) <= (others => '0');
- read_addrgray(0) <= '1';
- read_addrgray(read_addrgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_addrgray <= read_nextgray;
- end if;
- end if;
- end process ReadAddrGray;
-
- ReadLastGrey : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_lastgray(read_lastgray'high-1 downto 2) <= (others => '0');
- read_lastgray(0) <= '1';
- read_lastgray(1) <= '1';
- read_lastgray(read_lastgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_lastgray <= read_addrgray;
- end if;
- end if;
- end process ReadLastGrey;
-
- ----------------------------------------------------------------
- -- Generation of Write address pointers. Identical copy of --
- -- read pointer generation above, except for names. --
- ----------------------------------------------------------------
-
- WriteAddrCnt : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_addr <= (others => '0');
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_addr <= std_logic_vector(unsigned(write_addr) + 1);
- end if;
- end if;
- end process WriteAddrCnt;
-
- WriteNextGray : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_nextgray(write_nextgray'high-1 downto 0) <= (others => '0');
- write_nextgray(write_nextgray'high) <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_nextgray <= Bin2Gray(write_addr);
- end if;
- end if;
- end process WriteNextGray;
-
- WriteAddrGray : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_addrgray(write_addrgray'high-1 downto 0) <= (others => '0');
- write_addrgray(0) <= '1';
- write_addrgray(write_addrgray'high) <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_addrgray <= write_nextgray;
- end if;
- end if;
- end process WriteAddrGray;
-
-----------------------------------------------------------------
--- The two conditions decoded with special carry logic are --
--- Empty and Full (gated versions). These are used to --
--- determine the next state of the Full/Empty flags. Carry --
--- logic is used for optimal speed. (The previous --
--- implementation of AlmostEmpty and AlmostFull have been --
--- wrapped into the corresponding carry chains for faster --
--- performance). --
--- --
--- When write_addrgray is equal to read_addrgray, the FIFO --
--- is Empty, and emptyg (combinatorial) is asserted. Or, --
--- when write_addrgray is equal to read_nextgray (1 word in --
--- the FIFO) then the FIFO potentially could be going Empty, --
--- so emptyg is asserted, and the Empty flip-flop enable is --
--- gated with empty_allow, which is conditioned with a valid --
--- read. --
--- --
--- Similarly, when read_lastgray is equal to write_addrgray, --
--- the FIFO is full (511 addresses). Or, when read_lastgray --
--- is equal to write_nextgray, then the FIFO potentially --
--- could be going Full, so fullg is asserted, and the Full --
--- flip-flop enable is gated with full_allow, which is --
--- conditioned with a valid write. --
--- --
--- Note: To have utilized the full address space (512) --
--- would have required extra logic to determine Full/Empty --
--- on equal addresses, and this would have slowed down the --
--- overall performance, which was the top priority. --
-----------------------------------------------------------------
-
- ECompare : process(write_addrgray, read_addrgray, read_nextgray, empty)
- begin
- for I in 0 to Log2(MemSize)-1 loop
- ecomp(I) <= (not (write_addrgray(I) xor read_addrgray(I)) and empty) or
- (not (write_addrgray(I) xor read_nextgray(I)) and not empty);
- end loop;
- end process ECompare;
-
- emuxcylow : MUXCY_L port map(DI => '0', CI => '1', S => ecomp(0), LO => emuxcyo(0));
-
- Gen_emuxcy : for I in 1 to Log2(MemSize)-2 generate
- begin
- emuxcy : MUXCY_L port map(DI => '0', CI => emuxcyo(I-1), S => ecomp(I), LO => emuxcyo(I));
- end generate Gen_emuxcy;
-
- emuxcyhigh : MUXCY_L port map(DI => '0', CI => emuxcyo(Log2(MemSize)-2), S => ecomp(Log2(MemSize)-1), LO => emptyg);
-
- FCompare : process(read_lastgray, write_addrgray, write_nextgray, full_i)
- begin
- for I in 0 to Log2(MemSize)-1 loop
- fcomp(I) <= (not (read_lastgray(I) xor write_addrgray(I)) and full_i) or
- (not (read_lastgray(I) xor write_nextgray(I)) and not full_i);
- end loop;
- end process FCompare;
-
- fmuxcylow : MUXCY_L port map (DI => '0', CI => '1', S => fcomp(0), LO => fmuxcyo(0));
-
- Gen_fmuxcy : for I in 1 to Log2(MemSize)-2 generate
- begin
- fmuxcy : MUXCY_L port map (DI => '0', CI => fmuxcyo(I-1), S => fcomp(I), LO => fmuxcyo(I));
- end generate Gen_fmuxcy;
-
- fmuxcyhigh : MUXCY_L port map (DI => '0', CI => fmuxcyo(Log2(MemSize)-2), S => fcomp(Log2(MemSize)-1), LO => fullg);
-
-end architecture IMP;
-
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/fsl_v20.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/fsl_v20.vhd
deleted file mode 100644
index 6389753aa48540398d613bd1a80a7ff20f786982..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/fsl_v20.vhd
+++ /dev/null
@@ -1,469 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- fsl_v20.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: fsl_v20.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2003-02-13 First Version
--- satish 2004-03-03 New Version
--- rolandp 2006-08-20 BRAM in asynch mode
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-
-library Unisim;
-use Unisim.vcomponents.all;
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end entity fsl_v20;
-
-architecture IMP of fsl_v20 is
-
- component Sync_FIFO is
- generic (
- C_IMPL_STYLE : Integer;
- WordSize : Integer;
- MemSize : Integer);
- port (
- Reset : in Std_Logic;
- Clk : in Std_Logic;
-
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Sync_FIFO;
-
- component Async_FIFO is
- generic (
- WordSize : Integer;
- MemSize : Integer;
- Protect : Boolean);
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Async_FIFO;
-
- component Async_FIFO_BRAM is
- generic (
- WordSize : Integer;
- MemSize : Integer;
- Protect : Boolean);
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Async_FIFO_BRAM;
-
- signal sys_rst_i : std_logic;
- signal srl_time_out : std_logic;
- signal fsl_rst_i : std_logic;
- signal Data_In : std_logic_vector(0 to C_FSL_DWIDTH);
- signal Data_Out : std_logic_vector(0 to C_FSL_DWIDTH);
-
- signal fifo_full : std_logic;
- -- signal fifo_half_full : std_logic;
- -- signal fifo_half_empty : std_logic;
- signal fifo_has_data : std_logic;
-
- signal fsl_s_control_i : std_logic;
-
- signal srl_clk : std_logic;
-
-begin -- architecture IMP
-
- SYS_RST_PROC : process (SYS_Rst) is
- variable sys_rst_input : std_logic;
- begin
- if C_EXT_RESET_HIGH = 0 then
- sys_rst_i <= not SYS_Rst;
- else
- sys_rst_i <= SYS_Rst;
- end if;
- end process SYS_RST_PROC;
-
- Rst_Delay_Async: if (C_ASYNC_CLKS /= 0) generate
- srl_clk <= FSL_M_Clk;
-
- end generate Rst_Delay_Async;
-
- Rst_Delay_Sync: if (C_ASYNC_CLKS = 0) generate
- srl_clk <= FSL_Clk;
- end generate Rst_Delay_Sync;
-
- POR_SRL_I : SRL16
- generic map (
- INIT => X"FFFF")
- port map (
- D => '0',
- CLK => srl_Clk,
- A0 => '1',
- A1 => '1',
- A2 => '1',
- A3 => '1',
- Q => srl_time_out);
-
- POR_FF_I : FDS
- port map (
- Q => fsl_rst_i,
- D => srl_time_out,
- C => srl_Clk,
- S => sys_rst_i);
-
- FSL_Rst <= fsl_rst_i;
-
-
- -----------------------------------------------------------------------------
- -- Width is 1, so implement a registers
- -----------------------------------------------------------------------------
- Only_Register : if (C_FSL_DEPTH = 1) generate
- signal fsl_s_exists_i : std_logic;
- signal fsl_m_full_i : std_logic;
- begin
-
- -- FSL_S_Clk and FSL_M_Clk are the same
- Sync_Clocks: if (C_ASYNC_CLKS = 0) generate
-
- FIFO : process (FSL_Clk) is
- variable fifo_full : std_logic;
- begin -- process FIFO
- if FSL_Clk'event and FSL_Clk = '1' then -- rising clock edge
- if fsl_rst_i = '1' then -- synchronous reset (active high)
- fifo_full := '0';
- Fsl_m_full_i <= '1';
- Fsl_s_exists_i <= '0';
- else
- if (fifo_full = '0') then -- Empty
- if (FSL_M_Write = '1') then
- fifo_full := '1';
- FSL_S_Data <= FSL_M_Data;
- fsl_s_control_i <= FSL_M_Control;
- end if;
- end if;
- if (fifo_full = '1') then -- Has data
- if (FSL_S_Read = '1') then
- fifo_full := '0';
- end if;
- end if;
- Fsl_m_full_i <= fifo_full;
- Fsl_s_exists_i <= fifo_full;
- end if;
- end if;
- end process FIFO;
- end generate Sync_Clocks;
-
- FSL_S_Exists <= fsl_s_exists_i;
- FSL_Has_Data <= fsl_s_exists_i;
-
- FSL_M_Full <= fsl_m_full_i;
- FSL_Full <= fsl_m_full_i;
-
- FSL_S_Control <= fsl_s_control_i when C_USE_CONTROL /= 0 else '0';
- FSL_Control_IRQ <= fsl_s_control_i and fsl_s_exists_i when C_USE_CONTROL /= 0 else '0';
-
- end generate Only_Register;
-
- Using_FIFO: if (C_FSL_DEPTH > 1) generate
- begin
- -- Map Master Data/Control signal
- Data_In(0 to C_FSL_DWIDTH-1) <= FSL_M_Data;
-
- -- Map Slave Data/Control signal
- FSL_S_Data <= Data_Out(0 to C_FSL_DWIDTH-1);
-
- -- SRL FIFO BASED IMPLEMENTATION
- Sync_FIFO_Gen : if (C_ASYNC_CLKS = 0) generate
- Use_Control: if (C_USE_CONTROL /= 0) generate
-
- Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
- fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
-
- Sync_FIFO_I1 : Sync_FIFO
- generic map (
- C_IMPL_STYLE => C_IMPL_STYLE,
- WordSize => C_FSL_DWIDTH + 1,
- MemSize => C_FSL_DEPTH)
- port map (
- Reset => fsl_rst_i,
- Clk => FSL_Clk,
- WE => FSL_M_Write,
- DataIn => Data_In,
- Full => fifo_full,
- RD => FSL_S_Read,
- DataOut => Data_Out,
- Exists => fifo_has_data);
- end generate Use_Control;
-
- Use_Data: if (C_USE_CONTROL = 0) generate
-
- fsl_s_control_i <= '0';
-
- Sync_FIFO_I1 : Sync_FIFO
- generic map (
- C_IMPL_STYLE => C_IMPL_STYLE,
- WordSize => C_FSL_DWIDTH,
- MemSize => C_FSL_DEPTH)
- port map (
- Reset => fsl_rst_i,
- Clk => FSL_Clk,
- WE => FSL_M_Write,
- DataIn => Data_In(0 to C_FSL_DWIDTH-1),
- Full => fifo_full,
- RD => FSL_S_Read,
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1),
- Exists => fifo_has_data);
-
- end generate Use_Data;
- end generate Sync_FIFO_Gen;
-
- Async_FIFO_Gen: if (C_ASYNC_CLKS /= 0) generate
-
- Use_Control: if (C_USE_CONTROL /= 0) generate
-
- Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
- fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
-
- Use_DPRAM1: if (C_IMPL_STYLE = 0) generate
- -- LUT RAM implementation
- Async_FIFO_I1: Async_FIFO
- generic map (
- WordSize => C_FSL_DWIDTH + 1, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_DPRAM1;
-
- Use_BRAM1: if (C_IMPL_STYLE /= 0) generate
- -- BRAM implementation
- Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
- generic map (
- WordSize => C_FSL_DWIDTH + 1, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_BRAM1;
-
- end generate Use_Control;
-
- Use_Data: if (C_USE_CONTROL = 0) generate
-
- fsl_s_control_i <= '0';
-
- Use_DPRAM0: if (C_IMPL_STYLE = 0) generate
- -- LUT RAM implementation
- Async_FIFO_I1 : Async_FIFO
- generic map (
- WordSize => C_FSL_DWIDTH, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_DPRAM0;
-
- Use_BRAM0: if (C_IMPL_STYLE /= 0) generate
- -- BRAM implementation
- Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
- generic map (
- WordSize => C_FSL_DWIDTH, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_BRAM0;
-
- end generate Use_Data;
-
- end generate Async_FIFO_Gen;
-
- FSL_M_Full <= fifo_full or fsl_rst_i; -- Inhibit writes during reset by
- -- forcing full to '1'
- FSL_S_Exists <= fifo_has_data;
-
- FSL_Full <= fifo_full;
- FSL_Has_Data <= fifo_has_data;
-
- FSL_S_Control <= fsl_s_control_i;
- FSL_Control_IRQ <= fsl_s_control_i and fifo_has_data;
-
- end generate Using_FIFO;
-
-end architecture IMP;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_srlfifo.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_srlfifo.vhd
deleted file mode 100644
index 2176259d1b8ea187e382749b990716e48490f819..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_srlfifo.vhd
+++ /dev/null
@@ -1,220 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: gen_srlfifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- srl_fifo.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: srl_fifo.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- srl_fifo.vhd
---
--------------------------------------------------------------------------------
--- Author: goran
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- goran 2003-02-13 First Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity SRL_FIFO is
- generic (
- C_DATA_BITS : integer := 8;
- C_DEPTH : integer := 16
- );
- port (
- Clk : in std_logic;
- Reset : in std_logic;
- FIFO_Write : in std_logic;
- Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Read : in std_logic;
- Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Full : out std_logic;
- -- FIFO_Half_Full : out std_logic;
- -- FIFO_Half_Empty : out std_logic;
- Data_Exists : out std_logic
- );
-
-end entity SRL_FIFO;
-
-library UNISIM;
-use UNISIM.VCOMPONENTS.all;
-
-architecture IMP of SRL_FIFO is
-
- signal Addr : std_logic_vector(0 to 3);
- signal buffer_Full : std_logic;
- signal buffer_Empty : std_logic;
-
- signal next_Data_Exists : std_logic;
- signal data_Exists_I : std_logic;
-
- signal valid_Write : std_logic;
-
- signal hsum_A : std_logic_vector(0 to 3);
- signal sum_A : std_logic_vector(0 to 3);
- signal addr_cy : std_logic_vector(0 to 3);
-
- signal buffer_full_early : std_logic;
-
-begin -- architecture IMP
-
--- buffer_Full <= '1' when (Addr = "1111") else '0';
-
- buffer_full_early <= '1' when (sum_A = "1111") else '0';
-
- FDRE_I1: FDRE
- port map (
- Q => buffer_Full, -- [out std_logic]
- C => Clk, -- [in std_logic]
- CE => data_Exists_I, -- [in std_logic]
- D => buffer_full_early, -- [in std_logic]
- R => Reset); -- [in std_logic]
-
- FIFO_Full <= buffer_Full;
-
- -- FIFO_Half_Full <= Addr(3);
- -- FIFO_Half_Empty <= not Addr(3);
-
- buffer_Empty <= '1' when (Addr = "0000") else '0';
-
- next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
- (buffer_Empty and FIFO_Write) or
- (data_Exists_I and not FIFO_Read);
-
- Data_Exists_DFF : process (Clk) is
- begin -- process Data_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- data_Exists_I <= '0';
- else
- data_Exists_I <= next_Data_Exists;
- end if;
- end if;
- end process Data_Exists_DFF;
-
- Data_Exists <= data_Exists_I;
-
- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
-
- addr_cy(0) <= valid_Write;
-
- Addr_Counters : for I in 0 to 3 generate
-
- hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-
- -- Don't need the last muxcy, addr_cy(4) is not used anywhere
- Used_MuxCY: if I < 3 generate
- MUXCY_L_I : MUXCY_L
- port map (
- DI => addr(I), -- [in std_logic]
- CI => addr_cy(I), -- [in std_logic]
- S => hsum_A(I), -- [in std_logic]
- LO => addr_cy(I+1)); -- [out std_logic]
- end generate Used_MuxCY;
-
- XORCY_I : XORCY
- port map (
- LI => hsum_A(I), -- [in std_logic]
- CI => addr_cy(I), -- [in std_logic]
- O => sum_A(I)); -- [out std_logic]
-
- FDRE_I : FDRE
- port map (
- Q => addr(I), -- [out std_logic]
- C => Clk, -- [in std_logic]
- CE => data_Exists_I, -- [in std_logic]
- D => sum_A(I), -- [in std_logic]
- R => Reset); -- [in std_logic]
-
- end generate Addr_Counters;
-
- FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
- SRL16E_I : SRL16E
- generic map (
- INIT => x"0000")
- port map (
- CE => valid_Write, -- [in std_logic]
- D => Data_In(I), -- [in std_logic]
- Clk => Clk, -- [in std_logic]
- A0 => Addr(0), -- [in std_logic]
- A1 => Addr(1), -- [in std_logic]
- A2 => Addr(2), -- [in std_logic]
- A3 => Addr(3), -- [in std_logic]
- Q => Data_Out(I)); -- [out std_logic]
- end generate FIFO_RAM;
-
-end architecture IMP;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_sync_bram.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_sync_bram.vhd
deleted file mode 100644
index a962c754ee3330f63310cd227cd98dde5c672698..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_sync_bram.vhd
+++ /dev/null
@@ -1,129 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: gen_sync_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_bram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--- Description:
--- Code to infer synchronous dual port bram and separate read/write clock dual
--- port bram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-entity Sync_BRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- -- Write port
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- -- Read port
- dpra_en : in std_logic;
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
-end Sync_BRAM;
-
-architecture syn of Sync_BRAM is
- type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
- -- signal ram_mem : ram_type := (others => (others => '0'));
- signal ram_mem : ram_type;
- signal read_a : std_logic_vector(C_AWIDTH-1 downto 0);
- signal read_dpra : std_logic_vector(C_AWIDTH-1 downto 0);
-begin
- process (clk)
- begin
- if (clk'event and clk = '1') then
- if (we = '1') then
- ram_mem(conv_integer(a)) <= di;
- end if;
- read_a <= a;
- if (dpra_en = '1') then
- read_dpra <= dpra;
- end if;
- end if;
- end process;
- dpo <= ram_mem(conv_integer(read_dpra));
-end syn;
-
-
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_sync_dpram.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_sync_dpram.vhd
deleted file mode 100644
index 7a35506e9d7a79758f3f2b8b0f3dbb3a9672cc3e..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/gen_sync_dpram.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: gen_sync_dpram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_dpram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--- Description:
--- Code to infer synchronous dual port lut ram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity Sync_DPRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
-end Sync_DPRAM;
-
-architecture syn of Sync_DPRAM is
- type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
- -- signal RAM : ram_type := (others => (others => '0'));
- signal RAM : ram_type;
-begin
- process (clk)
- begin
- if (clk'event and clk = '1') then
- if (we = '1') then
- RAM(conv_integer(a)) <= di;
- end if;
- end if;
- end process;
- dpo <= RAM(conv_integer(dpra));
-end syn;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/sync_fifo.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/sync_fifo.vhd
deleted file mode 100644
index d6e6204893de84cb9ecef1fce77a734ccf9b59c0..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/src/vhdl/sync_fifo.vhd
+++ /dev/null
@@ -1,397 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: sync_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- sync_fifo.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.Std_Logic_1164.all;
-use IEEE.numeric_std.all;
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity Sync_FIFO is
- generic (
- C_IMPL_STYLE : integer := 0;
- WordSize : integer := 8;
- MemSize : integer := 16
- );
- port (
- Reset : in std_logic;
- Clk : in std_logic;
-
- WE : in std_logic;
- DataIn : in std_logic_vector(WordSize-1 downto 0);
- Full : out std_logic;
- RD : in std_logic;
- DataOut : out std_logic_vector(WordSize-1 downto 0);
- Exists : out std_logic
- );
-end Sync_FIFO;
-
-architecture VHDL_RTL of Sync_FIFO is
-
- function log2(x : natural) return integer is
- variable i : integer := 0;
- begin
- -- coverage off
- if x = 0 then return 0;
- -- coverage on
- else
- while 2**i < x loop
- i := i+1;
- end loop;
- return i;
- end if;
- end function log2;
-
- constant AddrWidth : integer := log2(MemSize);
- signal Read_Address : std_logic_vector(0 to AddrWidth-1);
- signal Write_Address : std_logic_vector(0 to AddrWidth-1);
-
- component SRL_FIFO is
- generic (
- C_DATA_BITS : integer;
- C_DEPTH : integer);
- port (
- Clk : in std_logic;
- Reset : in std_logic;
- FIFO_Write : in std_logic;
- Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Read : in std_logic;
- Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Full : out std_logic;
- -- FIFO_Half_Full : out std_logic;
- -- FIFO_Half_Empty : out std_logic;
- Data_Exists : out std_logic);
- end component SRL_FIFO;
-
- component Sync_DPRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
- end component;
-
- component Sync_BRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- -- Write port
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- -- Read port
- dpra_en : in std_logic;
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
- end component;
-
- signal read_bram_enable : std_logic;
- signal DataOut_BRAM : std_logic_vector(WordSize-1 downto 0);
-
-
-begin
-
- FSL_Flag_Handle : if ((MemSize > 16) or (C_IMPL_STYLE /= 0)) generate
- signal read_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
- signal write_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
-
- signal full_i : std_logic;
- signal exists_i : std_logic;
- signal read_addr_incr : std_logic;
- signal first_write_on_empty_fifo : std_logic;
- signal last_word : std_logic;
-
- signal fifo_length : natural range 0 to MemSize;
- begin
-
- -- FIFO length handling
- Fifo_Length_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- fifo_length <= 0;
- else
- -- write and no read => increment length
- -- don't increment length when FULL
- if (WE = '1' and RD = '0' and full_i = '0') then
- fifo_length <= fifo_length + 1;
- -- read and no write => decrement length
- -- don't decrement length when EMPTY
- elsif (WE = '0' and RD = '1' and exists_i = '1') then
- fifo_length <= fifo_length - 1;
- end if;
- end if;
- end if;
- end process Fifo_Length_Handle;
-
- ---------------------------------------------------------------------------
- -- Need special handling for BRAM based fifo since there is one extra delay
- -- reading out data from it.
- -- We are pipelining the reading by making read_addr be one read ahead and
- -- are holding the data on the BRAM output by enabling/disabling the BRAM
- -- enable signal
- ---------------------------------------------------------------------------
- Rd_Delay_For_Bram : if (C_IMPL_STYLE /= 0) generate
- signal fall_through_data : std_logic_vector(WordSize-1 downto 0);
- signal use_fall_through : std_logic;
- begin
-
- -------------------------------------------------------------------------
- -- Need to detect when writing into an empty FIFO,
- -------------------------------------------------------------------------
- First_Write : process (Clk) is
- begin -- process First_Write
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- first_write_on_empty_fifo <= '0';
- else
- first_write_on_empty_fifo <= WE and not exists_i;
- end if;
- end if;
- end process First_Write;
-
- -------------------------------------------------------------------------
- -- Read out BRAM contents on the first word written in an empty FIFO and
- -- all other FIFO read except when the last word is read since the "real"
- -- FIFO is actually empty at this time since the last word is on the
- -- output of the BRAM
- -------------------------------------------------------------------------
- last_word <= '1' when (fifo_length = 1) else '0';
- read_bram_enable <= first_write_on_empty_fifo or (RD and (not last_word or WE));
-
- read_addr_incr <= read_bram_enable;
-
- -------------------------------------------------------------------------
- -- The exists flag is now if the BRAM output has valid data and not the
- -- content of the FIFO
- -------------------------------------------------------------------------
- FIFO_Exists_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- Exists <= '0';
- else
- if (first_write_on_empty_fifo = '1') then
- Exists <= '1';
- elsif ((RD = '1') and (WE = '0') and (last_word = '1')) then
- Exists <= '0';
- end if;
- end if;
- end if;
- end process FIFO_Exists_DFF;
-
- -------------------------------------------------------------------------
- -- Data output with fallthrough
- -------------------------------------------------------------------------
- use_fall_through_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if ((RD and (not WE)) = '1') or (Reset = '1') then -- synchronous reset (active high)
- use_fall_through <= '0';
- elsif (RD and not last_word) = '1' then
- use_fall_through <= '0';
- elsif (RD = '1') then
--- The equation (RD and WE and last_word) = '1' can be reduced to (RD = '1')
- use_fall_through <= '1';
- end if;
- end if;
- end process use_fall_through_DFF;
-
- fall_through_data_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if (RD and WE and last_word) = '1' then
- fall_through_data <= DataIn;
- end if;
- end if;
- end process fall_through_data_DFF;
-
- DataOut <= fall_through_data when (use_fall_through = '1') else DataOut_BRAM;
-
- end generate Rd_Delay_For_Bram;
-
- Rd_No_Delay : if (C_IMPL_STYLE = 0) generate
- read_addr_incr <= RD;
- Exists <= exists_i;
- end generate Rd_No_Delay;
-
- -- Set Full and empty flags
- full_i <= '1' when (fifo_length = MemSize) else '0';
- exists_i <= '1' when (fifo_length /= 0) else '0';
-
- Full <= full_i;
-
- -- Increment Read Address Pointer
- Read_Addr_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- read_addr_ptr <= 0;
- elsif (read_addr_incr = '1') then
- read_addr_ptr <= (read_addr_ptr + 1) mod (2 ** AddrWidth);
- end if;
- end if;
- end process Read_Addr_Handle;
-
- -- Increment Write Address Pointer
- Write_Addr_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- write_addr_ptr <= 0;
- elsif (WE = '1') then
- write_addr_ptr <= (write_addr_ptr + 1) mod (2 ** AddrWidth);
- end if;
- end if;
- end process Write_Addr_Handle;
-
- Write_Address <= std_logic_vector(to_unsigned(write_addr_ptr, AddrWidth));
- Read_Address <= std_logic_vector(to_unsigned(read_addr_ptr, AddrWidth));
-
- end generate FSL_Flag_Handle;
-
-
- Sync_FIFO_I : if (C_IMPL_STYLE = 0) generate
- srl_fifo_i : if (MemSize <= 16) generate
- FSL_FIFO : SRL_FIFO
- generic map (
- C_DATA_BITS => WordSize,
- C_DEPTH => MemSize)
- port map (
- Clk => Clk,
- Reset => Reset,
- FIFO_Write => WE, -- Master Write Signal
- Data_In => DataIn, -- Master Data
- FIFO_Read => RD, -- Slave Read Signal
- Data_Out => DataOut, -- Slave Data
- FIFO_Full => Full, -- FIFO full signal
- -- FIFO_Half_Full => open,
- -- FIFO_Half_Empty => open,
- Data_Exists => Exists); -- Slave Data exists
- end generate srl_fifo_i;
-
- dpram_fifo_i : if (MemSize > 16) generate
- DPRAM_FIFO : SYNC_DPRAM
- generic map (
- C_DWIDTH => WordSize,
- C_AWIDTH => AddrWidth)
- port map (
- clk => Clk,
- we => WE,
- a => Write_Address,
- dpra => Read_Address,
- di => DataIn,
- dpo => DataOut);
- end generate dpram_fifo_i;
-
- end generate Sync_FIFO_I;
-
- Sync_BRAM_FIFO : if (C_IMPL_STYLE /= 0) generate
- Sync_BRAM_I1 : Sync_BRAM
- generic map (
- C_DWIDTH => WordSize, -- [integer]
- C_AWIDTH => AddrWidth) -- [integer]
- port map (
- clk => Clk, -- [in std_logic]
-
- -- Write port
- we => WE, -- [in std_logic]
- a => Write_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
- di => DataIn, -- [in std_logic_vector(C_DWIDTH-1 downto 0)]
-
- -- Read port
- dpra_en => read_bram_enable, -- [in std_logic]
- dpra => Read_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
- dpo => DataOut_BRAM); -- [out std_logic_vector(C_DWIDTH-1 downto 0)]
- end generate Sync_BRAM_FIFO;
-
-end VHDL_RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg
deleted file mode 100644
index 9576a2dde2f5cf5bc7066248fe66e6c8f1b7cb03..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-hdl_lib_name = compaandesign_com_common_hwnode_1
-hdl_library_clause_name = compaandesign_com_common_hwnode_1_lib
-hdl_lib_uses_synth = compaandesign_com_common_common_1 compaandesign_com_common_altera_1
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/controller.vhd
- src/vhdl/counter.vhd
- src/vhdl/it_mod.vhd
- src/vhdl/it_mul.vhd
- src/vhdl/parameters.vhd
- src/vhdl/read_mux.vhd
- src/vhdl/read_mmux.vhd
- src/vhdl/write_demux.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/controller.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/controller.vhd
deleted file mode 100644
index 9c232e661419837d2702374caea8658f59558351..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/controller.vhd
+++ /dev/null
@@ -1,107 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity CONTROLLER is
- generic(
- N_STAGES : natural := 1; -- number of pipeline stages or delay
- BLOCKING : natural := 0 -- '1'-block the pipeline if there is no input data
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
-
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
-
- CLK : in std_logic;
- RST : in std_logic
- );
-end CONTROLLER;
-
-architecture RTL of CONTROLLER is
-
- signal p_en : std_logic_vector(N_STAGES downto 0); -- Enable signals to the execution pipline stages
- signal blocked : std_logic; -- pipeline is blocked on Write
- signal pipe : std_logic_vector(N_STAGES downto 0); -- delay pipeline
- signal execute_pipe : std_logic_vector(N_STAGES downto 0); -- reverse signal of pipe
-
- function reverse_any_vector (a: in std_logic_vector)
- return std_logic_vector is variable result: std_logic_vector(a'RANGE);
- alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
- begin
- for i in aa'RANGE loop
- result(i) := aa(i);
- end loop;
- return result;
- end; -- function reverse_any_vector
-
-
- begin
- --
- Pipe_Fill: process( CLK, RST )
- begin
- if ( RST = '1' ) then
- pipe <= (others => '0');
- elsif ( rising_edge(CLK) ) then
- --
- BUBBLE_COMPRESS:
- for i in N_STAGES downto 1 loop
- if ( p_en(i)='1' ) then
- pipe(i) <= pipe(i-1) and not STALL_FRONT(i-1);
- end if;
- end loop;
- --
- if ( p_en(0)='1' ) then
- pipe(0) <= EXIST;
- end if;
-
- end if;
- end process Pipe_Fill;
-
- Pipe_Reverse: process(pipe, RST)
- begin
- if (RST = '1') then
- execute_pipe <= (others => '0');
- else
- execute_pipe <= reverse_any_vector(pipe);
- end if;
- end process Pipe_Reverse;
-
- --p_en(N_STAGES-1 downto 0) <= not pipe(N_STAGES-1 downto 0) or p_en(N_STAGES downto 1);
- p_en(N_STAGES-1 downto 0) <= p_en(N_STAGES downto 1) and not STALL_BACK(N_STAGES-1 downto 0);
- p_en(N_STAGES) <= not pipe(N_STAGES) or not FULL;
- --
- WRITE <= pipe(N_STAGES) and not FULL;
- READ <= EXIST and p_en(0);
- ENABLE_EX(N_STAGES-1 downto 0) <= pipe(N_STAGES-1 downto 0) and p_en(N_STAGES downto 1);
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/counter.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/counter.vhd
deleted file mode 100644
index 855aae130125e07d5f870b4da11a9e766c28c6be..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/counter.vhd
+++ /dev/null
@@ -1,89 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity counter is
- generic(
- C_STEP : natural := 1;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
-end counter;
-
-architecture RTL of counter is
-
- signal sl_counter : unsigned(C_WIDTH-1 downto 0);
- signal sl_register : unsigned(C_WIDTH-1 downto 0);
- signal sl_LOWER_BND : unsigned(C_WIDTH-1 downto 0);
- signal sl_UPPER_BND : unsigned(C_WIDTH-1 downto 0);
- signal sl_last_count : std_logic;
- signal sl_done : std_logic;
-
-begin
-
- ITERATOR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_counter);
- REG_CNTR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_register);
-
- sl_LOWER_BND <= UNSIGNED(LOWER_BND(C_WIDTH-1 downto 0));
- sl_UPPER_BND <= UNSIGNED(UPPER_BND(C_WIDTH-1 downto 0));
-
-
- sl_counter <= sl_LOWER_BND when (sl_done='1' or RST='1' or LOAD='1') else (sl_register + C_STEP);
- --sl_last_count <= '1' when (sl_counter >= sl_UPPER_BND) else '0';
- sl_last_count <= '1' when (sl_register >= sl_UPPER_BND) else '0';
- sl_done <= sl_last_count;
- --
- DONE <= sl_done;
-
- REG_PRCS : process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST='1' or LOAD ='1' ) then
- sl_register <= sl_LOWER_BND;
- --sl_done <= sl_last_count; -- special case: (sl_LOWER_BND == sl_UPPER_BND)
- elsif( ENABLE='1' ) then
- sl_register <= sl_counter;
- --sl_done <= sl_last_count;
- end if;
- end if;
- end process;
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd
deleted file mode 100644
index 1dea20fb8f3cb2c4c475f15255a204dc8804a252..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/it_mod.vhd
+++ /dev/null
@@ -1,96 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-
-entity it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
-end it_mod;
-
-architecture RTL of it_mod is
- signal sl_reg : unsigned(C_WIDTH-1 downto 0);
- signal sl_step : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_STEP,C_WIDTH);
- signal sl_init : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_INIT,C_WIDTH);
- signal sl_mod : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_MOD ,C_WIDTH);
--- signal a1 : unsigned(C_WIDTH downto 0);
--- signal a2 : unsigned(C_WIDTH downto 0);
-begin
- --
- -- Checks
- assert (2**C_WIDTH >= C_MOD)
- report "Parameter C_MOD (=" & integer'image(C_MOD) & ") bitwidth exceeds the output bitwidth (C_WIDTH=" & integer'image(C_WIDTH) & ")"
- severity ERROR;
- --
- assert (C_MOD >= C_STEP)
- report "Parameter C_STEP (=" & integer'image(C_STEP) & ") greater than parameter C_MOD (=" & integer'image(C_MOD) & ")"
- severity ERROR;
- --
- assert (C_MOD >= C_INIT)
- report "Parameter C_INIT (=" & integer'image(C_INIT) & ") greater than parameter C_MOD (=" & integer'image(C_MOD) & ")"
- severity ERROR;
-
-
- --
- REG_PRCS : process(CLK, RST)
- variable a1 : unsigned(C_WIDTH downto 0);
- variable a2 : signed(C_WIDTH downto 0);
- begin
- if rising_edge(CLK) then
- --if( RST='1' or LOAD='1') then
- if( RST='1' ) then
- sl_reg <= sl_init;
- elsif( ENABLE='1' ) then
- a1 := ("0"&sl_reg) + ("0"&sl_step);
- a2 := SIGNED(a1) - SIGNED("0"&sl_mod);
- if ( LOAD='1' ) then
- sl_reg <= sl_init;
- elsif (a2(a2'High)='1') then
- sl_reg <= a1(C_WIDTH-1 downto 0);
- else
- sl_reg <= UNSIGNED(a2(C_WIDTH-1 downto 0));
- end if;
- end if;
- end if;
- end process;
- --
- MODULE <= STD_LOGIC_VECTOR(sl_reg);
- --
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd
deleted file mode 100644
index ad9e36ed3c5057843490d51f41155f9a2b106726..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/it_mul.vhd
+++ /dev/null
@@ -1,80 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-
-entity it_mul is
- generic(
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MUL : out std_logic_vector(C_WIDTH-1 downto 0)
- );
-end it_mul;
-
-architecture RTL of it_mul is
- signal sl_counter : unsigned(C_WIDTH-1 downto 0);
- signal sl_step : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_STEP,C_WIDTH);
- signal sl_init : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_INIT,C_WIDTH);
-begin
- --
- -- Checks
- assert (2**C_WIDTH > C_INIT)
- report "Parameter C_INIT (=" & integer'image(C_INIT) & ") bitwidth exceeds the output bitwidth (C_WIDTH=" & integer'image(C_WIDTH) & ")"
- severity ERROR;
- --
- assert (2**C_WIDTH > C_STEP)
- report "Parameter C_STEP (=" & integer'image(C_STEP) & ") bitwidth exceeds the output bitwidth (C_WIDTH=" & integer'image(C_WIDTH) & ")"
- severity ERROR;
- --
- REG_PRCS : process(CLK, RST)
- begin
- if rising_edge(CLK) then
- --if( RST='1' or LOAD='1') then
- if( RST='1' ) then
- sl_counter <= sl_init;
- elsif( ENABLE='1' ) then
- if ( LOAD='1') then
- sl_counter <= sl_init;
- else
- sl_counter <= sl_counter + sl_step;
- end if;
- end if;
- end if;
- end process;
- --
- MUL <= STD_LOGIC_VECTOR(sl_counter);
- --
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/parameters.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/parameters.vhd
deleted file mode 100644
index a6ad130caf2cb46bc14f3cff629c03b0e0ba8863..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/parameters.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity parameters is
- generic (
- PAR_WIDTH : natural;
- PAR_BITWIDTH : natural;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural := 0;
- N_SYNC_OUT : natural := 0;
- N_PAR : natural
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0) := (others => '0');
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
- PARAMETERS : out std_logic_vector(PAR_BITWIDTH-1 downto 0)
- );
-end parameters;
-
-architecture RTL of parameters is
-
- --constant N_PAR : natural := PAR_VECTOR'Length-2; -- The last two elements in PAR_VECTOR are always a dummy component
- -- we will always read all the paramerets in parallel
- --constant N_PAR : natural := 1;
-
- signal sl_tmp_parameters : std_logic_vector(N_PAR*PAR_WIDTH-1 downto 0);
- signal sl_update : std_logic;
- signal sl_halt : std_logic;
- signal sl_sof : std_logic;
- signal sl_det_0, sl_det_1, sl_PARAM_LD : std_logic;
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- type state_type is (s_idle, s_update_rd, s_update_wr);
- signal state : state_type;
-
- signal delay_cnt : integer;
-
- type sic is array (N_SYNC_IN downto 0) of natural;
- signal sync_in_cnt : sic;
- signal sync_in_f : std_logic_vector(N_SYNC_IN downto 0);
- signal sync_in_a : std_logic;
- signal sync_in_o : std_logic;
-
-signal switch_p : std_logic;
-
-begin
-
- GenLabel1 : if N_PAR > 0 generate
-
- PENDING_RD <= sl_pending_rd;
- PENDING_WR <= sl_pending_wr;
- sl_update_ack_rd <= UPDATE_ACK_RD;
- sl_update_ack_wr <= UPDATE_ACK_WR;
-
- GenLabelSo : if N_SYNC_OUT > 0 generate
- sync_out_prcss : process(CLK)
- begin
- if rising_edge( CLK ) then
- for i in 0 to N_SYNC_OUT loop
- SYNC_OUT(i) <= sl_update;
- end loop;
- end if;
- end process;
- end generate; -- GenLabelSo
-
- GenLabelSi1 : if N_SYNC_IN = 1 generate
- sync_in_a <= SYNC_IN(0);
- end generate; -- GenLabelSi
-
- GenLabelSi2 : if N_SYNC_IN = 2 generate
- sync_in_a <= SYNC_IN(0) or SYNC_IN(1);
- end generate; -- GenLabelSi
-
-
- HALT <= sl_update;
- sl_sof <= HALTED;
-
- -- Rising_edge detection of PARAM_LD signal --------------------
- Edge_det_prcss : process(CLK)
- begin
- if falling_edge( CLK ) then
- sl_det_0 <= PARAM_LD;
- sl_det_1 <= sl_det_0;
- end if;
- end process;
-
- sl_PARAM_LD <= sl_det_0 and not(sl_det_1);
-
- -- Update the parameters (from the temp buffer) ----------------
-
- FSM : process(CLK, RST)
- begin
- if rising_edge(CLK) then
- if( RST='1' ) then
- state <= s_idle;
- PARAMETERS(PAR_BITWIDTH-1 downto 0) <= STD_LOGIC_VECTOR(to_signed(10,PAR_BITWIDTH));
- sl_pending_rd <= '0';
- sl_pending_wr <= '0';
- switch_p <= '0';
- else
- case (state) is
- when s_idle =>
- if (sync_in_a ='1' and N_SYNC_IN > 0) then
- PARAMETERS(PAR_BITWIDTH-1 downto 0) <= PARAM_DT;
- sl_pending_rd <= '1';
- state <= s_update_rd;
- end if;
- when s_update_rd =>
- if(sl_update_ack_rd = '1') then
- sl_pending_rd <= '0';
- sl_pending_wr <= '1';
- state <= s_update_wr;
- end if;
- when s_update_wr =>
- if(sl_update_ack_wr = '1') then
- sl_pending_wr <= '0';
- state <= s_idle;
- end if;
- when others => state <= s_idle;
- end case;
- end if;
- end if;
- end process;
-
- end generate; -- GenLabel1
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd
deleted file mode 100644
index 2b2c9a62b361f12ac383b9da59e390be27aafcb3..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/read_mmux.vhd
+++ /dev/null
@@ -1,288 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity read_mmux is
- generic(
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32;
- C_IMPL_STYLE : integer := 0;
- C_FSL_DWIDTH : natural := 32;
- C_FSL_DEPTH : natural := 64
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
- CLK : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
-
- RST : in std_logic;
- OBTAIN_OOMX : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE_OOMX : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end read_mmux;
-
-architecture RTL of read_mmux is
-
-signal fsl_m_control : std_logic;
-signal fsl_m_clk : std_logic;
-signal fsl_write : std_logic;
-signal fsl_data_write : std_logic_vector(0 to C_FSL_DWIDTH-1);
-signal fsl_m_full : std_logic;
-signal fsl_read : std_logic;
-signal fsl_data_read : std_logic_vector(0 to C_FSL_DWIDTH-1);
-signal fsl_s_clk : std_logic;
-signal fsl_s_control : std_logic;
-signal fsl_s_exists : std_logic;
-
-signal sl_read : std_logic;
-signal sl_exist : std_logic;
- signal sl_avail : std_logic;
-
-component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic
- );
-end component fsl_v20;
-
-
-
-begin
-
- -- REUSE_READ => OBTAIN
- -- REUSE => RELEASE
-
- EXIST <= READ_EN and sl_exist;
- sl_read <= READ_EN and READ;
- READ_ST <= (sl_read and sl_exist) or (sl_avail);
-
- DEMUX_GEN : for i in 0 to N_PORTS-1 generate
- READS(i) <= EXISTS(i) and CONTROL(i) and sl_read and OBTAIN_OOMX(i);
- fsl_read <= not OBTAIN_OOMX(i) and (sl_read );
- fsl_write <= not RELEASE_OOMX(i) and (sl_read );
- end generate;
-
- MUX_PRCSS : process(CONTROL, RELEASE_OOMX, OBTAIN_OOMX, IN_PORTS, fsl_data_read)
- begin
- OUT_PORT <= (others=>'0');
- -- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
-
- -- Extra check giving feedback that sizing FIFO is very tight or too small
- assert fsl_m_full = '0'
- report "Internal FIFO is FULL!!!"
- severity WARNING;
-
- for i in 0 to N_PORTS-1 loop
-
- -- If control is high, we need data
- if( CONTROL(i) = '1' ) then
-
- -- peek (take the token fron the fsl and send it to the output and back to fsl)
- -- obtained is hoog, en release hoog
- -- Should not happen
- if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '1') then
-
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- --assert false
- -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
- -- severity FAILURE;
-
- sl_avail <= '0';
- -- sl_exist <= EXISTS(i);
-
- --OUT_PORT <= fsl_data_read;
- --fsl_data_write <= fsl_data_read;
- end if;
-
- -- peek last (read from the fifo without rewriting to the fsl)
- -- obtained is hoog, en release laag
- -- Read from external FIFO and store locally.
- if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '0') then
-
- -- read from outside and forward
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
-
- -- and put a copy in the local FIFO
- fsl_data_write <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
-
- sl_avail <= '0';
- -- sl_exist <= EXISTS(i);
-
- --OUT_PORT <= fsl_data_read;
- --fsl_data_write <= fsl_data_read;
- end if;
-
- -- take first (take the first token from te input and store it to the fsl)
- -- obtained is laag, en release hoog
-
- if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '1') then
-
- -- read from the internal FIFO, and let the FIFO run empty
- OUT_PORT <= fsl_data_read;
- sl_avail <= '1';
- -- sl_exist <= '1' ;
-
- end if;
-
- --take (take from the input and wirte to the output)
- -- obtained is laag, en release laag
- if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '0') then
-
- -- steady state...
- -- read from internal FIFO
- OUT_PORT <= fsl_data_read;
-
- -- and put the value back in the FIFO
- fsl_data_write <= fsl_data_read;
-
- sl_avail <= '1';
- -- sl_exist <= '1';
-
- end if;
- end if;
-
- end loop;
- end process;
-
-
- MUX_EXIST : process(EXISTS, OBTAIN_OOMX, CONTROL)
- begin
- -- The default value needs to be '1'. See the node's top-level: sl_exist <= sl_exist_1 and sl_exist_0;
- --EXIST <= '0';
- -- sl_exist <= '0';
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1' ) then
- --EXIST <= EXISTS(i);
- sl_exist <= (EXISTS(i) and OBTAIN_OOMX(i)) or (not OBTAIN_OOMX(i));
-
- -- Problem hier is dat EXISTS door FIFO wordt gestuurd. Dus in interne FIFO, moet deze hoog worden, ongeacht wat externe FIFO zegt...
- -- sl_exist <= '1' when ((EXISTS(i)='1' and (REUSE_READ(i) = '1')) or (REUSE_READ(i)='0')) else '0';
-
-
- end if;
- end loop;
- end process;
-
-
- -- Checks
- process(CONTROL)
- variable c : integer;
- begin
- c := 0;
- for i in 0 to CONTROL'Length-1 loop
- if (CONTROL(i)='1') then
- c := c + 1;
- end if;
- end loop;
- assert (c <= 1)
- report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
- severity ERROR;
- end process;
-
-
- fsl_m_control <= '0';
- fsl_m_clk <= '0';
- fsl_s_clk <= '0';
- fsl_s_control <= '0';
-
- fsl_cirular : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS =>0,
- C_USE_CONTROL => 1,
- C_IMPL_STYLE => C_IMPL_STYLE,
- C_FSL_DWIDTH => C_FSL_DWIDTH,
- C_FSL_DEPTH => C_FSL_DEPTH
- )
- port map (
- -- Clock and reset signals
- FSL_Clk => CLK,
- SYS_Rst => RST,
- FSL_Rst => open,
- -- FSL master signals
- FSL_M_Clk => fsl_m_clk,
- FSL_M_Data => fsl_data_write,
- FSL_M_Control => fsl_m_control,
- FSL_M_Write => fsl_write,
- FSL_M_Full => fsl_m_full,
- -- FSL slave signals
- FSL_S_Clk => fsl_s_clk,
- FSL_S_Data => fsl_data_read,
- FSL_S_Control => fsl_s_control,
- FSL_S_Read => fsl_read,
- FSL_S_Exists => fsl_s_exists,
- -- FIFO status signals
- FSL_Full => open,
- FSL_Has_Data => open
- );
-
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
deleted file mode 100644
index df9f2f121a5d1e8dcc6f6afd73e013553c49cc3a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/read_mux.vhd
+++ /dev/null
@@ -1,130 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity read_mux is
- generic(
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CLK : in std_logic;
-
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end read_mux;
-
-architecture RTL of read_mux is
- signal sl_read : std_logic;
- signal sl_exist : std_logic;
- signal TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
-begin
- EXIST <= READ_EN and sl_exist;
- sl_read <= READ_EN and READ;
- READ_ST <= sl_read and sl_exist;
-
- DEMUX_GEN : for i in 0 to N_PORTS-1 generate
- --
- -- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read and (not SOFS(i) or SOF);
- -- The Reorder work showed problems as a result of SOFS signal. For now switched off until
- -- its use becomes clear again. BK 31mar14
- --
- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read;
- end generate;
-
- MUX_DATA : process(CLK, CONTROL, IN_PORTS, OBTAIN, RELEASE, TMP)
- begin
- if rising_edge(CLK) then
- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1') then
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '0') then
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- TMP <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH); -- keep a copy of the value
- end if ;
-
- if( OBTAIN(i) = '0' and RELEASE(i) = '0') then
- OUT_PORT <= TMP;
- end if ;
-
- if( OBTAIN(i) = '0' and RELEASE(i) = '1') then
- OUT_PORT <= TMP;
- end if ;
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '1') then
- --assert false
- -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
- -- severity WARNING;
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- end if ;
- end if;
- end loop;
- end if;
- end process;
-
- MUX_EXIST : process(EXISTS, READ, CONTROL)
- begin
- sl_exist <= '0';
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1' ) then
- sl_exist <= EXISTS(i);
- end if;
- end loop;
- end process;
-
-
- -- Checks. For simulation only
- process(CONTROL)
- variable c : integer;
- begin
- c := 0;
- for i in 0 to CONTROL'Length-1 loop
- if (CONTROL(i)='1') then
- c := c + 1;
- end if;
- end loop;
- assert (c <= 1)
- report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
- severity ERROR;
- end process;
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd
deleted file mode 100644
index dc27a86a1572bed45fda1d1dbccca5722ef98d2b..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/src/vhdl/write_demux.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity write_demux is
- generic(
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
-
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end write_demux;
-
-
-architecture RTL of write_demux is
-
- signal sl_full : std_logic;
- signal sl_write : std_logic;
-
-begin
- --
- GEN : for i in 0 to N_PORTS-1 generate
- WRITES(i) <= CONTROL(i) and sl_write;
- end generate;
- --
- process(CONTROL,FULLS)
- variable a : std_logic;
- variable b : std_logic;
- begin
- a := '0';
- for i in 0 to N_PORTS-1 loop
- a := a or ( CONTROL(i) and FULLS(i) );
- end loop;
- sl_full <= a;
- end process;
- --
- sl_write <= WRITE_EN and WRITE;
- FULL <= (not WRITE_EN) or sl_full;
- WRITE_ST <= not sl_full and sl_write;
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg
deleted file mode 100644
index 45248208078d355e374802f192b0616dd474027a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-hdl_lib_name = compaandesign_com_common_wire_connector_1
-hdl_library_clause_name = compaandesign_com_common_wire_connector_1_lib
-hdl_lib_uses_synth =
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/wire_connector.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd
deleted file mode 100644
index 8db9cdd109bbf56f6f1812c0cab099861e0e72d3..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/src/vhdl/wire_connector.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
---
--- This file, or parts of it, or modified versions of it, may not be
--- copied, reproduced or transmitted in any form, including
--- reprinting, translation, photocopying or microfilming, or by any
--- means, electronic, mechanical or otherwise, or stored in a
--- retrieval system, or used for any purpose, without the prior
--- written permission of all Owners unless it is explicitly marked as
--- having Classification `Public'.
---
--- Classification: Restricted.
---
--- Owners of this file give notice:
--- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
--- All rights, including copyrights, reserved.
---
--- This file contains or may contain restricted information and is
--- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
--- Notice(s) above do not evidence any actual or intended publication
--- of such source code. This file is additionally subject to the
--- conditions listed in the RESTRICTIONS file and is with NOWARRANTY.
---
--- END OF COPYRIGHT NOTICE
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity wire_connector is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end wire_connector;
-
-architecture STRUCTURE of wire_connector is
-
- signal ready : std_logic;
-
-begin
-
- ready <= FSL_M_Write ;
- FSL_S_Exists <= ready;
- FSL_S_Control <= FSL_M_Control;
- FSL_S_Data <= FSL_M_Data;
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg
deleted file mode 100644
index 5c21947d7d89f4d79f15f93e77129b9ef50547dd..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-hdl_lib_name = compaandesign_com_ipcore2RTL_control_if_1
-hdl_library_clause_name = compaandesign_com_ipcore2RTL_control_if_1_lib
-hdl_lib_uses_synth =
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/control_if.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/src/vhdl/control_if.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/src/vhdl/control_if.vhd
deleted file mode 100644
index e863d323e2df054b50c2dd1e3ce8e809329bf346..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/src/vhdl/control_if.vhd
+++ /dev/null
@@ -1,66 +0,0 @@
--- File automatically generated by KpnMapper
--- For control_if
-
-library ieee;
-use ieee.std_logic_1164.all;
-
---
--- ============================================
--- = PAMETER CONTROLLER =
--- ============================================
---
-
-entity control_if is
- generic (
- RESET_HIGH : natural := 1;
- QUANT : natural := 32
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAM_LD : out std_logic;
- PARAM_DT : out std_logic_vector((QUANT-1) downto 0);
- --
- PARAMETERS_IN_LD : in std_logic;
- PARAMETERS_IN : in std_logic_vector((QUANT-1) downto 0)
-
- );
-end control_if;
-
-architecture fsl_test of control_if is
-
- signal sl_RST : std_logic;
- signal sl_load : std_logic;
- signal sl_data : std_logic_vector((QUANT-1) downto 0);
- signal sl_data_r : std_logic_vector((QUANT-1) downto 0);
-
-begin
-
- sl_RST <= RST when (RESET_HIGH=1) else not RST;
-
- process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (sl_RST='1') then
- sl_load <= '0';
- sl_data <= (others=>'0');
- else
- if (sl_load = '1') then
- sl_load <= '0';
- else
- sl_data <= sl_data_r;
- sl_data_r <= PARAMETERS_IN((QUANT-1) downto 0);
- if(sl_data_r = sl_data) then
- sl_load <= '0';
- else
- sl_load <= '1';
- end if;
- end if;
- end if;
- end if;
- end process;
-
- PARAM_LD <= sl_load;
- PARAM_DT <= sl_DATA;
-
-end architecture fsl_test;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg
deleted file mode 100644
index e1efc20a5cba822b31fed65a22bf8b4f062ab575..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-hdl_lib_name = compaandesign_com_ipcore2RTL_hwn_nd_1_1
-hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_1_1_lib
-hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/ipcore2RTL_hwn_nd_1_execution_unit.vhd
- src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
- src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
- src/vhdl/ipcore2RTL_hwn_nd_1.vhd
- src/vhdl/hwn_nd_1_compaan_outlinedproc0.vhd
- src/vhdl/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/hwn_nd_1_compaan_outlinedproc0.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/hwn_nd_1_compaan_outlinedproc0.vhd
deleted file mode 100644
index 7a436f27bbcd82018d9ae0af2c382ecfeda3262a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/hwn_nd_1_compaan_outlinedproc0.vhd
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-
-
-entity hwn_nd_1_compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end hwn_nd_1_compaan_outlinedproc0;
-
-architecture RTL of hwn_nd_1_compaan_outlinedproc0 is
-
- component hwn_nd_1_compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : hwn_nd_1_compaan_outlinedproc0_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_i => it_i,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd
deleted file mode 100644
index 2f718b6c3c362680e36f7865ddae892c474e641a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd
+++ /dev/null
@@ -1,166 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines an implementation of a
--- function Test pipeline (containig inlined traces)
---
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-
-entity hwn_nd_1_compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end hwn_nd_1_compaan_outlinedproc0_pipeline;
-
-architecture RTL of hwn_nd_1_compaan_outlinedproc0_pipeline is
-
- type type_ref_array is array(natural range<>) of integer; -- range 0 to 2**32 - 1;
- type type_err_array is array(natural range<>) of boolean;
- --
- constant error_int : integer := -1;
- constant reset_int : integer := 0;
- --
- constant ref_tmp1 : type_ref_array := (
-
- 0 => 1,
- 1 => 1,
- 2 => 1,
- 3 => 1,
- 4 => 1,
- 5 => 1,
- 6 => 1,
- 7 => 1,
- 8 => 1,
- 9 => 1
- );
- constant ref_tmp0 : type_ref_array := (
-
- 0 => 165,
- 1 => 155,
- 2 => 65,
- 3 => 238,
- 4 => 134,
- 5 => 179,
- 6 => 123,
- 7 => 131,
- 8 => 229,
- 9 => 203
- );
- --
- signal cntr_i : integer := 0;
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
- signal ipr_tmp1_0 : std_logic_vector(31 downto 0);
- signal ipr_tmp1_ref : std_logic_vector(31 downto 0);
- signal ipr_tmp1_0_ref : std_logic_vector(31 downto 0);
- signal ipr_tmp0_ref : std_logic_vector(31 downto 0);
- signal ipr_tmp0_0_ref : std_logic_vector(31 downto 0);
- -- Iterator registers
- signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Output registers
- signal opr2_tmp0 : std_logic_vector(31 downto 0);
- signal s2_tmp0 : integer;
- -- Ppipeline signals
- signal error_pipe : type_err_array(2 downto 0);
- signal ee : boolean;
- signal ee_valid : boolean;
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- cntr_i <= 0;
- ipr_tmp1 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int, 32));
- ipr_tmp1_0 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int, 32));
- ipr_tmp1_ref <= STD_LOGIC_VECTOR(TO_SIGNED(reset_int, 32));
- ipr_tmp1_0_ref <= STD_LOGIC_VECTOR(TO_SIGNED(reset_int, 32));
- ee_valid <= false;
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- ipr_tmp1_ref <= STD_LOGIC_VECTOR(TO_SIGNED(ref_tmp1(cntr_i),32));
- -- Output Registers
- ipr_tmp0_ref <= STD_LOGIC_VECTOR(TO_SIGNED(ref_tmp0(cntr_i),32));
- -- Iterator Registers
- itr_i <= it_i;
- --
- if (cntr_i < ref_tmp1'Length-1) then
- cntr_i <= cntr_i + 1;
- else
- cntr_i <= 0;
- end if;
- --
- end if;
- -- Pipeline Depth: 3 stages
- -- The min. depth of a test pipeline is 2 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- -- Move reference values one stage
- ipr_tmp1_0 <= ipr_tmp1;
- ipr_tmp1_0_ref <= ipr_tmp1_ref;
- ipr_tmp0_0_ref <= ipr_tmp0_ref;
- error_pipe(0) <= ee;
- ee_valid <= true;
- end if;
- -- STAGE_2
- if( EN(2) = '1' ) then
- if(error_pipe(1)) then
- opr2_tmp0 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int,32));
- else
- opr2_tmp0 <= ipr_tmp0_0_ref;
- end if;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= opr2_tmp0;
- --
- -- PIPE_COMB:
- ee <= ee_valid and (false
- or (ipr_tmp1_0 /= ipr_tmp1_0_ref));
- --
- process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (RST='1') then
- ERROR <= '0';
- elsif (ee) then
- ERROR <= '1';
- end if;
- end if;
- end process;
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1.vhd
deleted file mode 100644
index 9663975df869a8ed769043c36d30cec6f7db2c66..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1.vhd
+++ /dev/null
@@ -1,509 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-
-entity ipcore2RTL_hwn_nd_1 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_2 : out_0
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
-
- -- ED_4 : out_0
- ND_1OP_1_d1_Wr : out std_logic;
- ND_1OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_d1_Full : in std_logic;
- ND_1OP_1_d1_CLK : out std_logic;
- ND_1OP_1_d1_CTRL : out std_logic;
-
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_hwn_nd_1 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 2; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 3; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- CLK : in std_logic;
-
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural:=1;
- N_SYNC_OUT : natural:=1;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0);
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
-
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- signal s_in : std_logic_vector(0 downto 0);
- signal s_out : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- data_in_CLK <= CLK;
- ND_1OP_1_CLK <= CLK;
- ND_1OP_1_d1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- CLK => CLK,
-
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- data_in_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= data_in_Din;
-
- sl_EXISTS(0) <= data_in_Exist ;
- sl_CTRLS(0) <= data_in_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- PENDING => sl_pending_rd,
- UPDATE_ACK => sl_update_ack_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 2
- )
- port map (
- WRITES => sl_WRITES(1 downto 0),
- FULLS => sl_FULLS(1 downto 0),
- CONTROL => sl_lortnoc_wr(1 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_1OP_1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- ND_1OP_1_CTRL <= sl_sof_wr ;
- ND_1OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_1OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- ND_1OP_1_d1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- ND_1OP_1_d1_CTRL <= sl_sof_wr ;
- ND_1OP_1_d1_Wr <= sl_WRITES(1);
- sl_FULLS(1) <= ND_1OP_1_d1_Full;
- sl_lortnoc_wr(1) <= sl_control_wr(1);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- PENDING => sl_pending_wr,
- UPDATE_ACK => sl_update_ack_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_1
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_SYNC_IN => 0,
- N_SYNC_OUT => 0,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- SYNC_IN => s_in,
- SYNC_OUT => s_out,
- PENDING_RD => sl_pending_rd,
- PENDING_WR => sl_pending_wr,
- UPDATE_ACK_RD => sl_update_ack_rd,
- UPDATE_ACK_WR => sl_update_ack_wr,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
deleted file mode 100644
index 680cf27395261ad5f5983f328595ddfd4ce31bf2..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
+++ /dev/null
@@ -1,274 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- alias load_i : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "data_in[i]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
-
- sl_loop_i <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_i_rg>=0;
- e1 <= -sl_loop_i_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port in_1 : EXTERNAL
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "data_in[i]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
deleted file mode 100644
index 12bfe0c134a7ab40556658de865533a38468c08c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
+++ /dev/null
@@ -1,266 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "out_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- --
- alias load_i : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
- signal e0 : boolean;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments (WRITE)
-
- sl_loop_i <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= sl_loop_i_rg=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : ED_2
- sl_CONTROL(0) <= sl_fire and b2std((e0));
-
- -- Convert FIFO Write Port out_2 : ED_4
- sl_CONTROL(1) <= sl_fire and b2std((e0));
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "out_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_execution_unit.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_execution_unit.vhd
deleted file mode 100644
index 9c59f555a2773af8832ba97c5cf18c317ae70af2..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/src/vhdl/ipcore2RTL_hwn_nd_1_execution_unit.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
-
- component hwn_nd_1_compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : hwn_nd_1_compaan_outlinedproc0
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg
deleted file mode 100644
index 68f60d2eaff3b12d42520c3fabce0cd7ff853582..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-hdl_lib_name = compaandesign_com_ipcore2RTL_hwn_nd_2_1
-hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_2_1_lib
-hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/ipcore2RTL_hwn_nd_2_execution_unit.vhd
- src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
- src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
- src/vhdl/ipcore2RTL_hwn_nd_2.vhd
- src/vhdl/hwn_nd_2_transformer.vhd
- src/vhdl/hwn_nd_2_transformer_pipeline.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/hwn_nd_2_transformer.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/hwn_nd_2_transformer.vhd
deleted file mode 100644
index 7b11f143c8004b980de9b6a5e9663c7b8304b958..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/hwn_nd_2_transformer.vhd
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-
-
-entity hwn_nd_2_transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end hwn_nd_2_transformer;
-
-architecture RTL of hwn_nd_2_transformer is
-
- component hwn_nd_2_transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : hwn_nd_2_transformer_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_a => ip_a,
- -- Iterators
- it_j => it_j,
- -- Outputs
- op_b => op_b,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/hwn_nd_2_transformer_pipeline.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/hwn_nd_2_transformer_pipeline.vhd
deleted file mode 100644
index c2308d9ac6cb3e181693880babf8e55269b2366d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/hwn_nd_2_transformer_pipeline.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines an implementation of a
--- function Test pipeline (containig inlined traces)
---
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-
-entity hwn_nd_2_transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end hwn_nd_2_transformer_pipeline;
-
-architecture RTL of hwn_nd_2_transformer_pipeline is
-
- type type_ref_array is array(natural range<>) of integer; -- range 0 to 2**32 - 1;
- type type_err_array is array(natural range<>) of boolean;
- --
- constant error_int : integer := -1;
- constant reset_int : integer := 0;
- --
- constant ref_a : type_ref_array := (
-
- 0 => 165,
- 1 => 247,
- 2 => 195,
- 3 => 69,
- 4 => 212,
- 5 => 44,
- 6 => 157,
- 7 => 93,
- 8 => 246
- );
- constant ref_b : type_ref_array := (
-
- 0 => 247,
- 1 => 195,
- 2 => 69,
- 3 => 212,
- 4 => 44,
- 5 => 157,
- 6 => 93,
- 7 => 246,
- 8 => 122
- );
- --
- signal cntr_i : integer := 0;
- -- Input registers
- signal ipr_a : std_logic_vector(31 downto 0);
- signal ipr_a_0 : std_logic_vector(31 downto 0);
- signal ipr_a_ref : std_logic_vector(31 downto 0);
- signal ipr_a_0_ref : std_logic_vector(31 downto 0);
- signal ipr_b_ref : std_logic_vector(31 downto 0);
- signal ipr_b_0_ref : std_logic_vector(31 downto 0);
- -- Iterator registers
- signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Output registers
- signal opr2_b : std_logic_vector(31 downto 0);
- signal s2_b : integer;
- -- Ppipeline signals
- signal error_pipe : type_err_array(2 downto 0);
- signal ee : boolean;
- signal ee_valid : boolean;
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- cntr_i <= 0;
- ipr_a <= STD_LOGIC_VECTOR(TO_SIGNED(error_int, 32));
- ipr_a_0 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int, 32));
- ipr_a_ref <= STD_LOGIC_VECTOR(TO_SIGNED(reset_int, 32));
- ipr_a_0_ref <= STD_LOGIC_VECTOR(TO_SIGNED(reset_int, 32));
- ee_valid <= false;
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_a <= ip_a;
- ipr_a_ref <= STD_LOGIC_VECTOR(TO_SIGNED(ref_a(cntr_i),32));
- -- Output Registers
- ipr_b_ref <= STD_LOGIC_VECTOR(TO_SIGNED(ref_b(cntr_i),32));
- -- Iterator Registers
- itr_j <= it_j;
- --
- if (cntr_i < ref_a'Length-1) then
- cntr_i <= cntr_i + 1;
- else
- cntr_i <= 0;
- end if;
- --
- end if;
- -- Pipeline Depth: 3 stages
- -- The min. depth of a test pipeline is 2 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- -- Move reference values one stage
- ipr_a_0 <= ipr_a;
- ipr_a_0_ref <= ipr_a_ref;
- ipr_b_0_ref <= ipr_b_ref;
- error_pipe(0) <= ee;
- ee_valid <= true;
- end if;
- -- STAGE_2
- if( EN(2) = '1' ) then
- if(error_pipe(1)) then
- opr2_b <= STD_LOGIC_VECTOR(TO_SIGNED(error_int,32));
- else
- opr2_b <= ipr_b_0_ref;
- end if;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_b <= opr2_b;
- --
- -- PIPE_COMB:
- ee <= ee_valid and (false
- or (ipr_a_0 /= ipr_a_0_ref));
- --
- process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (RST='1') then
- ERROR <= '0';
- elsif (ee) then
- ERROR <= '1';
- end if;
- end if;
- end process;
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2.vhd
deleted file mode 100644
index 25cf2d311877fe18b010fc995047fff42293617d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2.vhd
+++ /dev/null
@@ -1,519 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-
-entity ipcore2RTL_hwn_nd_2 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_1 : in_0
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
-
- -- ED_2 : in_0
- ND_2IP_2_Rd : out std_logic;
- ND_2IP_2_Din : in std_logic_vector(31 downto 0);
- ND_2IP_2_Exist : in std_logic;
- ND_2IP_2_CLK : out std_logic;
- ND_2IP_2_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_1 : out_0
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
-
- -- ED_3 : out_0
- ND_2OP_1_d1_Wr : out std_logic;
- ND_2OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_d1_Full : in std_logic;
- ND_2OP_1_d1_CLK : out std_logic;
- ND_2OP_1_d1_CTRL : out std_logic;
-
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_hwn_nd_2 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 2; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 2; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 3; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- CLK : in std_logic;
-
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- a
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- b
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural:=1;
- N_SYNC_OUT : natural:=1;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0);
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
-
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(2*32-1 downto 0); -- a
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- a
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- b
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- signal s_in : std_logic_vector(0 downto 0);
- signal s_out : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_2IP_1_CLK <= CLK;
- ND_2IP_2_CLK <= CLK;
- ND_2OP_1_CLK <= CLK;
- ND_2OP_1_d1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "a"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 2,
- PORT_WIDTH => 32
- )
- port map (
- CLK => CLK,
-
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(1 downto 0),
- READS => sl_READS(1 downto 0),
- SOFS => sl_CTRLS(1 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(1 downto 0),
- OBTAIN => sl_obtain_rd(1 downto 0),
- RELEASE => sl_release_rd(1 downto 0)
- );
-
- ND_2IP_1_Rd <= sl_READS(0);
- ND_2IP_2_Rd <= sl_READS(1);
-
- sl_IN_PORTS_0 <= ND_2IP_2_Din & ND_2IP_1_Din;
-
- sl_EXISTS <= ND_2IP_2_Exist & ND_2IP_1_Exist ;
- sl_CTRLS <= ND_2IP_2_CTRL & ND_2IP_1_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- PENDING => sl_pending_rd,
- UPDATE_ACK => sl_update_ack_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "b"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 2
- )
- port map (
- WRITES => sl_WRITES(1 downto 0),
- FULLS => sl_FULLS(1 downto 0),
- CONTROL => sl_lortnoc_wr(1 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_2OP_1_Dout <= sl_out_port_0; -- Func. Output param. "b"
- ND_2OP_1_CTRL <= sl_sof_wr ;
- ND_2OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_2OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- ND_2OP_1_d1_Dout <= sl_out_port_0; -- Func. Output param. "b"
- ND_2OP_1_d1_CTRL <= sl_sof_wr ;
- ND_2OP_1_d1_Wr <= sl_WRITES(1);
- sl_FULLS(1) <= ND_2OP_1_d1_Full;
- sl_lortnoc_wr(1) <= sl_control_wr(1);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- PENDING => sl_pending_wr,
- UPDATE_ACK => sl_update_ack_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_2
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_SYNC_IN => 0,
- N_SYNC_OUT => 0,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- SYNC_IN => s_in,
- SYNC_OUT => s_out,
- PENDING_RD => sl_pending_rd,
- PENDING_WR => sl_pending_wr,
- UPDATE_ACK_RD => sl_update_ack_rd,
- UPDATE_ACK_WR => sl_update_ack_wr,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) or sl_READS(1) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
deleted file mode 100644
index 86fe212d49255fc0edb9e5cc26e1ca0b6e423205..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
+++ /dev/null
@@ -1,284 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_j, sl_high_j : integer;
- signal sl_loop_j, sl_loop_j_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_j : std_logic is sl_cntr_en(0);
- alias load_j : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_j : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "in_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
- signal sl_obtain1 : std_logic;
- signal sl_release1 : std_logic;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
-
- sl_loop_j <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_j <= 1;
- sl_high_j <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_j_rg-2>=0;
- e1 <= sl_loop_j_rg-1=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port ND_2IP_1 Argument in_1 : ED_1 : 0 of type IOMM
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- -- Convert FIFO Read Port ND_2IP_2 Argument in_2 : ED_2 : 1 of type IOMM
- sl_obtain1 <= ('1'); -- set obtain/release to const value; not used
- sl_release1 <= ('1');
-
- sl_CONTROL(1) <= sl_fire and b2std((e1));
- OBTAIN(1) <= sl_obtain1;
- RELEASE(1) <= sl_release1;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "in_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
deleted file mode 100644
index 6d71191dba3d389ea6c1487bd64f30a59f299b5e..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
+++ /dev/null
@@ -1,266 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "out_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_j, sl_high_j : integer;
- signal sl_loop_j, sl_loop_j_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_j : std_logic is sl_cntr_en(0);
- --
- alias load_j : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_j : std_logic;
-
- signal e0 : boolean;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments (WRITE)
-
- sl_loop_j <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_j <= 1;
- sl_high_j <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= -sl_loop_j_rg + 8>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : ED_1
- sl_CONTROL(0) <= sl_fire and b2std((e0));
-
- -- Convert FIFO Write Port out_2 : ED_3
- sl_CONTROL(1) <= sl_fire and ('1');
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "out_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_execution_unit.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_execution_unit.vhd
deleted file mode 100644
index 32a729e6b9ab760646973eb08d935c8a32d3a823..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/src/vhdl/ipcore2RTL_hwn_nd_2_execution_unit.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "a"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "b"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
-
- component hwn_nd_2_transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : hwn_nd_2_transformer
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_a => IN_PORT_0,
- -- Iterators
- it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_b => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg
deleted file mode 100644
index 3378a88e561221d979a46bf2bbf7a43b9a27f507..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-hdl_lib_name = compaandesign_com_ipcore2RTL_hwn_nd_3_1
-hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_3_1_lib
-hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/ipcore2RTL_hwn_nd_3_execution_unit.vhd
- src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
- src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
- src/vhdl/ipcore2RTL_hwn_nd_3.vhd
- src/vhdl/hwn_nd_3_compaan_outlinedproc1.vhd
- src/vhdl/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/hwn_nd_3_compaan_outlinedproc1.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/hwn_nd_3_compaan_outlinedproc1.vhd
deleted file mode 100644
index a09854e76a2e3302f826f659118a4405b8606030..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/hwn_nd_3_compaan_outlinedproc1.vhd
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-
-
-entity hwn_nd_3_compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end hwn_nd_3_compaan_outlinedproc1;
-
-architecture RTL of hwn_nd_3_compaan_outlinedproc1 is
-
- component hwn_nd_3_compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : hwn_nd_3_compaan_outlinedproc1_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_x => it_x,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd
deleted file mode 100644
index dc7cbf698e8eb6177f176ced1312b101ce8aa8d1..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd
+++ /dev/null
@@ -1,166 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines an implementation of a
--- function Test pipeline (containig inlined traces)
---
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-
-entity hwn_nd_3_compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end hwn_nd_3_compaan_outlinedproc1_pipeline;
-
-architecture RTL of hwn_nd_3_compaan_outlinedproc1_pipeline is
-
- type type_ref_array is array(natural range<>) of integer; -- range 0 to 2**32 - 1;
- type type_err_array is array(natural range<>) of boolean;
- --
- constant error_int : integer := -1;
- constant reset_int : integer := 0;
- --
- constant ref_tmp1 : type_ref_array := (
-
- 0 => 165,
- 1 => 247,
- 2 => 195,
- 3 => 69,
- 4 => 212,
- 5 => 44,
- 6 => 157,
- 7 => 93,
- 8 => 246,
- 9 => 122
- );
- constant ref_tmp0 : type_ref_array := (
-
- 0 => 84,
- 1 => 150,
- 2 => 114,
- 3 => 19,
- 4 => 158,
- 5 => 240,
- 6 => 60,
- 7 => 38,
- 8 => 206,
- 9 => 162
- );
- --
- signal cntr_i : integer := 0;
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
- signal ipr_tmp1_0 : std_logic_vector(31 downto 0);
- signal ipr_tmp1_ref : std_logic_vector(31 downto 0);
- signal ipr_tmp1_0_ref : std_logic_vector(31 downto 0);
- signal ipr_tmp0_ref : std_logic_vector(31 downto 0);
- signal ipr_tmp0_0_ref : std_logic_vector(31 downto 0);
- -- Iterator registers
- signal itr_x : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Output registers
- signal opr2_tmp0 : std_logic_vector(31 downto 0);
- signal s2_tmp0 : integer;
- -- Ppipeline signals
- signal error_pipe : type_err_array(2 downto 0);
- signal ee : boolean;
- signal ee_valid : boolean;
-
-begin
-
- PIPE_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- cntr_i <= 0;
- ipr_tmp1 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int, 32));
- ipr_tmp1_0 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int, 32));
- ipr_tmp1_ref <= STD_LOGIC_VECTOR(TO_SIGNED(reset_int, 32));
- ipr_tmp1_0_ref <= STD_LOGIC_VECTOR(TO_SIGNED(reset_int, 32));
- ee_valid <= false;
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- ipr_tmp1_ref <= STD_LOGIC_VECTOR(TO_SIGNED(ref_tmp1(cntr_i),32));
- -- Output Registers
- ipr_tmp0_ref <= STD_LOGIC_VECTOR(TO_SIGNED(ref_tmp0(cntr_i),32));
- -- Iterator Registers
- itr_x <= it_x;
- --
- if (cntr_i < ref_tmp1'Length-1) then
- cntr_i <= cntr_i + 1;
- else
- cntr_i <= 0;
- end if;
- --
- end if;
- -- Pipeline Depth: 3 stages
- -- The min. depth of a test pipeline is 2 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- -- Move reference values one stage
- ipr_tmp1_0 <= ipr_tmp1;
- ipr_tmp1_0_ref <= ipr_tmp1_ref;
- ipr_tmp0_0_ref <= ipr_tmp0_ref;
- error_pipe(0) <= ee;
- ee_valid <= true;
- end if;
- -- STAGE_2
- if( EN(2) = '1' ) then
- if(error_pipe(1)) then
- opr2_tmp0 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int,32));
- else
- opr2_tmp0 <= ipr_tmp0_0_ref;
- end if;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= opr2_tmp0;
- --
- -- PIPE_COMB:
- ee <= ee_valid and (false
- or (ipr_tmp1_0 /= ipr_tmp1_0_ref));
- --
- process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (RST='1') then
- ERROR <= '0';
- elsif (ee) then
- ERROR <= '1';
- end if;
- end if;
- end process;
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3.vhd
deleted file mode 100644
index 4630bc36f9e4253a4d26778a8cdd4d14f9747c09..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3.vhd
+++ /dev/null
@@ -1,504 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-
-entity ipcore2RTL_hwn_nd_3 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_3 : in_0
- ND_3IP_3_Rd : out std_logic;
- ND_3IP_3_Din : in std_logic_vector(31 downto 0);
- ND_3IP_3_Exist : in std_logic;
- ND_3IP_3_CLK : out std_logic;
- ND_3IP_3_CTRL : in std_logic;
-
- -- ED_4 : in_0
- ND_3IP_4_Rd : out std_logic;
- ND_3IP_4_Din : in std_logic_vector(31 downto 0);
- ND_3IP_4_Exist : in std_logic;
- ND_3IP_4_CLK : out std_logic;
- ND_3IP_4_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
-
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_hwn_nd_3 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 2; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 3; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := WRAP; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- CLK : in std_logic;
-
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural:=1;
- N_SYNC_OUT : natural:=1;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0);
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
-
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(2*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- signal s_in : std_logic_vector(0 downto 0);
- signal s_out : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_3IP_3_CLK <= CLK;
- ND_3IP_4_CLK <= CLK;
- data_out_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 2,
- PORT_WIDTH => 32
- )
- port map (
- CLK => CLK,
-
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(1 downto 0),
- READS => sl_READS(1 downto 0),
- SOFS => sl_CTRLS(1 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(1 downto 0),
- OBTAIN => sl_obtain_rd(1 downto 0),
- RELEASE => sl_release_rd(1 downto 0)
- );
-
- ND_3IP_3_Rd <= sl_READS(0);
- ND_3IP_4_Rd <= sl_READS(1);
-
- sl_IN_PORTS_0 <= ND_3IP_4_Din & ND_3IP_3_Din;
-
- sl_EXISTS <= ND_3IP_4_Exist & ND_3IP_3_Exist ;
- sl_CTRLS <= ND_3IP_4_CTRL & ND_3IP_3_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- PENDING => sl_pending_rd,
- UPDATE_ACK => sl_update_ack_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- data_out_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- data_out_CTRL <= sl_sof_wr ;
- data_out_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= data_out_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- PENDING => sl_pending_wr,
- UPDATE_ACK => sl_update_ack_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_3
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_SYNC_IN => 0,
- N_SYNC_OUT => 0,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- SYNC_IN => s_in,
- SYNC_OUT => s_out,
- PENDING_RD => sl_pending_rd,
- PENDING_WR => sl_pending_wr,
- UPDATE_ACK_RD => sl_update_ack_rd,
- UPDATE_ACK_WR => sl_update_ack_wr,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) or sl_READS(1) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
deleted file mode 100644
index f82a38275b027e1b98feb61e7d133da5937fb0bc..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
+++ /dev/null
@@ -1,284 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- alias load_x : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "in_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
- signal sl_obtain1 : std_logic;
- signal sl_release1 : std_logic;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
-
- sl_loop_x <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_x_rg-1>=0;
- e1 <= sl_loop_x_rg=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port ND_3IP_3 Argument in_1 : ED_3 : 0 of type IOMM
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- -- Convert FIFO Read Port ND_3IP_4 Argument in_2 : ED_4 : 1 of type IOMM
- sl_obtain1 <= ('1'); -- set obtain/release to const value; not used
- sl_release1 <= ('1');
-
- sl_CONTROL(1) <= sl_fire and b2std((e1));
- OBTAIN(1) <= sl_obtain1;
- RELEASE(1) <= sl_release1;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "in_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
deleted file mode 100644
index 1f3ee52caf561abfc4a03846bde245a290ebdc37..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
+++ /dev/null
@@ -1,264 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1_lib;
-use compaandesign_com_common_hwnode_1_lib.all;
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "data_out[x]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- --
- alias load_x : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- signal e0, e1 : boolean;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments (WRITE)
-
- sl_loop_x <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= sl_loop_x_rg>=0;
- e1 <= -sl_loop_x_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : EXTERNAL
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "data_out[x]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_execution_unit.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_execution_unit.vhd
deleted file mode 100644
index e6f5c82c8c32d25909636a0a53b8918aec82cf07..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/src/vhdl/ipcore2RTL_hwn_nd_3_execution_unit.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1_lib;
-use compaandesign_com_common_common_1_lib.hw_node_pkg.all;
-
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
-
- component hwn_nd_3_compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : hwn_nd_3_compaan_outlinedproc1
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_x => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg
deleted file mode 100644
index 133b6ea234f126418c7467490da281470ce4cc53..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-hdl_lib_name = compaandesign_com_ipcore2RTL_register_rf_1
-hdl_library_clause_name = compaandesign_com_ipcore2RTL_register_rf_1_lib
-hdl_lib_uses_synth =
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/register_rf.vhd
-
-test_bench_files =
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/src/vhdl/register_rf.vhd b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/src/vhdl/register_rf.vhd
deleted file mode 100644
index abceca506cb710453358e486970983df59b69bfa..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/src/vhdl/register_rf.vhd
+++ /dev/null
@@ -1,76 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity register_rf is
-generic (
- C_reg_rf_address : std_logic_vector(18 downto 0) := B"0000000000000000000" -- 0
-);
-port (
- dp_rst : in std_logic;
- dp_clk : in std_logic;
- mm_rst : in std_logic;
- mm_clk : in std_logic;
-
- -- Interface to PCIe
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
-
- -- Interface to reg reg
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0)
-);
-end register_rf;
-
-architecture RTL of register_rf is
-
-signal sl_read_data : std_logic_vector(32-1 downto 0) := (others=>'0');
-
-begin
-
-process (mm_clk, mm_rst)
- begin
- if (rising_edge(mm_clk)) then
- if (mm_rst = '1') then
- reg_rf_write_en <= '0';
- reg_rf_read_en <= '0';
- else
- if ( (address(18 downto 2) = C_reg_rf_address(18 downto 2)) and write_en = '1') then
- reg_rf_write_data <= write_data(32-1 downto 0);
- reg_rf_write_en <= '1';
- else
- reg_rf_write_en <= '0';
- end if;
-
- if( (address(18 downto 2) = C_reg_rf_address(18 downto 2)) and read_en= '1') then
- reg_rf_read_en <= '1';
- else
- reg_rf_read_en <= '0';
- end if;
- end if;
- end if;
-end process;
-
-process (mm_clk, mm_rst)
-begin
- if (rising_edge(mm_clk)) then
- if (mm_rst = '1') then
- else
- case address(18 downto 2) is
- when (C_reg_rf_address(18 downto 2) ) =>
- sl_read_data(32-1 downto 0) <= reg_rf_read_data;
- when others =>
- sl_read_data <= (others => '0');
- end case;
- end if;
- end if;
-end process;
-
-read_data <= sl_read_data;
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg
deleted file mode 100644
index 2479f4683414a5148729888b86113420baa6357d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-hdl_lib_name = ipcore
-hdl_library_clause_name = ipcore_lib
-
-hdl_lib_uses_synth = compaandesign_com_ipcore2RTL_hwn_nd_1_1 compaandesign_com_ipcore2RTL_hwn_nd_2_1 compaandesign_com_ipcore2RTL_register_rf_1 compaandesign_com_ipcore2RTL_hwn_nd_3_1 compaandesign_com_ipcore2RTL_control_if_1 compaandesign_com_common_altera_1
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
- src/vhdl/ipcore.vhd
- src/vhdl/ipcore2RTL_control_if_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_ed_1_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_ed_2_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_ed_3_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_ed_4_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
- src/vhdl/ipcore2RTL_register_rf_ip_wrapper.vhd
-
-test_bench_files =
- src/vhdl/system_ext_TB.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/isim_timeline.tcl b/applications/compaan/libraries/ipcore_trace/astron/isim_timeline.tcl
deleted file mode 100644
index 46e4dabd53203e11c676445ebe922a333874f5be..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/isim_timeline.tcl
+++ /dev/null
@@ -1,11 +0,0 @@
-add wave -divider FIFO
-wave add SUT/ipcore2RTL_hwn_nd_1_ip/ipcore2RTL_hwn_nd_1_ip_wrapper_ip/EX/FUNC/CTRL/read
-wave add SUT/ipcore2RTL_hwn_nd_1_ip/ipcore2RTL_hwn_nd_1_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe
-wave add SUT/ipcore2RTL_hwn_nd_1_ip/ipcore2RTL_hwn_nd_1_ip_wrapper_ip/EX/FUNC/CTRL/write
-wave add SUT/ipcore2RTL_hwn_nd_2_ip/ipcore2RTL_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/read
-wave add SUT/ipcore2RTL_hwn_nd_2_ip/ipcore2RTL_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe
-wave add SUT/ipcore2RTL_hwn_nd_2_ip/ipcore2RTL_hwn_nd_2_ip_wrapper_ip/EX/FUNC/CTRL/write
-wave add SUT/ipcore2RTL_hwn_nd_3_ip/ipcore2RTL_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/read
-wave add SUT/ipcore2RTL_hwn_nd_3_ip/ipcore2RTL_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/execute_pipe
-wave add SUT/ipcore2RTL_hwn_nd_3_ip/ipcore2RTL_hwn_nd_3_ip_wrapper_ip/EX/FUNC/CTRL/write
-add wave -divider FIFO
diff --git a/applications/compaan/libraries/ipcore_trace/astron/isim_wave.tcl b/applications/compaan/libraries/ipcore_trace/astron/isim_wave.tcl
deleted file mode 100644
index ac0edeae4b8fee111ef4c508214d219d32c7b6a8..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/isim_wave.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-add wave -divider FIFO_BEGIN
-add wave -radix unsigned -label ed_1 /system_ext_tb/SUT/ipcore2RTL_ed_1/FSL_S_Data
-add wave -radix unsigned -label ed_2 /system_ext_tb/SUT/ipcore2RTL_ed_2/FSL_S_Data
-add wave -radix unsigned -label ed_3 /system_ext_tb/SUT/ipcore2RTL_ed_3/FSL_S_Data
-add wave -radix unsigned -label ed_4 /system_ext_tb/SUT/ipcore2RTL_ed_4/FSL_S_Data
-add wave -divider FIFO_END
diff --git a/applications/compaan/libraries/ipcore_trace/astron/isim_wave_vivado.tcl b/applications/compaan/libraries/ipcore_trace/astron/isim_wave_vivado.tcl
deleted file mode 100644
index 87f34948bfb6369719a55b68356cf18e5201c717..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/isim_wave_vivado.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-add_wave_divider {FIFO DATA}
-add_wave {/system_ext_TB/SUT/ipcore2RTL_ed_1/fsl_s_data } -name ed_1 -radix unsigned
-add_wave {/system_ext_TB/SUT/ipcore2RTL_ed_2/fsl_s_data } -name ed_2 -radix unsigned
-add_wave {/system_ext_TB/SUT/ipcore2RTL_ed_3/fsl_s_data } -name ed_3 -radix unsigned
-add_wave {/system_ext_TB/SUT/ipcore2RTL_ed_4/fsl_s_data } -name ed_4 -radix unsigned
-add_wave_divider {FIFO DATA}
diff --git a/applications/compaan/libraries/ipcore_trace/astron/modelsim_system.do b/applications/compaan/libraries/ipcore_trace/astron/modelsim_system.do
deleted file mode 100644
index be1fb0ce4ee8622a52d499b1cf45424ddc0199c3..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/modelsim_system.do
+++ /dev/null
@@ -1,146 +0,0 @@
-transcript on
-
-onerror {quit -f}
-onbreak {quit -f}
-config wave -signalnamewidth 1
-
-if {[file exists rtl_work]} {
- vdel -lib rtl_work -all
-}
-vlib rtl_work
-vmap work rtl_work
-
-if {[file exists technology_lib]} {
- vdel -lib technology_lib -all
-}
-vlib technology_lib
-vmap technology_lib technology_lib
-
-if {[file exists common_lib]} {
- vdel -lib common_lib -all
-}
-vlib common_lib
-vmap common_lib common_lib
-
-vlib ip_stratixiv_fifo_lib
-vmap ip_stratixiv_fifo_lib ip_stratixiv_fifo_lib
-
-vlib ip_arria10_fifo_lib
-vmap ip_arria10_fifo_lib ip_arria10_fifo_lib
-
-vlib tech_fifo_lib
-vmap tech_fifo_lib tech_fifo_lib
-
-vlib dp_lib
-vmap dp_lib dp_lib
-
-set SVNROOT c:/Users/Bart/projects/
-set RadioHDL ${SVNROOT}/RadioHDL
-set UniBoard ${SVNROOT}/UniBoard
-vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_pkg.vhd
-vcom -93 -work work ${RadioHDL}/libraries/technology/technology_pkg.vhd
-vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_pkg.vhd
-vcom -93 -work work ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
-vcom -93 -work technology_lib ${RadioHDL}/libraries/technology/technology_select_pkg.vhd
-
-vcom -93 -work ip_arria10_fifo_lib ${RadioHDL}/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
-
-vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc.vhd
-vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_sc.vhd
-vcom -93 -work ip_stratixiv_fifo_lib ${RadioHDL}/libraries/technology/ip_stratixiv/fifo/ip_stratixiv_fifo_dc_mixed_widths.vhd
-
-vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_component_pkg.vhd
-vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc.vhd
-vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_sc.vhd
-vcom -93 -work tech_fifo_lib ${RadioHDL}/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
-vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
-vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_areset.vhd
-
-vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
-vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_increase.vhd
-vcom -93 -work dp_lib ${UniBoard}/Firmware/modules/dp/src/vhdl/dp_latency_adapter.vhd
-
-vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_sc.vhd
-vcom -93 -work common_lib ${RadioHDL}/libraries/base/common/src/vhdl/common_fifo_dc.vhd
-vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
-vcom -93 -work dp_lib ${RadioHDL}/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
-
-vcom -93 -work common_lib ${UniBoard}/Firmware/modules/common/src/vhdl/common_async.vhd
-
-# -- Compaan Specific
-vlib compaandesign_com_common_common_1
-vmap compaandesign_com_common_common_1 compaandesign_com_common_common_1
-vcom -93 -work compaandesign_com_common_common_1 {compaandesign_com/common/common/1/hw_node_pkg.vhd}
-
-vlib compaandesign_com_common_hwnode_1
-vmap compaandesign_com_common_hwnode_1 compaandesign_com_common_hwnode_1
-#vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/read_mmux.vhd}
-vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/parameters.vhd}
-vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/counter.vhd}
-vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/write_demux.vhd}
-vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/read_mux.vhd}
-vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/it_mul.vhd}
-vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/it_mod.vhd}
-vcom -93 -work compaandesign_com_common_hwnode_1 {compaandesign_com/common/hwnode/1/controller.vhd}
-
-vlib compaandesign_com_common_fifo_1
-vmap compaandesign_com_common_fifo_1 compaandesign_com_common_fifo_1
-vcom -93 -work compaandesign_com_common_fifo_1 {compaandesign_com/common/altera/1/fsl_v20.vhd}
-
-
-vlib compaandesign_com_ipcore2RTL_hwn_nd_1_1
-vmap compaandesign_com_ipcore2RTL_hwn_nd_1_1 compaandesign_com_ipcore2RTL_hwn_nd_1_1
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_1_1 {compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_1_1 {compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_1_1 {compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_1_1 {compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_1_1 {compaandesign_com/ipcore2RTL/hwn_nd_1/1/hwn_nd_1_compaan_outlinedproc0.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_1_1 {compaandesign_com/ipcore2RTL/hwn_nd_1/1/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd}
-
-vlib compaandesign_com_ipcore2RTL_hwn_nd_2_1
-vmap compaandesign_com_ipcore2RTL_hwn_nd_2_1 compaandesign_com_ipcore2RTL_hwn_nd_2_1
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_2_1 {compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_2_1 {compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_2_1 {compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_2_1 {compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_2_1 {compaandesign_com/ipcore2RTL/hwn_nd_2/1/hwn_nd_2_transformer.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_2_1 {compaandesign_com/ipcore2RTL/hwn_nd_2/1/hwn_nd_2_transformer_pipeline.vhd}
-
-vlib compaandesign_com_ipcore2RTL_hwn_nd_3_1
-vmap compaandesign_com_ipcore2RTL_hwn_nd_3_1 compaandesign_com_ipcore2RTL_hwn_nd_3_1
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_3_1 {compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_3_1 {compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_3_1 {compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_3_1 {compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_3_1 {compaandesign_com/ipcore2RTL/hwn_nd_3/1/hwn_nd_3_compaan_outlinedproc1.vhd}
-vcom -93 -work compaandesign_com_ipcore2RTL_hwn_nd_3_1 {compaandesign_com/ipcore2RTL/hwn_nd_3/1/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd}
-
-vlib compaandesign_com_ipcore2RTL_control_if_1
-vmap compaandesign_com_ipcore2RTL_control_if_1 compaandesign_com_ipcore2RTL_control_if_1
-vcom -93 -work compaandesign_com_ipcore2RTL_control_if_1 {compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd}
-
-vlib compaandesign_com_ipcore2RTL_register_rf_1
-vmap compaandesign_com_ipcore2RTL_register_rf_1 compaandesign_com_ipcore2RTL_register_rf_1
-vcom -93 -work compaandesign_com_ipcore2RTL_register_rf_1 {compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd}
-
-
-
-
-
-
-vcom -93 -work work {system_ext_TB.vhd}
-
-set strlist [glob *.vhd]
-foreach strfile $strlist {
- set file_name $strfile
-vcom -93 -work work $file_name
-}
-
-vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv -L common_lib -L ip_stratixiv_fifo_lib -L tech_fifo_lib -L dp_lib -L technology_lib -L rtl_work -L work -L compaandesign_com_common_hwnode_1 -L compaandesign_com_common_fifo_1 -L compaandesign_com_common_common_1 -L compaandesign_com_ipcore2RTL_hwn_nd_1_1 -L compaandesign_com_ipcore2RTL_hwn_nd_2_1 -L compaandesign_com_ipcore2RTL_register_rf_1 -L compaandesign_com_ipcore2RTL_control_if_1 -L compaandesign_com_ipcore2RTL_hwn_nd_3_1 -voptargs="+acc" system_ext_TB
-add wave *
-view structure
-view signals
-source isim_wave.tcl
-run -all
-quit -f
-
diff --git a/applications/compaan/libraries/ipcore_trace/astron/run_quartus.tcl b/applications/compaan/libraries/ipcore_trace/astron/run_quartus.tcl
deleted file mode 100644
index 8f4c212c62acb12a4f3689c0eb0cc629f27fd72d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/run_quartus.tcl
+++ /dev/null
@@ -1,100 +0,0 @@
-# Load Quartus II Tcl Project package
-package require ::quartus::project
-
-set need_to_close_project 0
-set make_assignments 1
-
-# Check that the right project is open
-if {[is_project_open]} {
- if {[string compare $quartus(project) "ipcore"]} {
- puts "Project ipcore is not open"
- set make_assignments 0
-}
-} else {
- # Only open if not already open
- if {[project_exists ipcore]} {
- project_open -revision ipcore ipcore
- } else {
- project_new -revision ipcore ipcore
- }
-}
-set need_to_close_project 1
-
-# Make assignments
-if {$make_assignments} {
- set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
- set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:26 JANUARY 22, 2015"
- set_global_assignment -name LAST_QUARTUS_VERSION 12.0
- set_global_assignment -name FAMILY "Stratix V"
- set_global_assignment -name TOP_LEVEL_ENTITY ipcore
- set_global_assignment -name DEVICE auto
- set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
- set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/write_demux.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mux.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/read_mmux.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/parameters.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mul.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/it_mod.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/counter.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/hwnode/1/controller.vhd -library compaandesign_com_common_hwnode_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/altera/1/fsl_v20.vhd -library compaandesign_com_common_fifo_1
- set_global_assignment -name VHDL_FILE compaandesign_com/common/common/1/hw_node_pkg.vhd -library compaandesign_com_common_common_1
-
-
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_execution_unit.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_1_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_1_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_1_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_1/1/ipcore2RTL_hwn_nd_1.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_1_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_1/1/hwn_nd_1_compaan_outlinedproc0.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_1_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_1/1/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_1_1
-
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_execution_unit.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_2_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_2_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_2_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_2/1/ipcore2RTL_hwn_nd_2.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_2_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_2/1/hwn_nd_2_transformer.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_2_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_2/1/hwn_nd_2_transformer_pipeline.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_2_1
-
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_execution_unit.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_3_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_3_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_3_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_3_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_3/1/hwn_nd_3_compaan_outlinedproc1.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_3_1
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/hwn_nd_3/1/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd -library compaandesign_com_ipcore2RTL_hwn_nd_3_1
-
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/control_if/1/control_if.vhd -library compaandesign_com_ipcore2RTL_control_if_1
-
- set_global_assignment -name VHDL_FILE compaandesign_com/ipcore2RTL/register_rf/1/register_rf.vhd -library compaandesign_com_ipcore2RTL_register_rf_1
-
-
-
-
-# add functions of Laura node into a library
-
-# add wrapper to library work
- set strlist [glob *.vhd]
- foreach strfile $strlist {
- set file_name $strfile
- set_global_assignment -name VHDL_FILE $file_name -library work
- }
-
-# testbench information
-set_global_assignment -name VHDL_FILE system_ext_TB.vhd -library work
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ipcore -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_NAME ipcore -section_id eda_simulation
-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME ipcore -section_id ipcore
-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ipcore -section_id ipcore
-set_global_assignment -name EDA_TEST_BENCH_FILE system_ext_TB.vhd -section_id ipcore -library work
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-# Commit assignments
-export_assignments
-
-# Close project
-if {$need_to_close_project} {
- project_close
-}
-}
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore.vhd
deleted file mode 100644
index 5532d4fb07abe9dbba1d04bd954987681ea65338..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore.vhd
+++ /dev/null
@@ -1,584 +0,0 @@
--------------------------------------------------------------------------------
--- TOP LEVEL
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity ipcore is
- port (
- data_in_Data : in std_logic_vector(31 downto 0 );
- data_in_Control : in std_logic;
- data_in_Read : out std_logic;
- data_in_Exists : in std_logic;
-
- data_out_Data : out std_logic_vector(31 downto 0 );
- data_out_Control : out std_logic;
- data_out_Write : out std_logic;
- data_out_Full : in std_logic;
-
- TEST_STOP : out std_logic_vector(2 downto 0 );
- TEST_ERROR : out std_logic_vector(2 downto 0 );
- TEST_FIFO_FULL : out std_logic_vector(3 downto 0 );
- TEST_BLOCK_RD : out std_logic_vector(2 downto 0 );
- address : in std_logic_vector(18 downto 0 );
- read_data : out std_logic_vector(31 downto 0 );
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0 );
-
- MM_CLK : in std_logic;
- MM_RST : in std_logic;
- KPN_CLK : in std_logic;
- KPN_RST : in std_logic
- );
-end ipcore;
-
-architecture STRUCTURE of ipcore is
-
- component ipcore2RTL_hwn_nd_1_ip_wrapper is
- port (
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
-
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
-
- ND_1OP_1_d1_Wr : out std_logic;
- ND_1OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_d1_Full : in std_logic;
- ND_1OP_1_d1_CLK : out std_logic;
- ND_1OP_1_d1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
-
- RST : in std_logic;
- CLK : in std_logic
- );
- end component;
-
- component ipcore2RTL_hwn_nd_2_ip_wrapper is
- port (
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
-
- ND_2IP_2_Rd : out std_logic;
- ND_2IP_2_Din : in std_logic_vector(31 downto 0);
- ND_2IP_2_Exist : in std_logic;
- ND_2IP_2_CLK : out std_logic;
- ND_2IP_2_CTRL : in std_logic;
-
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
-
- ND_2OP_1_d1_Wr : out std_logic;
- ND_2OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_d1_Full : in std_logic;
- ND_2OP_1_d1_CLK : out std_logic;
- ND_2OP_1_d1_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
-
- RST : in std_logic;
- CLK : in std_logic
- );
- end component;
-
- component ipcore2RTL_hwn_nd_3_ip_wrapper is
- port (
- ND_3IP_3_Rd : out std_logic;
- ND_3IP_3_Din : in std_logic_vector(31 downto 0);
- ND_3IP_3_Exist : in std_logic;
- ND_3IP_3_CLK : out std_logic;
- ND_3IP_3_CTRL : in std_logic;
-
- ND_3IP_4_Rd : out std_logic;
- ND_3IP_4_Din : in std_logic_vector(31 downto 0);
- ND_3IP_4_Exist : in std_logic;
- ND_3IP_4_CLK : out std_logic;
- ND_3IP_4_CTRL : in std_logic;
-
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
-
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
-
- RST : in std_logic;
- CLK : in std_logic
- );
- end component;
-
-component ipcore2RTL_control_if_ip_wrapper is
- port (
- PARAM_DT : out std_logic_vector(31 downto 0);
- PARAM_LD : out std_logic;
- PARAMETERS_IN : in std_logic_vector(31 downto 0);
- PARAMETERS_IN_LD : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
-
- );
-end component;
-
-component ipcore2RTL_register_rf_ip_wrapper is
- port (
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0);
- DP_RST : in std_logic;
- DP_CLK : in std_logic;
- MM_RST : in std_logic;
- MM_CLK : in std_logic
- );
-end component;
-
- component ipcore2RTL_ed_1_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
- component ipcore2RTL_ed_2_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
- component ipcore2RTL_ed_3_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
- component ipcore2RTL_ed_4_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
- -- Internal signals
-
- signal signal_ed_2_out_FSL_M_Control : std_logic;
- signal signal_ed_2_out_FSL_M_Data : std_logic_vector(0 to 31);
- signal signal_ed_2_out_FSL_M_Full : std_logic;
- signal signal_ed_2_out_FSL_M_Write : std_logic;
- signal signal_ed_4_out_FSL_M_Control : std_logic;
- signal signal_ed_4_out_FSL_M_Data : std_logic_vector(0 to 31);
- signal signal_ed_4_out_FSL_M_Full : std_logic;
- signal signal_ed_4_out_FSL_M_Write : std_logic;
- signal signal_ed_1_in_FSL_S_Control : std_logic;
- signal signal_ed_1_in_FSL_S_Data : std_logic_vector(0 to 31);
- signal signal_ed_1_in_FSL_S_Exists : std_logic;
- signal signal_ed_1_in_FSL_S_Read : std_logic;
- signal signal_ed_2_in_FSL_S_Control : std_logic;
- signal signal_ed_2_in_FSL_S_Data : std_logic_vector(0 to 31);
- signal signal_ed_2_in_FSL_S_Exists : std_logic;
- signal signal_ed_2_in_FSL_S_Read : std_logic;
- signal signal_ed_1_out_FSL_M_Control : std_logic;
- signal signal_ed_1_out_FSL_M_Data : std_logic_vector(0 to 31);
- signal signal_ed_1_out_FSL_M_Full : std_logic;
- signal signal_ed_1_out_FSL_M_Write : std_logic;
- signal signal_ed_3_out_FSL_M_Control : std_logic;
- signal signal_ed_3_out_FSL_M_Data : std_logic_vector(0 to 31);
- signal signal_ed_3_out_FSL_M_Full : std_logic;
- signal signal_ed_3_out_FSL_M_Write : std_logic;
- signal signal_ed_3_in_FSL_S_Control : std_logic;
- signal signal_ed_3_in_FSL_S_Data : std_logic_vector(0 to 31);
- signal signal_ed_3_in_FSL_S_Exists : std_logic;
- signal signal_ed_3_in_FSL_S_Read : std_logic;
- signal signal_ed_4_in_FSL_S_Control : std_logic;
- signal signal_ed_4_in_FSL_S_Data : std_logic_vector(0 to 31);
- signal signal_ed_4_in_FSL_S_Exists : std_logic;
- signal signal_ed_4_in_FSL_S_Read : std_logic;
-
- -- AD HOC Internal signals
-
- signal signal_hwn_nd_1_STOP : std_logic;
- signal signal_hwn_nd_1_ERROR : std_logic;
- signal signal_hwn_nd_1_BLOCK_RD : std_logic;
- signal signal_hwn_nd_2_STOP : std_logic;
- signal signal_hwn_nd_2_ERROR : std_logic;
- signal signal_hwn_nd_2_BLOCK_RD : std_logic;
- signal signal_hwn_nd_3_STOP : std_logic;
- signal signal_hwn_nd_3_ERROR : std_logic;
- signal signal_hwn_nd_3_BLOCK_RD : std_logic;
- signal signal_ed_1_FIFO_FULL : std_logic;
- signal signal_ed_2_FIFO_FULL : std_logic;
- signal signal_ed_3_FIFO_FULL : std_logic;
- signal signal_ed_4_FIFO_FULL : std_logic;
- signal signal_PARAM_DT : std_logic_vector(31 downto 0);
- signal signal_PARAM_LD : std_logic;
- signal signal_PARAMETERS : std_logic_vector(31 downto 0);
- signal signal_PARAMETERS_LD : std_logic;
- signal signal_address : std_logic_vector(18 downto 0);
- signal signal_read_data : std_logic_vector(31 downto 0);
- signal signal_write_data : std_logic_vector(31 downto 0);
- signal signal_read_en : std_logic;
- signal signal_write_en : std_logic;
-
- -- Hierarchical signals
-
- signal I_data_in_Control : std_logic;
- signal I_data_in_Data : std_logic_vector(31 downto 0);
- signal I_data_in_Exists : std_logic;
- signal I_data_in_Read : std_logic;
- signal I_data_out_Control : std_logic;
- signal I_data_out_Data : std_logic_vector(31 downto 0);
- signal I_data_out_Full : std_logic;
- signal I_data_out_Write : std_logic;
-
- -- Default signals
-
- signal net_gnd0 : std_logic;
- signal net_gnd16 : std_logic_vector(15 downto 0);
-
- signal mm_clk_s : std_logic;
- signal mm_rst_s : std_logic;
- signal sys_clk_s : std_logic;
- signal sys_rst_s : std_logic;
-
- signal signal_reg_rf_read_data : std_logic_vector(31 downto 0);
- signal signal_reg_rf_read_en : std_logic;
- signal signal_reg_rf_write_en : std_logic;
- signal signal_reg_rf_write_data : std_logic_vector(31 downto 0);
-
- -- START the actual definition of a Design
-
-begin
-
- -- Connect Clock
-
- mm_clk_s <= MM_CLK;
- mm_rst_s <= MM_RST;
- sys_clk_s <= KPN_CLK;
- sys_rst_s <= KPN_RST;
-
- -- Connect parameters
- signal_PARAMETERS <= signal_reg_rf_write_data;
- signal_PARAMETERS_LD <= signal_reg_rf_write_en;
-
- -- Connect Hiercical Interconnections
-
- -- Hierarchical signals -3- compaandesign.com:ipcore2RTL:design_ipcore:1:data_in
- I_data_in_Data <= data_in_Data;
- I_data_in_Control <= data_in_Control;
- data_in_Read <= I_data_in_Read;
- I_data_in_Exists <= data_in_Exists;
- -- Hierarchical signals -3- compaandesign.com:ipcore2RTL:design_ipcore:1:data_out
- data_out_Data <= I_data_out_Data;
- data_out_Control <= I_data_out_Control;
- data_out_Write <= I_data_out_Write;
- I_data_out_Full <= data_out_Full;
-
- -- AD HOC EXTERNAL CONNECTIONS
- -- DESIGN ID : compaandesign.com:ipcore2RTL:design_ipcore:1
- TEST_STOP(0) <= signal_hwn_nd_1_STOP;
- TEST_ERROR(0) <= signal_hwn_nd_1_ERROR;
- TEST_BLOCK_RD(0) <= signal_hwn_nd_1_BLOCK_RD;
- TEST_STOP(1) <= signal_hwn_nd_2_STOP;
- TEST_ERROR(1) <= signal_hwn_nd_2_ERROR;
- TEST_BLOCK_RD(1) <= signal_hwn_nd_2_BLOCK_RD;
- TEST_STOP(2) <= signal_hwn_nd_3_STOP;
- TEST_ERROR(2) <= signal_hwn_nd_3_ERROR;
- TEST_BLOCK_RD(2) <= signal_hwn_nd_3_BLOCK_RD;
- TEST_FIFO_FULL(0) <= signal_ed_1_FIFO_FULL;
- TEST_FIFO_FULL(1) <= signal_ed_2_FIFO_FULL;
- TEST_FIFO_FULL(2) <= signal_ed_3_FIFO_FULL;
- TEST_FIFO_FULL(3) <= signal_ed_4_FIFO_FULL;
- signal_address <= address( 18 downto 0);
- read_data( 31 downto 0) <= signal_read_data;
- signal_write_data <= write_data( 31 downto 0);
- signal_read_en <= read_en;
- signal_write_en <= write_en;
-
--- Give default signals, default values
-
- net_gnd0 <= '0';
- net_gnd16(15 downto 0) <= B"0000000000000000";
-
--- Instanciate the wrappers (HWN and Edges)
-
-
- ipcore2RTL_hwn_nd_1_ip : ipcore2RTL_hwn_nd_1_ip_wrapper
- port map (
- data_in_Rd => I_data_in_Read,
- data_in_Din => I_data_in_Data(31 downto 0),
- data_in_Exist => I_data_in_Exists,
- data_in_CLK => open,
- data_in_CTRL => I_data_in_Control,
- ND_1OP_1_Wr => signal_ed_2_out_FSL_M_Write,
- ND_1OP_1_Dout(31 downto 0) => signal_ed_2_out_FSL_M_Data(0 to 31),
- ND_1OP_1_Full => signal_ed_2_out_FSL_M_Full,
- ND_1OP_1_CLK => open,
- ND_1OP_1_CTRL => signal_ed_2_out_FSL_M_Control,
- ND_1OP_1_d1_Wr => signal_ed_4_out_FSL_M_Write,
- ND_1OP_1_d1_Dout(31 downto 0) => signal_ed_4_out_FSL_M_Data(0 to 31),
- ND_1OP_1_d1_Full => signal_ed_4_out_FSL_M_Full,
- ND_1OP_1_d1_CLK => open,
- ND_1OP_1_d1_CTRL => signal_ed_4_out_FSL_M_Control,
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- STOP => signal_hwn_nd_1_STOP,
- ERROR => signal_hwn_nd_1_ERROR,
- BLOCK_RD => signal_hwn_nd_1_BLOCK_RD,
- RST => sys_rst_s,
- CLK => sys_clk_s
- );
-
- ipcore2RTL_hwn_nd_2_ip : ipcore2RTL_hwn_nd_2_ip_wrapper
- port map (
- ND_2IP_1_Rd => signal_ed_1_in_FSL_S_Read,
- ND_2IP_1_Din(31 downto 0) => signal_ed_1_in_FSL_S_Data(0 to 31),
- ND_2IP_1_Exist => signal_ed_1_in_FSL_S_Exists,
- ND_2IP_1_CLK => open,
- ND_2IP_1_CTRL => signal_ed_1_in_FSL_S_Control,
- ND_2IP_2_Rd => signal_ed_2_in_FSL_S_Read,
- ND_2IP_2_Din(31 downto 0) => signal_ed_2_in_FSL_S_Data(0 to 31),
- ND_2IP_2_Exist => signal_ed_2_in_FSL_S_Exists,
- ND_2IP_2_CLK => open,
- ND_2IP_2_CTRL => signal_ed_2_in_FSL_S_Control,
- ND_2OP_1_Wr => signal_ed_1_out_FSL_M_Write,
- ND_2OP_1_Dout(31 downto 0) => signal_ed_1_out_FSL_M_Data(0 to 31),
- ND_2OP_1_Full => signal_ed_1_out_FSL_M_Full,
- ND_2OP_1_CLK => open,
- ND_2OP_1_CTRL => signal_ed_1_out_FSL_M_Control,
- ND_2OP_1_d1_Wr => signal_ed_3_out_FSL_M_Write,
- ND_2OP_1_d1_Dout(31 downto 0) => signal_ed_3_out_FSL_M_Data(0 to 31),
- ND_2OP_1_d1_Full => signal_ed_3_out_FSL_M_Full,
- ND_2OP_1_d1_CLK => open,
- ND_2OP_1_d1_CTRL => signal_ed_3_out_FSL_M_Control,
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- STOP => signal_hwn_nd_2_STOP,
- ERROR => signal_hwn_nd_2_ERROR,
- BLOCK_RD => signal_hwn_nd_2_BLOCK_RD,
- RST => sys_rst_s,
- CLK => sys_clk_s
- );
-
- ipcore2RTL_hwn_nd_3_ip : ipcore2RTL_hwn_nd_3_ip_wrapper
- port map (
- ND_3IP_3_Rd => signal_ed_3_in_FSL_S_Read,
- ND_3IP_3_Din(31 downto 0) => signal_ed_3_in_FSL_S_Data(0 to 31),
- ND_3IP_3_Exist => signal_ed_3_in_FSL_S_Exists,
- ND_3IP_3_CLK => open,
- ND_3IP_3_CTRL => signal_ed_3_in_FSL_S_Control,
- ND_3IP_4_Rd => signal_ed_4_in_FSL_S_Read,
- ND_3IP_4_Din(31 downto 0) => signal_ed_4_in_FSL_S_Data(0 to 31),
- ND_3IP_4_Exist => signal_ed_4_in_FSL_S_Exists,
- ND_3IP_4_CLK => open,
- ND_3IP_4_CTRL => signal_ed_4_in_FSL_S_Control,
- data_out_Wr => I_data_out_Write,
- data_out_Dout => I_data_out_Data(31 downto 0),
- data_out_Full => I_data_out_Full,
- data_out_CLK => open,
- data_out_CTRL => I_data_out_Control,
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- STOP => signal_hwn_nd_3_STOP,
- ERROR => signal_hwn_nd_3_ERROR,
- BLOCK_RD => signal_hwn_nd_3_BLOCK_RD,
- RST => sys_rst_s,
- CLK => sys_clk_s
- );
-
- ipcore2RTL_control_if_ip : ipcore2RTL_control_if_ip_wrapper
- port map (
- PARAM_DT => signal_PARAM_DT,
- PARAM_LD => signal_PARAM_LD,
- PARAMETERS_IN => signal_PARAMETERS,
- PARAMETERS_IN_LD => signal_PARAMETERS_LD,
- RST => sys_rst_s,
- CLK => sys_clk_s
- );
-
- ipcore2RTL_register_rf_ip : ipcore2RTL_register_rf_ip_wrapper
- port map (
- address => signal_address,
- read_data => signal_read_data,
- read_en => signal_read_en,
- write_en => signal_write_en,
- write_data => signal_write_data,
- reg_rf_read_data => signal_reg_rf_read_data,
- reg_rf_read_en => signal_reg_rf_read_en,
- reg_rf_write_en => signal_reg_rf_write_en,
- reg_rf_write_data => signal_reg_rf_write_data,
- DP_RST => sys_rst_s,
- DP_CLK => sys_clk_s,
- MM_RST => mm_rst_s,
- MM_CLK => mm_clk_s
- );
-
- ipcore2RTL_ed_1 : ipcore2RTL_ed_1_ip_wrapper
- port map (
- FSL_Clk => sys_clk_s,
- SYS_Rst => sys_rst_s,
- FSL_Rst => open,
- FSL_M_Clk => net_gnd0,
- FSL_M_Data => signal_ed_1_out_FSL_M_Data,
- FSL_M_Control => signal_ed_1_out_FSL_M_Control,
- FSL_M_Write => signal_ed_1_out_FSL_M_Write,
- FSL_M_Full => signal_ed_1_out_FSL_M_Full,
- FSL_S_Data => signal_ed_1_in_FSL_S_Data,
- FSL_S_Control => signal_ed_1_in_FSL_S_Control,
- FSL_S_Read => signal_ed_1_in_FSL_S_Read,
- FSL_S_Exists => signal_ed_1_in_FSL_S_Exists,
- FSL_S_Clk => net_gnd0,
- FSL_FULL => signal_ed_1_FIFO_FULL,
- FSL_Has_Data => open,
- FSL_Control_IRQ => open
- );
-
- ipcore2RTL_ed_2 : ipcore2RTL_ed_2_ip_wrapper
- port map (
- FSL_Clk => sys_clk_s,
- SYS_Rst => sys_rst_s,
- FSL_Rst => open,
- FSL_M_Clk => net_gnd0,
- FSL_M_Data => signal_ed_2_out_FSL_M_Data,
- FSL_M_Control => signal_ed_2_out_FSL_M_Control,
- FSL_M_Write => signal_ed_2_out_FSL_M_Write,
- FSL_M_Full => signal_ed_2_out_FSL_M_Full,
- FSL_S_Data => signal_ed_2_in_FSL_S_Data,
- FSL_S_Control => signal_ed_2_in_FSL_S_Control,
- FSL_S_Read => signal_ed_2_in_FSL_S_Read,
- FSL_S_Exists => signal_ed_2_in_FSL_S_Exists,
- FSL_S_Clk => net_gnd0,
- FSL_FULL => signal_ed_2_FIFO_FULL,
- FSL_Has_Data => open,
- FSL_Control_IRQ => open
- );
-
- ipcore2RTL_ed_3 : ipcore2RTL_ed_3_ip_wrapper
- port map (
- FSL_Clk => sys_clk_s,
- SYS_Rst => sys_rst_s,
- FSL_Rst => open,
- FSL_M_Clk => net_gnd0,
- FSL_M_Data => signal_ed_3_out_FSL_M_Data,
- FSL_M_Control => signal_ed_3_out_FSL_M_Control,
- FSL_M_Write => signal_ed_3_out_FSL_M_Write,
- FSL_M_Full => signal_ed_3_out_FSL_M_Full,
- FSL_S_Data => signal_ed_3_in_FSL_S_Data,
- FSL_S_Control => signal_ed_3_in_FSL_S_Control,
- FSL_S_Read => signal_ed_3_in_FSL_S_Read,
- FSL_S_Exists => signal_ed_3_in_FSL_S_Exists,
- FSL_S_Clk => net_gnd0,
- FSL_FULL => signal_ed_3_FIFO_FULL,
- FSL_Has_Data => open,
- FSL_Control_IRQ => open
- );
-
- ipcore2RTL_ed_4 : ipcore2RTL_ed_4_ip_wrapper
- port map (
- FSL_Clk => sys_clk_s,
- SYS_Rst => sys_rst_s,
- FSL_Rst => open,
- FSL_M_Clk => net_gnd0,
- FSL_M_Data => signal_ed_4_out_FSL_M_Data,
- FSL_M_Control => signal_ed_4_out_FSL_M_Control,
- FSL_M_Write => signal_ed_4_out_FSL_M_Write,
- FSL_M_Full => signal_ed_4_out_FSL_M_Full,
- FSL_S_Data => signal_ed_4_in_FSL_S_Data,
- FSL_S_Control => signal_ed_4_in_FSL_S_Control,
- FSL_S_Read => signal_ed_4_in_FSL_S_Read,
- FSL_S_Exists => signal_ed_4_in_FSL_S_Exists,
- FSL_S_Clk => net_gnd0,
- FSL_FULL => signal_ed_4_FIFO_FULL,
- FSL_Has_Data => open,
- FSL_Control_IRQ => open
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_control_if_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_control_if_ip_wrapper.vhd
deleted file mode 100644
index 780c8eb9bea2a8fe017d14513aaa8848d3ed0680..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_control_if_ip_wrapper.vhd
+++ /dev/null
@@ -1,56 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_control_if_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library compaandesign_com_ipcore2RTL_control_if_1_lib;
-use compaandesign_com_ipcore2RTL_control_if_1_lib.all;
-
-entity ipcore2RTL_control_if_ip_wrapper is
- port (
- PARAM_DT : out std_logic_vector(31 downto 0);
- PARAM_LD : out std_logic;
- PARAMETERS_IN : in std_logic_vector(31 downto 0);
- PARAMETERS_IN_LD : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_control_if_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_control_if_ip_wrapper is
-
- component control_if is
- generic (
- RESET_HIGH : NATURAL := 1;
- QUANT : NATURAL := 32
- );
- port (
- PARAM_DT : out std_logic_vector(31 downto 0);
- PARAM_LD : out std_logic;
- PARAMETERS_IN : in std_logic_vector(31 downto 0);
- PARAMETERS_IN_LD : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_control_if_ip_wrapper_ip : control_if
- generic map (
- RESET_HIGH => 1,
- QUANT => 32
- )
- port map (
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- PARAMETERS_IN => PARAMETERS_IN,
- PARAMETERS_IN_LD => PARAMETERS_IN_LD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_1_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_1_ip_wrapper.vhd
deleted file mode 100644
index 6f338208cae56939c065d217b60555faaaedd424..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_1_ip_wrapper.vhd
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_1_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_1_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_1_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_1_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_1 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 16,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_1_ip_wrapper.vhd.bak b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_1_ip_wrapper.vhd.bak
deleted file mode 100644
index 07e1ca123c15eeedde0c6228826576e1d54f03ff..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_1_ip_wrapper.vhd.bak
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_1_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_1_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_1_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_1_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_1 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 5,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_2_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_2_ip_wrapper.vhd
deleted file mode 100644
index 232bb05b9e173a4da6a88bd7417c994646e23a94..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_2_ip_wrapper.vhd
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_2_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_2_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_2_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_2_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_2 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 16,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_2_ip_wrapper.vhd.bak b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_2_ip_wrapper.vhd.bak
deleted file mode 100644
index aeb6cdc6269af5e3485051222087f96e8379cf3a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_2_ip_wrapper.vhd.bak
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_2_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_2_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_2_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_2_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_2 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 216,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_3_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_3_ip_wrapper.vhd
deleted file mode 100644
index bccb997075f1606eba26929b1e7193bb9141bf18..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_3_ip_wrapper.vhd
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_3_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_3_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_3_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_3_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_3 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 16,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_3_ip_wrapper.vhd.bak b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_3_ip_wrapper.vhd.bak
deleted file mode 100644
index 8f2b7069595b4965bcdf8050720a705524a1ccd5..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_3_ip_wrapper.vhd.bak
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_3_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_3_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_3_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_3_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_3 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 2,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_4_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_4_ip_wrapper.vhd
deleted file mode 100644
index 0dd3e300bc3fc382805620975e0a30337af55041..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_4_ip_wrapper.vhd
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_4_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_4_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_4_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_4_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_4 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 16,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_4_ip_wrapper.vhd.bak b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_4_ip_wrapper.vhd.bak
deleted file mode 100644
index d49b4fb83b3f55a55b93d156494d71e2f50d5361..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_ed_4_ip_wrapper.vhd.bak
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_ed_4_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
-library compaandesign_com_common_altera_1_lib;
-use compaandesign_com_common_altera_1_lib.all;
-
-entity ipcore2RTL_ed_4_ip_wrapper is
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-
-
-end ipcore2RTL_ed_4_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_ed_4_ip_wrapper is
-
- component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer;
- C_ASYNC_CLKS : integer;
- C_IMPL_STYLE : integer;
- C_USE_CONTROL : integer;
- C_FSL_DWIDTH : integer;
- C_FSL_DEPTH : integer;
- C_READ_CLOCK_PERIOD : integer
- );
- port (
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to 31);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to 31);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
- end component;
-
-begin
-
- ipcore2RTL_ed_4 : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS => 0,
- C_IMPL_STYLE => 0,
- C_USE_CONTROL => 0,
- C_FSL_DWIDTH => 31+1,
- C_FSL_DEPTH => 2,
- C_READ_CLOCK_PERIOD => 0
- )
- port map (
- FSL_Clk => FSL_Clk,
- SYS_Rst => SYS_Rst,
- FSL_Rst => FSL_Rst,
- FSL_M_Clk => FSL_M_Clk,
- FSL_M_Data => FSL_M_Data,
- FSL_M_Control => FSL_M_Control,
- FSL_M_Write => FSL_M_Write,
- FSL_M_Full => FSL_M_Full,
- FSL_S_Clk => FSL_S_Clk,
- FSL_S_Data => FSL_S_Data,
- FSL_S_Control => FSL_S_Control,
- FSL_S_Read => FSL_S_Read,
- FSL_S_Exists => FSL_S_Exists,
- FSL_Full => FSL_Full,
- FSL_Has_Data => FSL_Has_Data,
- FSL_Control_IRQ => FSL_Control_IRQ
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
deleted file mode 100644
index fa289357835f62f47d82b55f37e0142147b92a5c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
+++ /dev/null
@@ -1,108 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_hwn_nd_1_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library compaandesign_com_ipcore2RTL_hwn_nd_1_1_lib;
-use compaandesign_com_ipcore2RTL_hwn_nd_1_1_lib.all;
-
-entity ipcore2RTL_hwn_nd_1_ip_wrapper is
- port (
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
- ND_1OP_1_d1_Wr : out std_logic;
- ND_1OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_d1_Full : in std_logic;
- ND_1OP_1_d1_CLK : out std_logic;
- ND_1OP_1_d1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_hwn_nd_1_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_hwn_nd_1_ip_wrapper is
-
- component ipcore2rtl_hwn_nd_1 is
- generic (
- RESET_HIGH : NATURAL := 1;
- PAR_WIDTH : NATURAL := 16;
- QUANT : NATURAL := 32;
- WRAP : BOOLEAN := true
- );
- port (
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
- ND_1OP_1_d1_Wr : out std_logic;
- ND_1OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_d1_Full : in std_logic;
- ND_1OP_1_d1_CLK : out std_logic;
- ND_1OP_1_d1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_hwn_nd_1_ip_wrapper_ip : ipcore2rtl_hwn_nd_1
- generic map (
- RESET_HIGH => 1,
- PAR_WIDTH => 32,
- QUANT => 32,
- WRAP => true
- )
- port map (
- data_in_Rd => data_in_Rd,
- data_in_Din => data_in_Din,
- data_in_Exist => data_in_Exist,
- data_in_CLK => data_in_CLK,
- data_in_CTRL => data_in_CTRL,
- ND_1OP_1_Wr => ND_1OP_1_Wr,
- ND_1OP_1_Dout => ND_1OP_1_Dout,
- ND_1OP_1_Full => ND_1OP_1_Full,
- ND_1OP_1_CLK => ND_1OP_1_CLK,
- ND_1OP_1_CTRL => ND_1OP_1_CTRL,
- ND_1OP_1_d1_Wr => ND_1OP_1_d1_Wr,
- ND_1OP_1_d1_Dout => ND_1OP_1_d1_Dout,
- ND_1OP_1_d1_Full => ND_1OP_1_d1_Full,
- ND_1OP_1_d1_CLK => ND_1OP_1_d1_CLK,
- ND_1OP_1_d1_CTRL => ND_1OP_1_d1_CTRL,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- STOP => STOP,
- ERROR => ERROR,
- BLOCK_RD => BLOCK_RD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
deleted file mode 100644
index 807f00d5289a0e4e1777f4763ca8ef2275eb3b08..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
+++ /dev/null
@@ -1,123 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_hwn_nd_2_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library compaandesign_com_ipcore2RTL_hwn_nd_2_1_lib;
-use compaandesign_com_ipcore2RTL_hwn_nd_2_1_lib.all;
-
-entity ipcore2RTL_hwn_nd_2_ip_wrapper is
- port (
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
- ND_2IP_2_Rd : out std_logic;
- ND_2IP_2_Din : in std_logic_vector(31 downto 0);
- ND_2IP_2_Exist : in std_logic;
- ND_2IP_2_CLK : out std_logic;
- ND_2IP_2_CTRL : in std_logic;
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
- ND_2OP_1_d1_Wr : out std_logic;
- ND_2OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_d1_Full : in std_logic;
- ND_2OP_1_d1_CLK : out std_logic;
- ND_2OP_1_d1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_hwn_nd_2_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_hwn_nd_2_ip_wrapper is
-
- component ipcore2rtl_hwn_nd_2 is
- generic (
- RESET_HIGH : NATURAL := 1;
- PAR_WIDTH : NATURAL := 16;
- QUANT : NATURAL := 32;
- WRAP : BOOLEAN := true
- );
- port (
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
- ND_2IP_2_Rd : out std_logic;
- ND_2IP_2_Din : in std_logic_vector(31 downto 0);
- ND_2IP_2_Exist : in std_logic;
- ND_2IP_2_CLK : out std_logic;
- ND_2IP_2_CTRL : in std_logic;
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
- ND_2OP_1_d1_Wr : out std_logic;
- ND_2OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_d1_Full : in std_logic;
- ND_2OP_1_d1_CLK : out std_logic;
- ND_2OP_1_d1_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_hwn_nd_2_ip_wrapper_ip : ipcore2rtl_hwn_nd_2
- generic map (
- RESET_HIGH => 1,
- PAR_WIDTH => 32,
- QUANT => 32,
- WRAP => true
- )
- port map (
- ND_2IP_1_Rd => ND_2IP_1_Rd,
- ND_2IP_1_Din => ND_2IP_1_Din,
- ND_2IP_1_Exist => ND_2IP_1_Exist,
- ND_2IP_1_CLK => ND_2IP_1_CLK,
- ND_2IP_1_CTRL => ND_2IP_1_CTRL,
- ND_2IP_2_Rd => ND_2IP_2_Rd,
- ND_2IP_2_Din => ND_2IP_2_Din,
- ND_2IP_2_Exist => ND_2IP_2_Exist,
- ND_2IP_2_CLK => ND_2IP_2_CLK,
- ND_2IP_2_CTRL => ND_2IP_2_CTRL,
- ND_2OP_1_Wr => ND_2OP_1_Wr,
- ND_2OP_1_Dout => ND_2OP_1_Dout,
- ND_2OP_1_Full => ND_2OP_1_Full,
- ND_2OP_1_CLK => ND_2OP_1_CLK,
- ND_2OP_1_CTRL => ND_2OP_1_CTRL,
- ND_2OP_1_d1_Wr => ND_2OP_1_d1_Wr,
- ND_2OP_1_d1_Dout => ND_2OP_1_d1_Dout,
- ND_2OP_1_d1_Full => ND_2OP_1_d1_Full,
- ND_2OP_1_d1_CLK => ND_2OP_1_d1_CLK,
- ND_2OP_1_d1_CTRL => ND_2OP_1_d1_CTRL,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- STOP => STOP,
- ERROR => ERROR,
- BLOCK_RD => BLOCK_RD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
deleted file mode 100644
index 56813a3eb36e089f2393ca42fb6754b1f34c4818..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
+++ /dev/null
@@ -1,108 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library compaandesign_com_ipcore2RTL_hwn_nd_3_1_lib;
-use compaandesign_com_ipcore2RTL_hwn_nd_3_1_lib.all;
-
-entity ipcore2RTL_hwn_nd_3_ip_wrapper is
- port (
- ND_3IP_3_Rd : out std_logic;
- ND_3IP_3_Din : in std_logic_vector(31 downto 0);
- ND_3IP_3_Exist : in std_logic;
- ND_3IP_3_CLK : out std_logic;
- ND_3IP_3_CTRL : in std_logic;
- ND_3IP_4_Rd : out std_logic;
- ND_3IP_4_Din : in std_logic_vector(31 downto 0);
- ND_3IP_4_Exist : in std_logic;
- ND_3IP_4_CLK : out std_logic;
- ND_3IP_4_CTRL : in std_logic;
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_hwn_nd_3_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_hwn_nd_3_ip_wrapper is
-
- component ipcore2rtl_hwn_nd_3 is
- generic (
- RESET_HIGH : NATURAL := 1;
- PAR_WIDTH : NATURAL := 16;
- QUANT : NATURAL := 32;
- WRAP : BOOLEAN := true
- );
- port (
- ND_3IP_3_Rd : out std_logic;
- ND_3IP_3_Din : in std_logic_vector(31 downto 0);
- ND_3IP_3_Exist : in std_logic;
- ND_3IP_3_CLK : out std_logic;
- ND_3IP_3_CTRL : in std_logic;
- ND_3IP_4_Rd : out std_logic;
- ND_3IP_4_Din : in std_logic_vector(31 downto 0);
- ND_3IP_4_Exist : in std_logic;
- ND_3IP_4_CLK : out std_logic;
- ND_3IP_4_CTRL : in std_logic;
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(31 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_hwn_nd_3_ip_wrapper_ip : ipcore2rtl_hwn_nd_3
- generic map (
- RESET_HIGH => 1,
- PAR_WIDTH => 32,
- QUANT => 32,
- WRAP => true
- )
- port map (
- ND_3IP_3_Rd => ND_3IP_3_Rd,
- ND_3IP_3_Din => ND_3IP_3_Din,
- ND_3IP_3_Exist => ND_3IP_3_Exist,
- ND_3IP_3_CLK => ND_3IP_3_CLK,
- ND_3IP_3_CTRL => ND_3IP_3_CTRL,
- ND_3IP_4_Rd => ND_3IP_4_Rd,
- ND_3IP_4_Din => ND_3IP_4_Din,
- ND_3IP_4_Exist => ND_3IP_4_Exist,
- ND_3IP_4_CLK => ND_3IP_4_CLK,
- ND_3IP_4_CTRL => ND_3IP_4_CTRL,
- data_out_Wr => data_out_Wr,
- data_out_Dout => data_out_Dout,
- data_out_Full => data_out_Full,
- data_out_CLK => data_out_CLK,
- data_out_CTRL => data_out_CTRL,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- STOP => STOP,
- ERROR => ERROR,
- BLOCK_RD => BLOCK_RD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd.bak b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd.bak
deleted file mode 100644
index 75eb839c5ff382ac8cb2e16fe556c53a420d466c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_hwn_nd_3_ip_wrapper.vhd.bak
+++ /dev/null
@@ -1,108 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_hwn_nd_3_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library compaandesign_com_ipcore2RTL_hwn_nd_3_1_lib;
-use compaandesign_com_ipcore2RTL_hwn_nd_3_1_lib.all;
-
-entity ipcore2RTL_hwn_nd_3_ip_wrapper is
- port (
- ND_3IP_3_Rd : out std_logic;
- ND_3IP_3_Din : in std_logic_vector(31 downto 0);
- ND_3IP_3_Exist : in std_logic;
- ND_3IP_3_CLK : out std_logic;
- ND_3IP_3_CTRL : in std_logic;
- ND_3IP_4_Rd : out std_logic;
- ND_3IP_4_Din : in std_logic_vector(31 downto 0);
- ND_3IP_4_Exist : in std_logic;
- ND_3IP_4_CLK : out std_logic;
- ND_3IP_4_CTRL : in std_logic;
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(0 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-
-
-end ipcore2RTL_hwn_nd_3_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_hwn_nd_3_ip_wrapper is
-
- component ipcore2rtl_hwn_nd_3 is
- generic (
- RESET_HIGH : NATURAL := 1;
- PAR_WIDTH : NATURAL := 16;
- QUANT : NATURAL := 32;
- WRAP : BOOLEAN := true
- );
- port (
- ND_3IP_3_Rd : out std_logic;
- ND_3IP_3_Din : in std_logic_vector(31 downto 0);
- ND_3IP_3_Exist : in std_logic;
- ND_3IP_3_CLK : out std_logic;
- ND_3IP_3_CTRL : in std_logic;
- ND_3IP_4_Rd : out std_logic;
- ND_3IP_4_Din : in std_logic_vector(31 downto 0);
- ND_3IP_4_Exist : in std_logic;
- ND_3IP_4_CLK : out std_logic;
- ND_3IP_4_CTRL : in std_logic;
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
- PARAM_DT : in std_logic_vector(0 downto 0);
- PARAM_LD : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic;
- RST : in std_logic;
- CLK : in std_logic
- );
-end component;
-
-begin
-
-ipcore2RTL_hwn_nd_3_ip_wrapper_ip : ipcore2rtl_hwn_nd_3
- generic map (
- RESET_HIGH => 1,
- PAR_WIDTH => 1,
- QUANT => 32,
- WRAP => false
- )
- port map (
- ND_3IP_3_Rd => ND_3IP_3_Rd,
- ND_3IP_3_Din => ND_3IP_3_Din,
- ND_3IP_3_Exist => ND_3IP_3_Exist,
- ND_3IP_3_CLK => ND_3IP_3_CLK,
- ND_3IP_3_CTRL => ND_3IP_3_CTRL,
- ND_3IP_4_Rd => ND_3IP_4_Rd,
- ND_3IP_4_Din => ND_3IP_4_Din,
- ND_3IP_4_Exist => ND_3IP_4_Exist,
- ND_3IP_4_CLK => ND_3IP_4_CLK,
- ND_3IP_4_CTRL => ND_3IP_4_CTRL,
- data_out_Wr => data_out_Wr,
- data_out_Dout => data_out_Dout,
- data_out_Full => data_out_Full,
- data_out_CLK => data_out_CLK,
- data_out_CTRL => data_out_CTRL,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- STOP => STOP,
- ERROR => ERROR,
- BLOCK_RD => BLOCK_RD,
- RST => RST,
- CLK => CLK
- );
-
-end architecture STRUCTURE;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_register_rf_ip_wrapper.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_register_rf_ip_wrapper.vhd
deleted file mode 100644
index 7ba297250c4ea81a54a3cd92cea844990707a1bc..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/ipcore2RTL_register_rf_ip_wrapper.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
--------------------------------------------------------------------------------
--- ipcore2RTL_register_rf_ip_wrapper.vhd
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library compaandesign_com_ipcore2RTL_register_rf_1_lib;
-use compaandesign_com_ipcore2RTL_register_rf_1_lib.all;
-
-entity ipcore2RTL_register_rf_ip_wrapper is
- port (
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0);
- DP_RST : in std_logic;
- DP_CLK : in std_logic;
- MM_RST : in std_logic;
- MM_CLK : in std_logic
- );
-
-end ipcore2RTL_register_rf_ip_wrapper;
-
-architecture STRUCTURE of ipcore2RTL_register_rf_ip_wrapper is
-
- component register_rf is
- port (
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- reg_rf_read_data : in std_logic_vector(32-1 downto 0);
- reg_rf_read_en : out std_logic;
- reg_rf_write_en : out std_logic;
- reg_rf_write_data : out std_logic_vector(32-1 downto 0);
- DP_RST : in std_logic;
- DP_CLK : in std_logic;
- MM_RST : in std_logic;
- MM_CLK : in std_logic
- );
- end component;
-
-begin
-
-ipcore2RTL_register_rf_ip_wrapper_ip : register_rf
- port map (
- address => address,
- read_data => read_data,
- read_en => read_en,
- write_en => write_en,
- write_data => write_data,
- reg_rf_read_data => reg_rf_read_data,
- reg_rf_read_en => reg_rf_read_en,
- reg_rf_write_en => reg_rf_write_en,
- reg_rf_write_data => reg_rf_write_data,
- DP_RST => DP_RST,
- DP_CLK => DP_CLK,
- MM_RST => MM_RST,
- MM_CLK => MM_CLK
- );
-
-end architecture STRUCTURE;
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/system_ext_TB.vhd b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/system_ext_TB.vhd
deleted file mode 100644
index 3bf5ff13881f9d5776e0684833532cf4ea2fbf5e..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/system_ext_TB.vhd
+++ /dev/null
@@ -1,406 +0,0 @@
--- System TestBench; automatically generated by KpnMapper
--- Use this file to test the system generated by XPS
--- The interface of the tested System includes only the FIFO interfaces
--- declared as external interfaces and not the FIFO interfaces connected
--- to platform FIFOs
--- To generate a System with complete interface select the *noboard* platform option
---
--- =====================================================================================
--- To use this testbench file you have to:
--- 1. Set propper Time-Out interval (constant TIMEOUT)
--- 2. If you read stimuli from files, provide a path to the directory that contains the stimuli files (constant STIM_DIR)
--- 3. For each input select whether stimuli is read from a file (default) or from a table (see processes *_STIM_DRV)
--- 4. For each output select whether stimuli is read from a file (default) or from a table (see processes *_STIM_CMP)
--- 5. For each stimuli that is read from a table fill the stimuli data in the table (constant *_STIM)
--- =====================================================================================
---
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library std;
-use std.textio.all;
-
-entity system_ext_TB is
-end system_ext_TB;
-
-architecture RTL of system_ext_TB is
-
- constant CLK_PERIOD : TIME := 10 ns; -- Period of the system clock
- constant RESET_LENGTH : natural := 5; -- Reset duration [clock cycles]
- constant STIM_DELAY : natural := RESET_LENGTH + 5; -- When stimuli supply starts [clock cycles]
- --
- -- Set Time-0ut interval sufficienly long for your application to complete
- constant TIMEOUT : natural := 64*(32+1024) + 100; -- Time-Out [clock cycles]
- --
- constant STIM_DIR : string := ""; -- Provide here the path to your stimuli files directory
- -- Input stimuli files: to provide data streams to input FIFOs
- constant STIM_FILE_data_in : string := "/home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp1.txt";
- constant STIM_FILE_data_out : string := "/home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp0.txt";
-
- signal ENDSIM : boolean := false; -- Simulation has finished
- signal ENDSTIM_IN : boolean := false; -- All input stimuli has been sent
- signal ENDSTIM_OUT : boolean := false; -- All expected data has been received
- signal ENDTIMEOUT : boolean := false; -- Simulation Time-Out has occured
- signal timeout_cntr : natural;
- signal ERROR_SYS : boolean := false; -- Error: Some of te system nodes indicated error
- signal ERROR_OUT : boolean := false; -- Error: Detected output data differs from the expected output data
- signal FIRST_ERROR : time; -- The time when the first error occured
- signal ENDSTOP : boolean := true; -- All system nodes have flagged 'Stop'
-
- --
- -- Component Under Test
- component ipcore is
- port (
- -- FIFO_In Interface: data_in
- data_in_Data : in std_logic_vector(31 downto 0);
- data_in_Control : in std_logic;
- data_in_Read : out std_logic;
- data_in_Exists : in std_logic;
-
- -- FIFO_Out Interface: data_out
- data_out_Data : out std_logic_vector(31 downto 0);
- data_out_Control : out std_logic;
- data_out_Write : out std_logic;
- data_out_Full : in std_logic;
-
- TEST_STOP : out std_logic_vector(2 downto 0);
- TEST_ERROR : out std_logic_vector(2 downto 0);
- TEST_FIFO_FULL : out std_logic_vector(3 downto 0);
- TEST_BLOCK_RD : out std_logic_vector(2 downto 0);
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- --
- KPN_CLK : in std_logic;
- KPN_RST : in std_logic
- );
- end component;
- --
- signal RST : STD_LOGIC := '0';
- signal CLK : STD_LOGIC := '0';
- --
- type FIFO_SRC_REC is record
- Data : integer;
- Control : std_logic;
- Read : std_logic;
- Exists : std_logic;
- --
- Count : natural;
- Done : boolean;
- end record;
- --
- type FIFO_SNK_REC is record
- Data : integer;
- Control : std_logic;
- Write : std_logic;
- Full : std_logic;
- --
- Count : natural;
- Done : boolean;
- Error : boolean;
- First_error : time;
- end record;
- --
- signal data_in : FIFO_SRC_REC;
- signal data_out : FIFO_SNK_REC;
- --
- signal data_in_Data : std_logic_vector(31 downto 0);
- signal data_out_Data : std_logic_vector(31 downto 0);
- signal TEST_STOP : std_logic_vector(2 downto 0);
- signal TEST_ERROR : std_logic_vector(2 downto 0);
- signal TEST_FIFO_FULL : std_logic_vector(3 downto 0);
- signal TEST_BLOCK_RD : std_logic_vector(2 downto 0);
- signal address : std_logic_vector(18 downto 0);
- signal read_data : std_logic_vector(31 downto 0);
- signal read_en : std_logic;
- signal write_en : std_logic;
- signal write_data : std_logic_vector(31 downto 0);
- --
- -- record keeping values of input and output stimuli
- type STIM_REC is record
- Data : integer;
- Control : std_logic;
- end record;
- --
- -- Function that reads a STIM_REC from a (stimuli) file
- impure function FREAD_STIM(file F : TEXT) return STIM_REC is
- variable VECTOR : STIM_REC;
- variable IN_LINE : LINE;
- begin
- readline(F ,IN_LINE);
- read(IN_LINE, VECTOR.Data);
- deallocate(IN_LINE);
- VECTOR.Control := '0'; -- Control bit is not used at the moment
- return VECTOR;
- end;
- --
- -- table of records
- type STIM_ARRAY is array(positive range <>) of STIM_REC;
- --
- -- Stimuli can be read either from a file or from the constant tables below
- -- If you will use constant tables, uncomment below those you need
--- constant data_in_STIM : STIM_ARRAY := (
--- -- Provide your stimuli here
--- -- ( Data, Control),
--- -- e.g. ( 0, '0'),
--- -- e.g. ( 0, '0')
--- );
- --
--- constant data_out_STIM : STIM_ARRAY := (
--- -- Provide your stimuli here
--- -- ( Data, Control),
--- -- e.g. ( 0, '0'),
--- -- e.g. ( 0, '0')
--- );
- --
-begin
- --
- -- =============================================
- -- = System Under Test
- -- =============================================
- SUT : ipcore port map(
- --
- data_in_Data => data_in_Data ,
- data_in_Control => data_in.Control ,
- data_in_Read => data_in.Read ,
- data_in_Exists => data_in.Exists ,
- --
- data_out_Data => data_out_Data ,
- data_out_Control => data_out.Control ,
- data_out_Write => data_out.Write ,
- data_out_Full => data_out.Full ,
- TEST_STOP => TEST_STOP ,
- TEST_ERROR => TEST_ERROR ,
- TEST_FIFO_FULL => TEST_FIFO_FULL ,
- TEST_BLOCK_RD => TEST_BLOCK_RD ,
- address => address ,
- read_data => read_data ,
- read_en => read_en ,
- write_en => write_en ,
- write_data => write_data ,
- --
- KPN_CLK => CLK,
- KPN_RST => RST
- );
- --
- data_in_Data <= STD_LOGIC_VECTOR(TO_SIGNED(data_in.Data, data_in_Data'Length));
- data_out.Data <= TO_INTEGER(SIGNED(data_out_Data));
-
- -- Adjust these values to changes values in the Register file to change parameters and shmem
-reg_file : process
- variable read_in : std_logic_vector(31 downto 0);
-begin
- address <= (others => '0');
- write_en <= '0';
- read_en <= '0';
- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
-
--- wait for 100ns;
--- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
--- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
--- wait for 1*CLK_PERIOD;
--- write_en <= '1';
--- wait for 2*CLK_PERIOD;
--- write_en <= '0';
--- wait for 1*CLK_PERIOD;
--- --read_en <= '1';
--- wait for 2*CLK_PERIOD;
--- --read_en <= '0';
--- wait for 1*CLK_PERIOD;
--- wait for 300ns;
- wait;
-end process;
-
- --
- -- Stimuli Driver for input stream : data_in
- data_in_STIM_DRV : process
- variable VECTOR : STIM_REC;
- file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_in;
- begin
- data_in.Exists <= '0';
- data_in.Count <= 0;
- data_in.Done <= false;
- wait for STIM_DELAY*CLK_PERIOD;
- wait until rising_edge(CLK);
-----------------------------------------------
--- -- Uncomment if stimuli for data_in is read from a constant tables
--- for i in data_in_STIM'range loop
--- VECTOR:= data_in_STIM(i);
-----------------------------------------------
- -- Uncomment if stimuli for data_in is read from a file
- while not( endfile(STIM_FILE)) loop
- VECTOR := FREAD_STIM(STIM_FILE);
---------------------------------------------
- data_in.Data <= VECTOR.Data;
- data_in.Control <= VECTOR.Control;
- data_in.Exists <= '1';
- L1: loop
- wait until rising_edge(CLK);
- exit L1 when (data_in.Read = '1');
- end loop L1;
- data_in.Count <= data_in.Count + 1;
- end loop;
- data_in.Exists <= '0';
- data_in.Done <= true;
- wait for 10*CLK_PERIOD;
- wait;
- end process;
- --
- ENDSTIM_IN <= data_in.Done;
- --
- -- Stimuli Comparator for output stream data_out
- data_out_STIM_CMP : process
- variable VECTOR : STIM_REC;
- file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_out;
- begin
- data_out.Full <= '1';
- data_out.Count <= 0;
- data_out.Done <= false;
- data_out.Error <= false;
- wait for STIM_DELAY*CLK_PERIOD;
- wait until rising_edge(CLK);
-----------------------------------------------
--- -- Uncomment if stimuli for data_out is read from a constant tables
--- for i in data_out_STIM'range loop
--- VECTOR := data_out_STIM(i);
-----------------------------------------------
- -- Uncomment if stimuli for data_out is read from a file
- while not( endfile(STIM_FILE)) loop
- VECTOR := FREAD_STIM(STIM_FILE);
-----------------------------------------------
- --
- data_out.Full <= '0';
- L1: loop
- wait until rising_edge(CLK);
- exit L1 when (data_out.Write = '1');
- end loop L1;
- data_out.Count <= data_out.Count + 1;
- if (data_out.Data /= VECTOR.Data) then
- report "TB_ERROR: Output 'data_out': the detected value " & integer'image(data_out.Data) & " differs from the expected value " & integer'image(VECTOR.Data) & "!!! (@time " & time'image(now) & ")."
- severity WARNING;
- if (not data_out.Error) then
- data_out.First_error <= now;
- end if;
- data_out.Error <= true;
- end if;
- end loop;
- data_out.Full <= '1';
- data_out.Done <= true;
- wait for 10*CLK_PERIOD;
- wait;
- end process;
- --
- ENDSTIM_OUT <= data_out.Done;
- ERROR_OUT <= data_out.Error;
- --
- -- Record the time when the first error occures
- FIRST_ERROR_TIME : process
- begin
- wait until (ERROR_OUT'event and ERROR_OUT=true) or (ERROR_SYS'event and ERROR_SYS=true);
- FIRST_ERROR <= now;
- wait;
- end process;
- --
---=============================================
---= All Nodes stopped ?
---=============================================
- process(test_stop)
- variable s : std_logic;
- variable e : std_logic;
- begin
- s := '1';
- e := '0';
- --
- for i in 0 to TEST_ERROR'Length-1 loop
- s := s and test_stop(i);
- e := e or test_error(i);
- end loop;
- --
- ENDSTOP <= (s = '1');
- ERROR_SYS <= (e = '1');
- --
- end process;
- -- Timeout counter
- TO_CTRL : process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (RST = '1') then
- timeout_cntr <= 0;
- else
- if (timeout_cntr = TIMEOUT) then
- ENDTIMEOUT <= true;
- else
- timeout_cntr <= timeout_cntr + 1;
- end if;
- end if;
- end if;
- end process;
- --
- -- Simulation control
- ENDSIM <= (ENDSTIM_IN and ENDSTOP and ENDSTIM_OUT) or ENDTIMEOUT;
- --
- PRINT_REPORT : process
- variable ERROR_CODE : natural;
- variable l : line;
- begin
- -- write(l, "***TB_REPOT: Simulation in progress...");
- writeline(output,l);
- wait until ENDSIM=true;
- -- write(l, "***TB_REPOT: Simulation END.");
- writeline(output,l);
- ERROR_CODE := 0;
- --
- if (ENDTIMEOUT) then
- ERROR_CODE := ERROR_CODE + 1;
- write(l, "***TB_REPOT: [TIMEOUT] Simulation terminated by a TIMEOUT after " & integer'image(timeout_cntr) & " clock cycles.");
- writeline(output,l);
- end if;
- --
- if (ERROR_OUT or ERROR_SYS) then
- ERROR_CODE := ERROR_CODE + 2;
- write(l, "***TB_REPOT: [ERROR] Simulation terminated with ERRORS!!! First error occured at time " & time'image(FIRST_ERROR) & ".");
- writeline(output,l);
- -- write(l, "***TB_REPOT: [ERROR] Flags ERROR = b");
- -- write(l, test_error, RIGHT, test_error'Length);
- -- writeline(output,l);
- end if;
- --
- write(l, "***TB_REPOT: [ERROR_CODE=" & integer'image(ERROR_CODE) & "]");
- writeline(output,l);
- --
- if (ERROR_CODE = 0) then
- write(l, "***TB_REPOT: [OK] Simulation completed successfully in " & integer'image(timeout_cntr) & " cycles !!!");
- writeline(output,l);
- -- write(l, "None of the processors flagged ERROR. ");
- writeline(output,l);
- end if;
- wait;
- end process;
- --
- -- CLK generator
- CLK_GEN: process
- begin
- if (ENDSIM=false) then
- CLK <= '0';
- wait for CLK_PERIOD/2;
- CLK <= '1';
- wait for CLK_PERIOD/2;
- else
- wait;
- end if;
- end process;
- --
- -- RESET generator
- RST_GEN: process
- begin
- RST <='1';
- wait for RESET_LENGTH*CLK_PERIOD;
- RST <='0';
- wait;
- end process;
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/system_ext_TB.vhd.bak b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/system_ext_TB.vhd.bak
deleted file mode 100644
index 4649bea62e513f998a08edbf63b900a4e6adef1f..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/system_ext_TB.vhd.bak
+++ /dev/null
@@ -1,406 +0,0 @@
--- System TestBench; automatically generated by KpnMapper
--- Use this file to test the system generated by XPS
--- The interface of the tested System includes only the FIFO interfaces
--- declared as external interfaces and not the FIFO interfaces connected
--- to platform FIFOs
--- To generate a System with complete interface select the *noboard* platform option
---
--- =====================================================================================
--- To use this testbench file you have to:
--- 1. Set propper Time-Out interval (constant TIMEOUT)
--- 2. If you read stimuli from files, provide a path to the directory that contains the stimuli files (constant STIM_DIR)
--- 3. For each input select whether stimuli is read from a file (default) or from a table (see processes *_STIM_DRV)
--- 4. For each output select whether stimuli is read from a file (default) or from a table (see processes *_STIM_CMP)
--- 5. For each stimuli that is read from a table fill the stimuli data in the table (constant *_STIM)
--- =====================================================================================
---
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library std;
-use std.textio.all;
-
-entity system_ext_TB is
-end system_ext_TB;
-
-architecture RTL of system_ext_TB is
-
- constant CLK_PERIOD : TIME := 10 ns; -- Period of the system clock
- constant RESET_LENGTH : natural := 5; -- Reset duration [clock cycles]
- constant STIM_DELAY : natural := RESET_LENGTH + 5; -- When stimuli supply starts [clock cycles]
- --
- -- Set Time-0ut interval sufficienly long for your application to complete
- constant TIMEOUT : natural := 64*(32+1024) + 100; -- Time-Out [clock cycles]
- --
- constant STIM_DIR : string := ""; -- Provide here the path to your stimuli files directory
- -- Input stimuli files: to provide data streams to input FIFOs
- constant STIM_FILE_data_in : string := " := "/home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp1.txt";
- constant STIM_FILE_data_out : string := " := "/home/shoshkov/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp0.txt";
-
- signal ENDSIM : boolean := false; -- Simulation has finished
- signal ENDSTIM_IN : boolean := false; -- All input stimuli has been sent
- signal ENDSTIM_OUT : boolean := false; -- All expected data has been received
- signal ENDTIMEOUT : boolean := false; -- Simulation Time-Out has occured
- signal timeout_cntr : natural;
- signal ERROR_SYS : boolean := false; -- Error: Some of te system nodes indicated error
- signal ERROR_OUT : boolean := false; -- Error: Detected output data differs from the expected output data
- signal FIRST_ERROR : time; -- The time when the first error occured
- signal ENDSTOP : boolean := true; -- All system nodes have flagged 'Stop'
-
- --
- -- Component Under Test
- component ipcore is
- port (
- -- FIFO_In Interface: data_in
- data_in_Data : in std_logic_vector(31 downto 0);
- data_in_Control : in std_logic;
- data_in_Read : out std_logic;
- data_in_Exists : in std_logic;
-
- -- FIFO_Out Interface: data_out
- data_out_Data : out std_logic_vector(31 downto 0);
- data_out_Control : out std_logic;
- data_out_Write : out std_logic;
- data_out_Full : in std_logic;
-
- TEST_STOP : out std_logic_vector(2 downto 0);
- TEST_ERROR : out std_logic_vector(2 downto 0);
- TEST_FIFO_FULL : out std_logic_vector(3 downto 0);
- TEST_BLOCK_RD : out std_logic_vector(2 downto 0);
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- --
- KPN_CLK : in std_logic;
- KPN_RST : in std_logic
- );
- end component;
- --
- signal RST : STD_LOGIC := '0';
- signal CLK : STD_LOGIC := '0';
- --
- type FIFO_SRC_REC is record
- Data : integer;
- Control : std_logic;
- Read : std_logic;
- Exists : std_logic;
- --
- Count : natural;
- Done : boolean;
- end record;
- --
- type FIFO_SNK_REC is record
- Data : integer;
- Control : std_logic;
- Write : std_logic;
- Full : std_logic;
- --
- Count : natural;
- Done : boolean;
- Error : boolean;
- First_error : time;
- end record;
- --
- signal data_in : FIFO_SRC_REC;
- signal data_out : FIFO_SNK_REC;
- --
- signal data_in_Data : std_logic_vector(31 downto 0);
- signal data_out_Data : std_logic_vector(31 downto 0);
- signal TEST_STOP : std_logic_vector(2 downto 0);
- signal TEST_ERROR : std_logic_vector(2 downto 0);
- signal TEST_FIFO_FULL : std_logic_vector(3 downto 0);
- signal TEST_BLOCK_RD : std_logic_vector(2 downto 0);
- signal address : std_logic_vector(18 downto 0);
- signal read_data : std_logic_vector(31 downto 0);
- signal read_en : std_logic;
- signal write_en : std_logic;
- signal write_data : std_logic_vector(31 downto 0);
- --
- -- record keeping values of input and output stimuli
- type STIM_REC is record
- Data : integer;
- Control : std_logic;
- end record;
- --
- -- Function that reads a STIM_REC from a (stimuli) file
- impure function FREAD_STIM(file F : TEXT) return STIM_REC is
- variable VECTOR : STIM_REC;
- variable IN_LINE : LINE;
- begin
- readline(F ,IN_LINE);
- read(IN_LINE, VECTOR.Data);
- deallocate(IN_LINE);
- VECTOR.Control := '0'; -- Control bit is not used at the moment
- return VECTOR;
- end;
- --
- -- table of records
- type STIM_ARRAY is array(positive range <>) of STIM_REC;
- --
- -- Stimuli can be read either from a file or from the constant tables below
- -- If you will use constant tables, uncomment below those you need
--- constant data_in_STIM : STIM_ARRAY := (
--- -- Provide your stimuli here
--- -- ( Data, Control),
--- -- e.g. ( 0, '0'),
--- -- e.g. ( 0, '0')
--- );
- --
--- constant data_out_STIM : STIM_ARRAY := (
--- -- Provide your stimuli here
--- -- ( Data, Control),
--- -- e.g. ( 0, '0'),
--- -- e.g. ( 0, '0')
--- );
- --
-begin
- --
- -- =============================================
- -- = System Under Test
- -- =============================================
- SUT : ipcore port map(
- --
- data_in_Data => data_in_Data ,
- data_in_Control => data_in.Control ,
- data_in_Read => data_in.Read ,
- data_in_Exists => data_in.Exists ,
- --
- data_out_Data => data_out_Data ,
- data_out_Control => data_out.Control ,
- data_out_Write => data_out.Write ,
- data_out_Full => data_out.Full ,
- TEST_STOP => TEST_STOP ,
- TEST_ERROR => TEST_ERROR ,
- TEST_FIFO_FULL => TEST_FIFO_FULL ,
- TEST_BLOCK_RD => TEST_BLOCK_RD ,
- address => address ,
- read_data => read_data ,
- read_en => read_en ,
- write_en => write_en ,
- write_data => write_data ,
- --
- KPN_CLK => CLK,
- KPN_RST => RST
- );
- --
- data_in_Data <= STD_LOGIC_VECTOR(TO_SIGNED(data_in.Data, data_in_Data'Length));
- data_out.Data <= TO_INTEGER(SIGNED(data_out_Data));
-
- -- Adjust these values to changes values in the Register file to change parameters and shmem
-reg_file : process
- variable read_in : std_logic_vector(31 downto 0);
-begin
- address <= (others => '0');
- write_en <= '0';
- read_en <= '0';
- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
-
--- wait for 100ns;
--- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
--- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
--- wait for 1*CLK_PERIOD;
--- write_en <= '1';
--- wait for 2*CLK_PERIOD;
--- write_en <= '0';
--- wait for 1*CLK_PERIOD;
--- --read_en <= '1';
--- wait for 2*CLK_PERIOD;
--- --read_en <= '0';
--- wait for 1*CLK_PERIOD;
--- wait for 300ns;
- wait;
-end process;
-
- --
- -- Stimuli Driver for input stream : data_in
- data_in_STIM_DRV : process
- variable VECTOR : STIM_REC;
- file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_in;
- begin
- data_in.Exists <= '0';
- data_in.Count <= 0;
- data_in.Done <= false;
- wait for STIM_DELAY*CLK_PERIOD;
- wait until rising_edge(CLK);
-----------------------------------------------
--- -- Uncomment if stimuli for data_in is read from a constant tables
--- for i in data_in_STIM'range loop
--- VECTOR:= data_in_STIM(i);
-----------------------------------------------
- -- Uncomment if stimuli for data_in is read from a file
- while not( endfile(STIM_FILE)) loop
- VECTOR := FREAD_STIM(STIM_FILE);
---------------------------------------------
- data_in.Data <= VECTOR.Data;
- data_in.Control <= VECTOR.Control;
- data_in.Exists <= '1';
- L1: loop
- wait until rising_edge(CLK);
- exit L1 when (data_in.Read = '1');
- end loop L1;
- data_in.Count <= data_in.Count + 1;
- end loop;
- data_in.Exists <= '0';
- data_in.Done <= true;
- wait for 10*CLK_PERIOD;
- wait;
- end process;
- --
- ENDSTIM_IN <= data_in.Done;
- --
- -- Stimuli Comparator for output stream data_out
- data_out_STIM_CMP : process
- variable VECTOR : STIM_REC;
- file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_out;
- begin
- data_out.Full <= '1';
- data_out.Count <= 0;
- data_out.Done <= false;
- data_out.Error <= false;
- wait for STIM_DELAY*CLK_PERIOD;
- wait until rising_edge(CLK);
-----------------------------------------------
--- -- Uncomment if stimuli for data_out is read from a constant tables
--- for i in data_out_STIM'range loop
--- VECTOR := data_out_STIM(i);
-----------------------------------------------
- -- Uncomment if stimuli for data_out is read from a file
- while not( endfile(STIM_FILE)) loop
- VECTOR := FREAD_STIM(STIM_FILE);
-----------------------------------------------
- --
- data_out.Full <= '0';
- L1: loop
- wait until rising_edge(CLK);
- exit L1 when (data_out.Write = '1');
- end loop L1;
- data_out.Count <= data_out.Count + 1;
- if (data_out.Data /= VECTOR.Data) then
- report "TB_ERROR: Output 'data_out': the detected value " & integer'image(data_out.Data) & " differs from the expected value " & integer'image(VECTOR.Data) & "!!! (@time " & time'image(now) & ")."
- severity WARNING;
- if (not data_out.Error) then
- data_out.First_error <= now;
- end if;
- data_out.Error <= true;
- end if;
- end loop;
- data_out.Full <= '1';
- data_out.Done <= true;
- wait for 10*CLK_PERIOD;
- wait;
- end process;
- --
- ENDSTIM_OUT <= data_out.Done;
- ERROR_OUT <= data_out.Error;
- --
- -- Record the time when the first error occures
- FIRST_ERROR_TIME : process
- begin
- wait until (ERROR_OUT'event and ERROR_OUT=true) or (ERROR_SYS'event and ERROR_SYS=true);
- FIRST_ERROR <= now;
- wait;
- end process;
- --
---=============================================
---= All Nodes stopped ?
---=============================================
- process(test_stop)
- variable s : std_logic;
- variable e : std_logic;
- begin
- s := '1';
- e := '0';
- --
- for i in 0 to TEST_ERROR'Length-1 loop
- s := s and test_stop(i);
- e := e or test_error(i);
- end loop;
- --
- ENDSTOP <= (s = '1');
- ERROR_SYS <= (e = '1');
- --
- end process;
- -- Timeout counter
- TO_CTRL : process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (RST = '1') then
- timeout_cntr <= 0;
- else
- if (timeout_cntr = TIMEOUT) then
- ENDTIMEOUT <= true;
- else
- timeout_cntr <= timeout_cntr + 1;
- end if;
- end if;
- end if;
- end process;
- --
- -- Simulation control
- ENDSIM <= (ENDSTIM_IN and ENDSTOP and ENDSTIM_OUT) or ENDTIMEOUT;
- --
- PRINT_REPORT : process
- variable ERROR_CODE : natural;
- variable l : line;
- begin
- -- write(l, "***TB_REPOT: Simulation in progress...");
- writeline(output,l);
- wait until ENDSIM=true;
- -- write(l, "***TB_REPOT: Simulation END.");
- writeline(output,l);
- ERROR_CODE := 0;
- --
- if (ENDTIMEOUT) then
- ERROR_CODE := ERROR_CODE + 1;
- write(l, "***TB_REPOT: [TIMEOUT] Simulation terminated by a TIMEOUT after " & integer'image(timeout_cntr) & " clock cycles.");
- writeline(output,l);
- end if;
- --
- if (ERROR_OUT or ERROR_SYS) then
- ERROR_CODE := ERROR_CODE + 2;
- write(l, "***TB_REPOT: [ERROR] Simulation terminated with ERRORS!!! First error occured at time " & time'image(FIRST_ERROR) & ".");
- writeline(output,l);
- -- write(l, "***TB_REPOT: [ERROR] Flags ERROR = b");
- -- write(l, test_error, RIGHT, test_error'Length);
- -- writeline(output,l);
- end if;
- --
- write(l, "***TB_REPOT: [ERROR_CODE=" & integer'image(ERROR_CODE) & "]");
- writeline(output,l);
- --
- if (ERROR_CODE = 0) then
- write(l, "***TB_REPOT: [OK] Simulation completed successfully in " & integer'image(timeout_cntr) & " cycles !!!");
- writeline(output,l);
- -- write(l, "None of the processors flagged ERROR. ");
- writeline(output,l);
- end if;
- wait;
- end process;
- --
- -- CLK generator
- CLK_GEN: process
- begin
- if (ENDSIM=false) then
- CLK <= '0';
- wait for CLK_PERIOD/2;
- CLK <= '1';
- wait for CLK_PERIOD/2;
- else
- wait;
- end if;
- end process;
- --
- -- RESET generator
- RST_GEN: process
- begin
- RST <='1';
- wait for RESET_LENGTH*CLK_PERIOD;
- RST <='0';
- wait;
- end process;
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/transcript b/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/transcript
deleted file mode 100644
index 9a6eba6de9d6e86e9e33c7dadb61ae7b38f55d6b..0000000000000000000000000000000000000000
Binary files a/applications/compaan/libraries/ipcore_trace/astron/src/vhdl/transcript and /dev/null differ
diff --git a/applications/compaan/libraries/ipcore_trace/astron/system_ext_TB.vhd b/applications/compaan/libraries/ipcore_trace/astron/system_ext_TB.vhd
deleted file mode 100644
index e6cf3bb2d17c631c69d3d4c855a91dc07543ab62..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/astron/system_ext_TB.vhd
+++ /dev/null
@@ -1,406 +0,0 @@
--- System TestBench; automatically generated by KpnMapper
--- Use this file to test the system generated by XPS
--- The interface of the tested System includes only the FIFO interfaces
--- declared as external interfaces and not the FIFO interfaces connected
--- to platform FIFOs
--- To generate a System with complete interface select the *noboard* platform option
---
--- =====================================================================================
--- To use this testbench file you have to:
--- 1. Set propper Time-Out interval (constant TIMEOUT)
--- 2. If you read stimuli from files, provide a path to the directory that contains the stimuli files (constant STIM_DIR)
--- 3. For each input select whether stimuli is read from a file (default) or from a table (see processes *_STIM_DRV)
--- 4. For each output select whether stimuli is read from a file (default) or from a table (see processes *_STIM_CMP)
--- 5. For each stimuli that is read from a table fill the stimuli data in the table (constant *_STIM)
--- =====================================================================================
---
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library std;
-use std.textio.all;
-
-entity system_ext_TB is
-end system_ext_TB;
-
-architecture RTL of system_ext_TB is
-
- constant CLK_PERIOD : TIME := 10 ns; -- Period of the system clock
- constant RESET_LENGTH : natural := 5; -- Reset duration [clock cycles]
- constant STIM_DELAY : natural := RESET_LENGTH + 5; -- When stimuli supply starts [clock cycles]
- --
- -- Set Time-0ut interval sufficienly long for your application to complete
- constant TIMEOUT : natural := 64*(32+1024) + 100; -- Time-Out [clock cycles]
- --
- constant STIM_DIR : string := ""; -- Provide here the path to your stimuli files directory
- -- Input stimuli files: to provide data streams to input FIFOs
- constant STIM_FILE_data_in : string := ".\ipxact\compaandesign.com\ipcore2RTL\hwn_nd_1\1\hdlsrc\STIM_hwn_nd_1_tmp1.txt";
- constant STIM_FILE_data_out : string := ".\ipxact\compaandesign.com\ipcore2RTL\hwn_nd_3\1\hdlsrc\STIM_hwn_nd_3_tmp0.txt";
-
- signal ENDSIM : boolean := false; -- Simulation has finished
- signal ENDSTIM_IN : boolean := false; -- All input stimuli has been sent
- signal ENDSTIM_OUT : boolean := false; -- All expected data has been received
- signal ENDTIMEOUT : boolean := false; -- Simulation Time-Out has occured
- signal timeout_cntr : natural;
- signal ERROR_SYS : boolean := false; -- Error: Some of te system nodes indicated error
- signal ERROR_OUT : boolean := false; -- Error: Detected output data differs from the expected output data
- signal FIRST_ERROR : time; -- The time when the first error occured
- signal ENDSTOP : boolean := true; -- All system nodes have flagged 'Stop'
-
- --
- -- Component Under Test
- component ipcore is
- port (
- -- FIFO_In Interface: data_in
- data_in_Data : in std_logic_vector(31 downto 0);
- data_in_Control : in std_logic;
- data_in_Read : out std_logic;
- data_in_Exists : in std_logic;
-
- -- FIFO_Out Interface: data_out
- data_out_Data : out std_logic_vector(31 downto 0);
- data_out_Control : out std_logic;
- data_out_Write : out std_logic;
- data_out_Full : in std_logic;
-
- TEST_STOP : out std_logic_vector(2 downto 0);
- TEST_ERROR : out std_logic_vector(2 downto 0);
- TEST_FIFO_FULL : out std_logic_vector(3 downto 0);
- TEST_BLOCK_RD : out std_logic_vector(2 downto 0);
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0);
- --
- KPN_CLK : in std_logic;
- KPN_RST : in std_logic
- );
- end component;
- --
- signal RST : STD_LOGIC := '0';
- signal CLK : STD_LOGIC := '0';
- --
- type FIFO_SRC_REC is record
- Data : integer;
- Control : std_logic;
- Read : std_logic;
- Exists : std_logic;
- --
- Count : natural;
- Done : boolean;
- end record;
- --
- type FIFO_SNK_REC is record
- Data : integer;
- Control : std_logic;
- Write : std_logic;
- Full : std_logic;
- --
- Count : natural;
- Done : boolean;
- Error : boolean;
- First_error : time;
- end record;
- --
- signal data_in : FIFO_SRC_REC;
- signal data_out : FIFO_SNK_REC;
- --
- signal data_in_Data : std_logic_vector(31 downto 0);
- signal data_out_Data : std_logic_vector(31 downto 0);
- signal TEST_STOP : std_logic_vector(2 downto 0);
- signal TEST_ERROR : std_logic_vector(2 downto 0);
- signal TEST_FIFO_FULL : std_logic_vector(3 downto 0);
- signal TEST_BLOCK_RD : std_logic_vector(2 downto 0);
- signal address : std_logic_vector(18 downto 0);
- signal read_data : std_logic_vector(31 downto 0);
- signal read_en : std_logic;
- signal write_en : std_logic;
- signal write_data : std_logic_vector(31 downto 0);
- --
- -- record keeping values of input and output stimuli
- type STIM_REC is record
- Data : integer;
- Control : std_logic;
- end record;
- --
- -- Function that reads a STIM_REC from a (stimuli) file
- impure function FREAD_STIM(file F : TEXT) return STIM_REC is
- variable VECTOR : STIM_REC;
- variable IN_LINE : LINE;
- begin
- readline(F ,IN_LINE);
- read(IN_LINE, VECTOR.Data);
- deallocate(IN_LINE);
- VECTOR.Control := '0'; -- Control bit is not used at the moment
- return VECTOR;
- end;
- --
- -- table of records
- type STIM_ARRAY is array(positive range <>) of STIM_REC;
- --
- -- Stimuli can be read either from a file or from the constant tables below
- -- If you will use constant tables, uncomment below those you need
--- constant data_in_STIM : STIM_ARRAY := (
--- -- Provide your stimuli here
--- -- ( Data, Control),
--- -- e.g. ( 0, '0'),
--- -- e.g. ( 0, '0')
--- );
- --
--- constant data_out_STIM : STIM_ARRAY := (
--- -- Provide your stimuli here
--- -- ( Data, Control),
--- -- e.g. ( 0, '0'),
--- -- e.g. ( 0, '0')
--- );
- --
-begin
- --
- -- =============================================
- -- = System Under Test
- -- =============================================
- SUT : ipcore port map(
- --
- data_in_Data => data_in_Data ,
- data_in_Control => data_in.Control ,
- data_in_Read => data_in.Read ,
- data_in_Exists => data_in.Exists ,
- --
- data_out_Data => data_out_Data ,
- data_out_Control => data_out.Control ,
- data_out_Write => data_out.Write ,
- data_out_Full => data_out.Full ,
- TEST_STOP => TEST_STOP ,
- TEST_ERROR => TEST_ERROR ,
- TEST_FIFO_FULL => TEST_FIFO_FULL ,
- TEST_BLOCK_RD => TEST_BLOCK_RD ,
- address => address ,
- read_data => read_data ,
- read_en => read_en ,
- write_en => write_en ,
- write_data => write_data ,
- --
- KPN_CLK => CLK,
- KPN_RST => RST
- );
- --
- data_in_Data <= STD_LOGIC_VECTOR(TO_SIGNED(data_in.Data, data_in_Data'Length));
- data_out.Data <= TO_INTEGER(SIGNED(data_out_Data));
-
- -- Adjust these values to changes values in the Register file to change parameters and shmem
-reg_file : process
- variable read_in : std_logic_vector(31 downto 0);
-begin
- address <= (others => '0');
- write_en <= '0';
- read_en <= '0';
- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
-
--- wait for 100ns;
--- address <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,19));
--- write_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(0,32));
--- wait for 1*CLK_PERIOD;
--- write_en <= '1';
--- wait for 2*CLK_PERIOD;
--- write_en <= '0';
--- wait for 1*CLK_PERIOD;
--- --read_en <= '1';
--- wait for 2*CLK_PERIOD;
--- --read_en <= '0';
--- wait for 1*CLK_PERIOD;
--- wait for 300ns;
- wait;
-end process;
-
- --
- -- Stimuli Driver for input stream : data_in
- data_in_STIM_DRV : process
- variable VECTOR : STIM_REC;
- file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_in;
- begin
- data_in.Exists <= '0';
- data_in.Count <= 0;
- data_in.Done <= false;
- wait for STIM_DELAY*CLK_PERIOD;
- wait until rising_edge(CLK);
-----------------------------------------------
--- -- Uncomment if stimuli for data_in is read from a constant tables
--- for i in data_in_STIM'range loop
--- VECTOR:= data_in_STIM(i);
-----------------------------------------------
- -- Uncomment if stimuli for data_in is read from a file
- while not( endfile(STIM_FILE)) loop
- VECTOR := FREAD_STIM(STIM_FILE);
---------------------------------------------
- data_in.Data <= VECTOR.Data;
- data_in.Control <= VECTOR.Control;
- data_in.Exists <= '1';
- L1: loop
- wait until rising_edge(CLK);
- exit L1 when (data_in.Read = '1');
- end loop L1;
- data_in.Count <= data_in.Count + 1;
- end loop;
- data_in.Exists <= '0';
- data_in.Done <= true;
- wait for 10*CLK_PERIOD;
- wait;
- end process;
- --
- ENDSTIM_IN <= data_in.Done;
- --
- -- Stimuli Comparator for output stream data_out
- data_out_STIM_CMP : process
- variable VECTOR : STIM_REC;
- file STIM_FILE : TEXT open READ_MODE is STIM_DIR&STIM_FILE_data_out;
- begin
- data_out.Full <= '1';
- data_out.Count <= 0;
- data_out.Done <= false;
- data_out.Error <= false;
- wait for STIM_DELAY*CLK_PERIOD;
- wait until rising_edge(CLK);
-----------------------------------------------
--- -- Uncomment if stimuli for data_out is read from a constant tables
--- for i in data_out_STIM'range loop
--- VECTOR := data_out_STIM(i);
-----------------------------------------------
- -- Uncomment if stimuli for data_out is read from a file
- while not( endfile(STIM_FILE)) loop
- VECTOR := FREAD_STIM(STIM_FILE);
-----------------------------------------------
- --
- data_out.Full <= '0';
- L1: loop
- wait until rising_edge(CLK);
- exit L1 when (data_out.Write = '1');
- end loop L1;
- data_out.Count <= data_out.Count + 1;
- if (data_out.Data /= VECTOR.Data) then
- report "TB_ERROR: Output 'data_out': the detected value " & integer'image(data_out.Data) & " differs from the expected value " & integer'image(VECTOR.Data) & "!!! (@time " & time'image(now) & ")."
- severity WARNING;
- if (not data_out.Error) then
- data_out.First_error <= now;
- end if;
- data_out.Error <= true;
- end if;
- end loop;
- data_out.Full <= '1';
- data_out.Done <= true;
- wait for 10*CLK_PERIOD;
- wait;
- end process;
- --
- ENDSTIM_OUT <= data_out.Done;
- ERROR_OUT <= data_out.Error;
- --
- -- Record the time when the first error occures
- FIRST_ERROR_TIME : process
- begin
- wait until (ERROR_OUT'event and ERROR_OUT=true) or (ERROR_SYS'event and ERROR_SYS=true);
- FIRST_ERROR <= now;
- wait;
- end process;
- --
---=============================================
---= All Nodes stopped ?
---=============================================
- process(test_stop)
- variable s : std_logic;
- variable e : std_logic;
- begin
- s := '1';
- e := '0';
- --
- for i in 0 to TEST_ERROR'Length-1 loop
- s := s and test_stop(i);
- e := e or test_error(i);
- end loop;
- --
- ENDSTOP <= (s = '1');
- ERROR_SYS <= (e = '1');
- --
- end process;
- -- Timeout counter
- TO_CTRL : process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (RST = '1') then
- timeout_cntr <= 0;
- else
- if (timeout_cntr = TIMEOUT) then
- ENDTIMEOUT <= true;
- else
- timeout_cntr <= timeout_cntr + 1;
- end if;
- end if;
- end if;
- end process;
- --
- -- Simulation control
- ENDSIM <= (ENDSTIM_IN and ENDSTOP and ENDSTIM_OUT) or ENDTIMEOUT;
- --
- PRINT_REPORT : process
- variable ERROR_CODE : natural;
- variable l : line;
- begin
- -- write(l, "***TB_REPOT: Simulation in progress...");
- writeline(output,l);
- wait until ENDSIM=true;
- -- write(l, "***TB_REPOT: Simulation END.");
- writeline(output,l);
- ERROR_CODE := 0;
- --
- if (ENDTIMEOUT) then
- ERROR_CODE := ERROR_CODE + 1;
- write(l, "***TB_REPOT: [TIMEOUT] Simulation terminated by a TIMEOUT after " & integer'image(timeout_cntr) & " clock cycles.");
- writeline(output,l);
- end if;
- --
- if (ERROR_OUT or ERROR_SYS) then
- ERROR_CODE := ERROR_CODE + 2;
- write(l, "***TB_REPOT: [ERROR] Simulation terminated with ERRORS!!! First error occured at time " & time'image(FIRST_ERROR) & ".");
- writeline(output,l);
- -- write(l, "***TB_REPOT: [ERROR] Flags ERROR = b");
- -- write(l, test_error, RIGHT, test_error'Length);
- -- writeline(output,l);
- end if;
- --
- write(l, "***TB_REPOT: [ERROR_CODE=" & integer'image(ERROR_CODE) & "]");
- writeline(output,l);
- --
- if (ERROR_CODE = 0) then
- write(l, "***TB_REPOT: [OK] Simulation completed successfully in " & integer'image(timeout_cntr) & " cycles !!!");
- writeline(output,l);
- -- write(l, "None of the processors flagged ERROR. ");
- writeline(output,l);
- end if;
- wait;
- end process;
- --
- -- CLK generator
- CLK_GEN: process
- begin
- if (ENDSIM=false) then
- CLK <= '0';
- wait for CLK_PERIOD/2;
- CLK <= '1';
- wait for CLK_PERIOD/2;
- else
- wait;
- end if;
- end process;
- --
- -- RESET generator
- RST_GEN: process
- begin
- RST <='1';
- wait for RESET_LENGTH*CLK_PERIOD;
- RST <='0';
- wait;
- end process;
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore.ast b/applications/compaan/libraries/ipcore_trace/ipcore.ast
deleted file mode 100644
index e24d76150391684a50b5a27eb4d4c952e687e197..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore.ast
+++ /dev/null
@@ -1,56 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<!DOCTYPE AST PUBLIC "-//Compaan Design//DTD AST 1//EN" "http://www.compaandesign.com/dtd/ast.dtd">
-
-<AST>
- <local name="a">
- <dimension size="10
- "/>
- </local>
- <local name="i"/>
- <local name="j"/>
- <local name="x"/>
- <statements>
- <loop type="for" iterator="i" lb="0" ub="9" stepsize="1">
- <assignmentstatement name="compaan_outlinedproc0" line="15" pos="0">
- <LHS>
- <variable name="a">
- <index value="i"/>
- </variable>
- </LHS>
- <RHS>
- <variable name="data_in" kind="memref">
- <index value="i"/>
- </variable>
- </RHS>
- </assignmentstatement>
- </loop>
- <loop type="for" iterator="j" lb="1" ub="9" stepsize="1">
- <assignmentstatement name="transformer" line="19" pos="0">
- <LHS>
- <variable name="a">
- <index value="j"/>
- </variable>
- </LHS>
- <RHS>
- <variable name="a">
- <index value="-1 + j"/>
- </variable>
- </RHS>
- </assignmentstatement>
- </loop>
- <loop type="for" iterator="x" lb="0" ub="9" stepsize="1">
- <assignmentstatement name="compaan_outlinedproc1" line="24" pos="0">
- <LHS>
- <variable name="data_out" kind="memref">
- <index value="x"/>
- </variable>
- </LHS>
- <RHS>
- <variable name="a">
- <index value="x"/>
- </variable>
- </RHS>
- </assignmentstatement>
- </loop>
- </statements>
-</AST>
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore.bld b/applications/compaan/libraries/ipcore_trace/ipcore.bld
deleted file mode 100644
index 666e3205a38265b52a9b11ae97720e81b1bf8cdd..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore.bld
+++ /dev/null
@@ -1,160 +0,0 @@
-<?xml version="1.0" standalone="no"?>
-<!DOCTYPE model PUBLIC "-//Compaan Design//DTD KPN 3//EN"
-"http://www.compaandesign.com/dtd/kpn.dtd">
-<model name="ipcore">
-
-
- <entity name="ND_1" type="source">
- <port name="ND_1OP_1" type="write"/>
- <port name="ND_1OP_1_d1" type="write"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <assignstatement name="compaan_outlinedproc0" >
- <var name="data_in[i]" type="memref_in">
- <varindex value="i"/>
- </var>
- <var name="out_0" type="dataflow_out" />
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <opdstatement arg="out_0" port="ND_1OP_1" >
- <property name="variable" value="a_1"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <opdstatement arg="out_0" port="ND_1OP_1_d1" >
- <property name="variable" value="a_1"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <property name="simpleAssign" value="true"/>
- <property name="linenumber" value="15"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <entity name="ND_2" type="transformer">
- <port name="ND_2IP_1" type="read"/>
- <port name="ND_2IP_2" type="read"/>
- <port name="ND_2OP_1" type="write"/>
- <port name="ND_2OP_1_d1" type="write"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <ipdstatement arg="in_0" port="ND_2IP_1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1;
- 1, -1, 9;
- 1, 1, -2]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <ipdstatement arg="in_0" port="ND_2IP_2" >
- <property name="variable" value="a_1"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1;
- 1, -1, 9;
- 1, -1, 1]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <assignstatement name="transformer" >
- <var name="in_0" type="dataflow_in" />
- <var name="out_0" type="dataflow_out" />
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <opdstatement arg="out_0" port="ND_2OP_1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, -1, 8;
- 1, 1, -1]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <opdstatement arg="out_0" port="ND_2OP_1_d1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, -1, 9;
- 1, 1, -1]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <property name="linenumber" value="19"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <entity name="ND_3" type="sink">
- <port name="ND_3IP_3" type="read"/>
- <port name="ND_3IP_4" type="read"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <ipdstatement arg="in_0" port="ND_3IP_3" >
- <property name="variable" value="a_2"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9;
- 1, 1, -1]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <ipdstatement arg="in_0" port="ND_3IP_4" >
- <property name="variable" value="a_1"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9;
- 1, -1, 0]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <assignstatement name="compaan_outlinedproc1" >
- <var name="in_0" type="dataflow_in" />
- <var name="data_out[x]" type="memref_out">
- <varindex value="x"/>
- </var>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <property name="simpleAssign" value="true"/>
- <property name="linenumber" value="24"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <link name="ED_1" from="ND_2OP_1" to="ND_2IP_1" type="iomm">
- <mapping index="j" control="" parameter="" matrix="[ 1, -1]" />
- <property name="name" value="a_2(j-1)"/>
- </link>
- <link name="ED_2" from="ND_1OP_1" to="ND_2IP_2" type="iomm">
- <mapping index="j" control="" parameter="" matrix="[ 1, -1]" />
- <property name="name" value="a_1(j-1)"/>
- </link>
- <link name="ED_3" from="ND_2OP_1_d1" to="ND_3IP_3" type="iomm">
- <mapping index="x" control="" parameter="" matrix="[ 1, 0]" />
- <property name="name" value="a_2(x)"/>
- </link>
- <link name="ED_4" from="ND_1OP_1_d1" to="ND_3IP_4" type="iomm">
- <mapping index="x" control="" parameter="" matrix="[ 1, 0]" />
- <property name="name" value="a_1(x)"/>
- </link>
-</model>
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore.c b/applications/compaan/libraries/ipcore_trace/ipcore.c
deleted file mode 100644
index 334f9b499dd60224790f66746eef6899676ff386..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore.c
+++ /dev/null
@@ -1,48 +0,0 @@
-#define WIDTH 10
-
-void transformer(int a, int *b) {
-}
-
-#pragma compaan_procedure ipcore
-void filter(int data_in[WIDTH], int data_out[WIDTH]) {
-
- int a[WIDTH];
- int c[WIDTH];
- int i, j, x;
-
- // Stream data into the design
- for (i = 0; i < WIDTH; i = i + 1) {
- a[i] = data_in[i];
- }
-
- for (j = 1; j < WIDTH; j = j + 1) {
- transformer(a[j-1], &a[j]);
- }
-
- // Stream data out
- for (x = 0; x < WIDTH; x = x + 1) {
- data_out[x] = a[x];
- }
-}
-
-/* This example show how to create a IP core of the filter describe below.
- * The IP will get an input FIFO and output FIFO interface.
- *
- * DRIVER Code
- * */
-void main(void) {
- int i = 0, j = 0;
-
- int data_out[WIDTH];
- int data_in[WIDTH];
-
- for (j = 0; j < WIDTH; j++) {
- produce_data(&(data_in[j]));
- }
-
- filter(data_in, data_out);
-
- for (j = 0; j < WIDTH; j++) {
- consume_data(data_out[j]);
- }
-}
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore.kpn b/applications/compaan/libraries/ipcore_trace/ipcore.kpn
deleted file mode 100644
index 8f385ffe78d06303616338ad243e1a9d2c1c33d3..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore.kpn
+++ /dev/null
@@ -1,168 +0,0 @@
-<?xml version="1.0" standalone="no"?>
-<!DOCTYPE model PUBLIC "-//Compaan Design//DTD KPN 3//EN"
-"http://www.compaandesign.com/dtd/kpn.dtd">
-<model name="ipcore">
-
-
- <entity name="ND_1" type="source">
- <port name="ND_1OP_1" type="write"/>
- <port name="ND_1OP_1_d1" type="write"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <assignstatement name="compaan_outlinedproc0" >
- <var name="data_in[i]" type="memref_in">
- <varindex value="i"/>
- </var>
- <var name="out_0" type="dataflow_out" />
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <opdstatement arg="out_0" port="ND_1OP_1" >
- <property name="variable" value="a_1"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <opdstatement arg="out_0" port="ND_1OP_1_d1" >
- <property name="variable" value="a_1"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <property name="simpleAssign" value="true"/>
- <property name="linenumber" value="15"/>
- <property name="nonreadswitching" value="true"/>
- <property name="firing" value="{[1, 1]=10}"/>
- <property name="parameters" value="false"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <entity name="ND_2" type="transformer">
- <port name="ND_2IP_1" type="read"/>
- <port name="ND_2IP_2" type="read"/>
- <port name="ND_2OP_1" type="write"/>
- <port name="ND_2OP_1_d1" type="write"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <ipdstatement arg="in_0" port="ND_2IP_1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -2]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <ipdstatement arg="in_0" port="ND_2IP_2" >
- <property name="variable" value="a_1"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 0, 1, -1]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <assignstatement name="transformer" >
- <var name="in_0" type="dataflow_in" />
- <var name="out_0" type="dataflow_out" />
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <opdstatement arg="out_0" port="ND_2OP_1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, -1, 8]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <opdstatement arg="out_0" port="ND_2OP_1_d1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <property name="linenumber" value="19"/>
- <property name="firing" value="{[1, 1]=9}"/>
- <property name="parameters" value="false"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <entity name="ND_3" type="sink">
- <port name="ND_3IP_3" type="read"/>
- <port name="ND_3IP_4" type="read"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <ipdstatement arg="in_0" port="ND_3IP_3" >
- <property name="variable" value="a_2"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <ipdstatement arg="in_0" port="ND_3IP_4" >
- <property name="variable" value="a_1"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <assignstatement name="compaan_outlinedproc1" >
- <var name="in_0" type="dataflow_in" />
- <var name="data_out[x]" type="memref_out">
- <varindex value="x"/>
- </var>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <property name="simpleAssign" value="true"/>
- <property name="linenumber" value="24"/>
- <property name="firing" value="{[1, 1]=10}"/>
- <property name="nonwriteswitching" value="true"/>
- <property name="parameters" value="false"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <link name="ED_1" from="ND_2OP_1" to="ND_2IP_1" type="iomm">
- <mapping index="j" control="" parameter="" matrix="[ 1, -1]" />
- <property name="selfloop" value="true"/>
- <property name="name" value="a_2(j-1)"/>
- <property name="sizeIsExact" value="true"/>
- <property name="throughput" value="{[1, 1]=8}"/>
- <property name="size" value="{[1, 1]=5}"/>
- </link>
- <link name="ED_2" from="ND_1OP_1" to="ND_2IP_2" type="iomm">
- <mapping index="j" control="" parameter="" matrix="[ 1, -1]" />
- <property name="name" value="a_1(j-1)"/>
- <property name="sizeIsExact" value="false"/>
- <property name="throughput" value="{[1, 1]=1}"/>
- <property name="size" value="{[1, 1]=1}"/>
- </link>
- <link name="ED_3" from="ND_2OP_1_d1" to="ND_3IP_3" type="iomm">
- <mapping index="x" control="" parameter="" matrix="[ 1, 0]" />
- <property name="name" value="a_2(x)"/>
- <property name="sizeIsExact" value="true"/>
- <property name="throughput" value="{[1, 1]=9}"/>
- <property name="size" value="{[1, 1]=1}"/>
- </link>
- <link name="ED_4" from="ND_1OP_1_d1" to="ND_3IP_4" type="iomm">
- <mapping index="x" control="" parameter="" matrix="[ 1, 0]" />
- <property name="name" value="a_1(x)"/>
- <property name="sizeIsExact" value="true"/>
- <property name="throughput" value="{[1, 1]=1}"/>
- <property name="size" value="{[1, 1]=1}"/>
- </link>
-</model>
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore.rdg b/applications/compaan/libraries/ipcore_trace/ipcore.rdg
deleted file mode 100644
index 034eb1cc4b5cdd38881008b6a58721052bfd63e9..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore.rdg
+++ /dev/null
@@ -1,134 +0,0 @@
-<?xml version="1.0" standalone="no"?>
-<!DOCTYPE model PUBLIC "-//Compaan Design//DTD RDG 1//EN"
- "http://www.compaandesign.com/dtd/rdg.dtd">
-
-<model name="ipcore">
-
- <node name="ND_1" type="Node">
- <function name="compaan_outlinedproc0">
- <argument name="data_in" type="memref_in">
- <index value="i"/>
- </argument>
- <argument name="out_0" type="dataflow_out"/>
- </function>
- <domain index="i" control="" parameter="">
- <constraint matrix="[1, 1, 0; 1, -1, 9]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- <port name="OP_1" argument="out_0" variable="a_1" ref="a_1(i)">
- <domain index="i" control="" parameter="">
- <constraint matrix="[0, 0, 0]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- </port>
- <property name="linenumber" value="15"/>
- <property name="columnnumber" value="0"/>
- </node>
-
- <node name="ND_2" type="Node">
- <function name="transformer">
- <argument name="in_0" type="dataflow_in"/>
- <argument name="out_0" type="dataflow_out"/>
- </function>
- <domain index="j" control="" parameter="">
- <constraint matrix="[1, 1, -1; 1, -1, 9]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- <port name="IP_1" argument="in_0" variable="a_2" ref="a_2(j-1)">
- <domain index="j" control="" parameter="">
- <constraint matrix="[1, 1, -1; 1, -1, 9; 1, 1, -2]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- </port>
- <port name="IP_2" argument="in_0" variable="a_1" ref="a_1(j-1)">
- <domain index="j" control="" parameter="">
- <constraint matrix="[1, 1, -1; 1, -1, 9; 1, -1, 1]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- </port>
- <port name="OP_1" argument="out_0" variable="a_2" ref="a_2(j)">
- <domain index="j" control="" parameter="">
- <constraint matrix="[0, 0, 0]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- </port>
- <property name="linenumber" value="19"/>
- <property name="columnnumber" value="0"/>
-</node>
-
-<node name="ND_3" type="Node">
- <function name="compaan_outlinedproc1">
- <argument name="in_0" type="dataflow_in"/>
- <argument name="data_out" type="memref_out">
- <index value="x"/>
- </argument>
-</function>
-<domain index="x" control="" parameter="">
- <constraint matrix="[1, 1, 0; 1, -1, 9]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
-</domain>
-<port name="IP_3" argument="in_0" variable="a_2" ref="a_2(x)">
- <domain index="x" control="" parameter="">
- <constraint matrix="[1, 1, 0; 1, -1, 9; 1, 1, -1]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
-</port>
-<port name="IP_4" argument="in_0" variable="a_1" ref="a_1(x)">
- <domain index="x" control="" parameter="">
- <constraint matrix="[1, 1, 0; 1, -1, 9; 1, -1, 0]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
-</port>
-<property name="linenumber" value="24"/>
-<property name="columnnumber" value="0"/>
-</node>
-<edge name="ED_1">
- <to name="ND_2" port="IP_1" />
- <from name="ND_2" port="OP_1" />
- <domain index="j" control="" parameter="">
- <constraint matrix="[1, 1, -1; 1, -1, 9; 1, 1, -2]" />
- <context matrix="[]" />
- <mapping matrix="[1, -1]" />
- </domain>
- <doc>a_2(j-1)</doc>
-</edge>
-<edge name="ED_2">
- <to name="ND_2" port="IP_2" />
- <from name="ND_1" port="OP_1" />
- <domain index="j" control="" parameter="">
- <constraint matrix="[1, 1, -1; 1, -1, 9; 1, -1, 1]" />
- <context matrix="[]" />
- <mapping matrix="[1, -1]" />
- </domain>
- <doc>a_1(j-1)</doc>
-</edge>
-<edge name="ED_3">
- <to name="ND_3" port="IP_3" />
- <from name="ND_2" port="OP_1" />
- <domain index="x" control="" parameter="">
- <constraint matrix="[1, 1, 0; 1, -1, 9; 1, 1, -1]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- <doc>a_2(x)</doc>
-</edge>
-<edge name="ED_4">
- <to name="ND_3" port="IP_4" />
- <from name="ND_1" port="OP_1" />
- <domain index="x" control="" parameter="">
- <constraint matrix="[1, 1, 0; 1, -1, 9; 1, -1, 0]" />
- <context matrix="[]" />
- <mapping matrix="[1, 0]" />
- </domain>
- <doc>a_1(x)</doc>
-</edge>
-</model>
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore.sac b/applications/compaan/libraries/ipcore_trace/ipcore.sac
deleted file mode 100644
index a08b2a11c7509fb8f12ade1a473122752fdd6c83..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore.sac
+++ /dev/null
@@ -1,94 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<!DOCTYPE AST PUBLIC "-//Compaan Design//DTD AST 1//EN"
-"http://www.compaandesign.com/dtd/ast.dtd">
-
-<AST>
-<statements>
- <loop type="for" iterator="i" lb="0" ub="9" stepsize="1">
- <assignmentstatement name="compaan_outlinedproc0" line="15" pos="0">
- <LHS>
- <variable name="out_0"/>
- </LHS>
- <RHS>
- <variable name="data_in" kind="memref">
- <index value="i"/>
- </variable>
- </RHS>
- </assignmentstatement>
- <opd>
- <variable name="a_1">
- <index value="i"/>
- </variable>
- <variable name="out_0"/>
- </opd>
- </loop>
- <loop type="for" iterator="j" lb="1" ub="9" stepsize="1">
- <ifstatement condition="j-2 >= 0">
- <then>
- <ipd>
- <variable name="in_0"/>
- <variable name="a_2">
- <index value="j-1"/>
- </variable>
- </ipd>
- </then>
- </ifstatement>
- <ifstatement condition="-j+1 >= 0">
- <then>
- <ipd>
- <variable name="in_0"/>
- <variable name="a_1">
- <index value="j-1"/>
- </variable>
- </ipd>
- </then>
- </ifstatement>
- <assignmentstatement name="transformer" line="19" pos="0">
- <LHS>
- <variable name="out_0"/>
- </LHS>
- <RHS>
- <variable name="in_0"/>
- </RHS>
- </assignmentstatement>
- <opd>
- <variable name="a_2">
- <index value="j"/>
- </variable>
- <variable name="out_0"/>
- </opd>
- </loop>
- <loop type="for" iterator="x" lb="0" ub="9" stepsize="1">
- <ifstatement condition="x-1 >= 0">
- <then>
- <ipd>
- <variable name="in_0"/>
- <variable name="a_2">
- <index value="x"/>
- </variable>
- </ipd>
- </then>
- </ifstatement>
- <ifstatement condition="-x >= 0">
- <then>
- <ipd>
- <variable name="in_0"/>
- <variable name="a_1">
- <index value="x"/>
- </variable>
- </ipd>
- </then>
- </ifstatement>
- <assignmentstatement name="compaan_outlinedproc1" line="24" pos="0">
- <LHS>
- <variable name="data_out" kind="memref">
- <index value="x"/>
- </variable>
- </LHS>
- <RHS>
- <variable name="in_0"/>
- </RHS>
- </assignmentstatement>
- </loop>
-</statements>
-</AST>
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore.trn b/applications/compaan/libraries/ipcore_trace/ipcore.trn
deleted file mode 100644
index cbc2070d68d1183200a62b2e8153dbdbcf82cd64..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore.trn
+++ /dev/null
@@ -1,168 +0,0 @@
-<?xml version="1.0" standalone="no"?>
-<!DOCTYPE model PUBLIC "-//Compaan Design//DTD KPN 3//EN"
-"http://www.compaandesign.com/dtd/kpn.dtd">
-<model name="ipcore">
-
-
- <entity name="ND_1" type="source">
- <port name="ND_1OP_1" type="write"/>
- <port name="ND_1OP_1_d1" type="write"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <assignstatement name="compaan_outlinedproc0" >
- <var name="data_in[i]" type="memref_in">
- <varindex value="i"/>
- </var>
- <var name="out_0" type="dataflow_out" />
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <opdstatement arg="out_0" port="ND_1OP_1" >
- <property name="variable" value="a_1"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <opdstatement arg="out_0" port="ND_1OP_1_d1" >
- <property name="variable" value="a_1"/>
- <domain index="i" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <property name="nonreadswitching" value="true"/>
- <property name="linenumber" value="15"/>
- <property name="simpleAssign" value="true"/>
- <property name="firing" value="{[1, 1]=10}"/>
- <property name="parameters" value="false"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <entity name="ND_2" type="transformer">
- <port name="ND_2IP_1" type="read"/>
- <port name="ND_2IP_2" type="read"/>
- <port name="ND_2OP_1" type="write"/>
- <port name="ND_2OP_1_d1" type="write"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <ipdstatement arg="in_0" port="ND_2IP_1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 1, -2]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <ipdstatement arg="in_0" port="ND_2IP_2" >
- <property name="variable" value="a_1"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 0, 1, -1]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <assignstatement name="transformer" >
- <var name="in_0" type="dataflow_in" />
- <var name="out_0" type="dataflow_out" />
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <opdstatement arg="out_0" port="ND_2OP_1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, -1, 8]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <opdstatement arg="out_0" port="ND_2OP_1_d1" >
- <property name="variable" value="a_2"/>
- <domain index="j" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </opdstatement>
- <property name="linenumber" value="19"/>
- <property name="firing" value="{[1, 1]=9}"/>
- <property name="parameters" value="false"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <entity name="ND_3" type="sink">
- <port name="ND_3IP_3" type="read"/>
- <port name="ND_3IP_4" type="read"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, 0;
- 1, -1, 9]" />
- <context matrix="[]" />
- </domain>
- <ipdstatement arg="in_0" port="ND_3IP_3" >
- <property name="variable" value="a_2"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 1, -1]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <ipdstatement arg="in_0" port="ND_3IP_4" >
- <property name="variable" value="a_1"/>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 0, 1, 0]" />
- <context matrix="[]" />
- </domain>
- </ipdstatement>
- <assignstatement name="compaan_outlinedproc1" >
- <var name="in_0" type="dataflow_in" />
- <var name="data_out[x]" type="memref_out">
- <varindex value="x"/>
- </var>
- <domain index="x" control="" parameter="" >
- <constraint matrix="[ 1, 0, 1]" />
- <context matrix="[]" />
- </domain>
- </assignstatement>
- <property name="linenumber" value="24"/>
- <property name="simpleAssign" value="true"/>
- <property name="firing" value="{[1, 1]=10}"/>
- <property name="nonwriteswitching" value="true"/>
- <property name="parameters" value="false"/>
- <property name="columnnumber" value="0"/>
- </entity>
-
- <link name="ED_1" from="ND_2OP_1" to="ND_2IP_1" type="iomm">
- <mapping index="j" control="" parameter="" matrix="[ 1, -1]" />
- <property name="selfloop" value="true"/>
- <property name="name" value="a_2(j-1)"/>
- <property name="sizeIsExact" value="true"/>
- <property name="throughput" value="{[1, 1]=8}"/>
- <property name="size" value="{[1, 1]=1}"/>
- </link>
- <link name="ED_2" from="ND_1OP_1" to="ND_2IP_2" type="iomm">
- <mapping index="j" control="" parameter="" matrix="[ 1, -1]" />
- <property name="name" value="a_1(j-1)"/>
- <property name="sizeIsExact" value="false"/>
- <property name="throughput" value="{[1, 1]=1}"/>
- <property name="size" value="{[1, 1]=10}"/>
- </link>
- <link name="ED_3" from="ND_2OP_1_d1" to="ND_3IP_3" type="iomm">
- <mapping index="x" control="" parameter="" matrix="[ 1, 0]" />
- <property name="name" value="a_2(x)"/>
- <property name="sizeIsExact" value="false"/>
- <property name="throughput" value="{[1, 1]=9}"/>
- <property name="size" value="{[1, 1]=9}"/>
- </link>
- <link name="ED_4" from="ND_1OP_1_d1" to="ND_3IP_4" type="iomm">
- <mapping index="x" control="" parameter="" matrix="[ 1, 0]" />
- <property name="name" value="a_1(x)"/>
- <property name="sizeIsExact" value="false"/>
- <property name="throughput" value="{[1, 1]=1}"/>
- <property name="size" value="{[1, 1]=10}"/>
- </link>
-</model>
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore_main.c b/applications/compaan/libraries/ipcore_trace/ipcore_main.c
deleted file mode 100644
index 752193c1711383237ebf9d68f1ade14b25697d0a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore_main.c
+++ /dev/null
@@ -1,51 +0,0 @@
-#define WIDTH 10
-
-void transformer(int a, int *b) {
-}
-
-#pragma compaan_procedure ipcore
-/* Compaan procedure filter has been removed */
-extern void filter(int data_in[WIDTH], int data_out[WIDTH]) ;
-
-
-/* This example show how to create a IP core of the filter describe below.
- * The IP will get an input FIFO and output FIFO interface.
- *
- * DRIVER Code
- * */
-void main(void) {
- int i = 0, j = 0;
-
- int data_out[WIDTH];
- int data_in[WIDTH];
-
- for (j = 0; j < WIDTH; j++) {
- produce_data(&(data_in[j]));
- }
-
- filter(data_in, data_out);
-
- for (j = 0; j < WIDTH; j++) {
- consume_data(data_out[j]);
- }
-}
-
-
-/* END OF ORIGINAL INPUT */
-
-/* Definition of procedures */
-
-#line 15 "./ipcore.c"
-void compaan_outlinedproc0(int * tmp0, int tmp1)
-{
- (*tmp0) = (tmp1);
-}
-
-
-#line 24 "./ipcore.c"
-void compaan_outlinedproc1(int * tmp0, int tmp1)
-{
- (*tmp0) = (tmp1);
-}
-
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipcore_outline.xml b/applications/compaan/libraries/ipcore_trace/ipcore_outline.xml
deleted file mode 100644
index c374fc85b5f9b6853b466cbde2359de8d6e6934e..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipcore_outline.xml
+++ /dev/null
@@ -1,42 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<!DOCTYPE outline PUBLIC "-//Compaan Design//DTD OUTLINE 3//EN" "http://www.compaandesign.com/dtd/outline.dtd">
-<outline>
- <networkfunction name="filter">
- <memory name="data_in" type="0">
- <index />
- </memory>
- <memory name="data_out" type="0">
- <index />
- </memory>
- </networkfunction>
- <function name="transformer">
- <arguments>
- <data name="a" direction="in" type="0" />
- <data name="b" direction="out" type="0" />
- </arguments>
- <results>
- </results>
- </function>
- <function name="compaan_outlinedproc0">
- <arguments>
- <data name="tmp0" direction="out" type="0" />
- <memref name="tmp1" direction="in" type="0" />
- </arguments>
- <results>
- </results>
- <property name="simpleAssign" value="true"/>
- </function>
- <function name="compaan_outlinedproc1">
- <arguments>
- <memref name="tmp0" direction="out" type="0" />
- <data name="tmp1" direction="in" type="0" />
- </arguments>
- <results>
- </results>
- <property name="simpleAssign" value="true"/>
- </function>
- <type id="0">
- <integer size="32" alignment="32" signed="true" arithsize="32" />
- </type>
-</outline>
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/build.xml b/applications/compaan/libraries/ipcore_trace/ipxact/build.xml
deleted file mode 100644
index 4f69a77bfad4c4ae65f7595ccf07a6ab1c0e620f..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/build.xml
+++ /dev/null
@@ -1,51 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<project name="simulation" default="all" basedir=".">
-
-
- <target name="all">
- <antcall target="autoesl" />
- <antcall target="xps" />
- </target>
-
- <target name="xps">
- <exec executable="xps">
- <arg value="-nw" />
- <arg value="-scr" />
- <arg value="simulate.tcl" />
- <arg value="system.xmp" />
- </exec>
- </target>
-
- <target name="download">
- <exec executable="xps">
- <arg value="-nw" />
- <arg value="-scr" />
- <arg value="download.tcl" />
- <arg value="system.xmp" />
- </exec>
- </target>
-
- <target name="netlist">
- <exec executable="xps">
- <arg value="-nw" />
- <arg value="-scr" />
- <arg value="netlist.tcl" />
- <arg value="system.xmp" />
- </exec>
- </target>
-
- <target name="sim_build">
- <exec executable="sh" dir="simulation/behavioral">
- <arg value="system_fuse.sh" />
- </exec>
- </target>
-
- <target name="sim_run">
- <exec executable="cmd" >
- <arg value="/C" />
- <arg value="simulate_win32.bat" />
- </exec>
- </target>
- <target name="autoesl">
- </target>
-</project>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/altera/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/altera/1/component.xml
deleted file mode 100644
index 72a2b9f0f8f3bd6ef62ddedae0f03faf8432ad75..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/altera/1/component.xml
+++ /dev/null
@@ -1,141 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!-- // Copyright 2009 Compaan Design bv, The Netherlands // All rights,
- including copyrights, reserved. // www.compaandesign.com // // THIS WORK
- FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION. // USE OF THESE MATERIALS
- ARE GOVERNED BY // THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
- // SPECIFICATION DISCLAIMER AVAILABLE FROM // www.spiritconsortium.org //
- // This source file is provided on an AS IS basis. The SPIRIT Consortium
- disclaims // ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF //
- MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. // The user
- of the source file shall indemnify and hold The SPIRIT Consortium harmless
- // from any damages or liability arising out of the use thereof or the performance
- or // implementation or partial implementation of the schema. -->
-<spirit:component
- xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd"
- xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4"
- xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>common</spirit:library>
- <spirit:name>altera</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>FSL_S</spirit:name>
- <spirit:busType spirit:library="busdef.push"
- spirit:name="push" spirit:vendor="compaandesign.com" spirit:version="1.0" />
- <spirit:abstractionType spirit:library="busdef.push"
- spirit:name="push_rtl" spirit:vendor="compaandesign.com"
- spirit:version="1.0" />
- <spirit:slave />
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>fifo_in</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>push</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>FSL_M</spirit:name>
- <spirit:busType spirit:library="busdef.pop"
- spirit:name="pop" spirit:vendor="compaandesign.com" spirit:version="1.0" />
- <spirit:abstractionType spirit:library="busdef.pop"
- spirit:name="pop_rtl" spirit:vendor="compaandesign.com"
- spirit:version="1.0" />
- <spirit:master />
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>fifo_out</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>pop</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:xilinx.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>fifo</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>FSL_M</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>FSL_S</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_EXT_RESET_HIGH</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_ASYNC_CLKS</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_IMPL_STYLE</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_CONTROL</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_FSL_DWIDTH</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_FSL_DEPTH</spirit:name>
- <spirit:value>16</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_READ_CLOCK_PERIOD</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
-
- <spirit:file>
- <spirit:name>hdlsrc/fsl_v20.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
-
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/altera/1/hdlsrc/fsl_v20.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/altera/1/hdlsrc/fsl_v20.vhd
deleted file mode 100644
index 096f7ef40195318da53d7267cc9750a4129784d5..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/altera/1/hdlsrc/fsl_v20.vhd
+++ /dev/null
@@ -1,187 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- fsl_v20.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: fsl_v20.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2003-02-13 First Version
--- satish 2004-03-03 New Version
--- rolandp 2006-08-20 BRAM in asynch mode
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library ieee,common_lib,dp_lib;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-use ieee.math_real.all;
-
-entity fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end entity fsl_v20;
-
-architecture IMP of fsl_v20 is
-
- signal sl_full : std_logic;
- signal FSL_S_Empty : std_logic;
- signal snk_out : t_dp_siso;
- signal snk_in : t_dp_sosi;
- signal src_in : t_dp_siso;
- signal src_out : t_dp_sosi;
-
-begin
-
- FSL_M_Full <= not snk_out.ready;
- --FSL_S_Exists <= not FSL_S_Empty and src_out.valid;
- FSL_S_Exists <= src_out.valid;
- snk_in.data(C_FSL_DWIDTH-1 downto 0) <= FSL_M_Data;
- FSL_S_Data <= src_out.data(C_FSL_DWIDTH-1 downto 0);
- snk_in.valid <= FSL_M_Write;
- src_in.ready <= FSL_S_Read;
-
- u_dp_fifo_core : ENTITY dp_lib.dp_fifo_sc
- GENERIC MAP (
- g_data_w => C_FSL_DWIDTH, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
- g_bsn_w => 1,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_bsn => FALSE,
- g_use_empty => FALSE,
- g_use_channel => FALSE,
- g_use_error => FALSE,
- g_use_sync => FALSE,
- g_use_ctrl => FALSE, -- sop & eop
- g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => C_FSL_DEPTH, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- g_fifo_af_margin => 1, -- >=4, Nof words below max (full) at which fifo is considered almost full
- g_fifo_rl => 0
- )
- PORT MAP (
- rst => SYS_Rst,
- clk => FSL_Clk,
- -- Monitor FIFO filling
- wr_ful => sl_full,
- usedw => open,
- rd_emp => FSL_S_Empty,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
-
-end architecture IMP;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/common/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/common/1/component.xml
deleted file mode 100644
index 1b23c9705cc720295352f27faf83ae8533089661..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/common/1/component.xml
+++ /dev/null
@@ -1,45 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>common</spirit:library>
- <spirit:name>common</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:xilinx.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>common</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/hw_node_pkg.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/common/1/hdlsrc/hw_node_pkg.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/common/1/hdlsrc/hw_node_pkg.vhd
deleted file mode 100644
index 6a61da397792225e436fc6271b5df1b279e95292..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/common/1/hdlsrc/hw_node_pkg.vhd
+++ /dev/null
@@ -1,126 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
---
--- This file, or parts of it, or modified versions of it, may not be
--- copied, reproduced or transmitted in any form, including
--- reprinting, translation, photocopying or microfilming, or by any
--- means, electronic, mechanical or otherwise, or stored in a
--- retrieval system, or used for any purpose, without the prior
--- written permission of all Owners unless it is explicitly marked as
--- having Classification `Public'.
---
--- Classification: Restricted.
---
--- Owners of this file give notice:
--- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
--- All rights, including copyrights, reserved.
---
--- This file contains or may contain restricted information and is
--- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
--- Notice(s) above do not evidence any actual or intended publication
--- of such source code. This file is additionally subject to the
--- conditions listed in the RESTRICTIONS file and is with NOWARRANTY.
---
--- END OF COPYRIGHT NOTICE
---
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
---USE IEEE.numeric_std.all;
-
---library nodepack;
-package hw_node_pkg is
- type t_counter_step is array (0 to 10) of natural range 1 to 32;
- type t_counter_width is array (0 to 10) of natural range 1 to 32; -- each number represents the bit-width of a counter
- --
- --type t_par_values is array (0 to 10) of integer; -- each number represents the default value of a parameter
- type t_par is record
- val_min : integer;
- val_max : integer;
- val_def : integer;
- bitwidth : natural;
- end record;
-
- type t_par_vector is array (natural range<>) of t_par;
-
-
- Function b2std(b : boolean) return std_logic;
- function int2slv(int_value : integer; size: integer) return std_logic_vector;
- function slv2int(vect : std_logic_vector; size : integer) return integer;
- --Function modulo2(a:integer; b:integer) return integer;
- Function maxf(left: integer; right: integer) return integer;
- Function minf(left: integer; right: integer) return integer;
-
-end hw_node_pkg;
-
-package body hw_node_pkg is
-
- Function b2std(b : boolean) return std_logic is
- begin
- if b then
- return '1';
- else
- return '0';
- end if;
- end b2std;
-
------------------------------------------------------------------------------------
-
- Function int2slv(int_value : integer; size : integer) return std_logic_vector is
- variable result : std_logic_vector(size-1 downto 0);
- begin
- for i in 0 to size-1 loop
- if ((int_value/(2**i)) rem 2) = 0 then
- result(i) := '0';
- else
- result(i) := '1';
- end if;
- end loop;
- return result;
- end int2slv;
-
------------------------------------------------------------------------------------
-
- function slv2int(vect : std_logic_vector; size : integer) return integer is
-
- variable result : integer range (2**size)-1 downto 0;
- begin
- result := 0;
- for i in 0 to size-1 loop
-
- if( vect(i) = '1' ) then
- result := result + 2**i;
- end if;
-
- end loop;
- return result;
- end slv2int;
-
------------------------------------------------------------------------------------
-
- --Function modulo2(a:integer; b:integer) return integer is
- --variable eval :std_logic_vector(7 downto 0);
- --begin
- -- eval := (int2slv(a, 8) and int2slv(1, 8)) xor int2slv(b,8);
- -- return slv2int(eval,8);
- --end modulo2;
-
------------------------------------------------------------------------------------
-
- Function maxf(left: integer; right:integer) return integer is
- begin
- if left > right then return left;
- else return right;
- end if;
- end maxf;
-
------------------------------------------------------------------------------------
-
- Function minf(left: integer; right:integer) return integer is
- begin
- if left < right then return left;
- else return right;
- end if;
- end minf;
-
-end hw_node_pkg;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/const_connector/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/const_connector/1/component.xml
deleted file mode 100644
index 99b94e108250e7b9c0e8631d8b6efd27733edcc3..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/const_connector/1/component.xml
+++ /dev/null
@@ -1,70 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>common</spirit:library>
- <spirit:name>const_connector</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:xilinx.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>fifo</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>FSL_M</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_FSL_CONST</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_FSL_DWIDTH</spirit:name>
- <spirit:value>31</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/const_connector.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/const_connector/1/hdlsrc/const_connector.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/const_connector/1/hdlsrc/const_connector.vhd
deleted file mode 100644
index 0bcbf3ecc6ace7d13aa14222cb5af91d9ccace99..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/const_connector/1/hdlsrc/const_connector.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
-
-------------------------------------------------------------------------------
--- Filename: fsl_const
--- Version: 1.00.a
--- Description: Example FSL core (VHDL).
--- Date: Mon May 24 13:16:55 2010 (by Create and Import Peripheral Wizard)
--- VHDL Standard: VHDL'93
-------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port: "*_i"
--- device pins: "*_pin"
--- ports: "- Names begin with Uppercase"
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>"
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-------------------------------------------------------------------------------
--- Entity Section
-------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------
--- Entity Section
-------------------------------------------------------------------------------
-
-entity common_const_connector is
- generic (
- C_FSL_CONST : integer := 0;
- C_FSL_DWIDTH : integer := 31
- );
- port
- (
- FSL_M_CLK : out std_logic;
- FSL_M_Wr : out std_logic;
- FSL_M_Dout : out std_logic_vector(C_FSL_DWIDTH downto 0);
- FSL_M_CTRL : out std_logic;
- FSL_M_Full : in std_logic;
- RST : in std_logic;
- CLK : in std_logic
-
- );
-end common_const_connector;
-
-------------------------------------------------------------------------------
--- Architecture Section
-------------------------------------------------------------------------------
-
-architecture RTL of common_const_connector is
-begin
- FSL_M_CLK <= '0';
- FSL_M_Dout <= STD_LOGIC_VECTOR(TO_SIGNED(C_FSL_CONST,C_FSL_DWIDTH+1));
- FSL_M_CTRL <= '0';
- FSL_M_Wr <= '1';
-end architecture RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/extern_connector/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/extern_connector/1/component.xml
deleted file mode 100644
index bf0a14f938cf9b3bb173120796177b59f034d549..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/extern_connector/1/component.xml
+++ /dev/null
@@ -1,83 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>common</spirit:library>
- <spirit:name>extern_connector</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:xilinx.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>extern_connector</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>FSL_S</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>FSL_M</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>RESET_HIGH</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>C_FSL_DWIDTH</spirit:name>
- <spirit:value>31</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/extern_connector.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/extern_connector/1/hdlsrc/extern_connector.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/extern_connector/1/hdlsrc/extern_connector.vhd
deleted file mode 100644
index fe6367988ad45e5dcdffd3ff72c8146cae2a009c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/extern_connector/1/hdlsrc/extern_connector.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
---
--- This file, or parts of it, or modified versions of it, may not be
--- copied, reproduced or transmitted in any form, including
--- reprinting, translation, photocopying or microfilming, or by any
--- means, electronic, mechanical or otherwise, or stored in a
--- retrieval system, or used for any purpose, without the prior
--- written permission of all Owners unless it is explicitly marked as
--- having Classification `Public'.
---
--- Classification: Restricted.
---
--- Owners of this file give notice:
--- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
--- All rights, including copyrights, reserved.
---
--- This file contains or may contain restricted information and is
--- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
--- Notice(s) above do not evidence any actual or intended publication
--- of such source code. This file is additionally subject to the
--- conditions listed in the RESTRICTIONS file and is with NOWARRANTY.
---
--- END OF COPYRIGHT NOTICE
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity extern_connector is
- generic (
- RESET_HIGH : natural := 1;
- C_FSL_DWIDTH : natural := 31
- );
- port (
- CLK : in std_logic;
- RST : in std_logic;
- --
- -- ============================================
- -- = External Connector interface (INPUT)
- -- ============================================
- -- SRC (FSL_S Interface)
- FSL_S_Din : in STD_LOGIC_VECTOR(C_FSL_DWIDTH downto 0);
- FSL_S_CTRL : in STD_LOGIC;
- FSL_S_Rd : out STD_LOGIC;
- FSL_S_Exist : in STD_LOGIC;
- FSL_S_CLK : out std_logic;
- --
- -- SINK (FSL_M Interface)
- FSL_M_Dout : out STD_LOGIC_VECTOR(C_FSL_DWIDTH downto 0);
- FSL_M_CTRL : out STD_LOGIC;
- FSL_M_Wr : out STD_LOGIC;
- FSL_M_Full : in STD_LOGIC;
- FSL_M_CLK : out std_logic
- );
-end extern_connector;
-
-architecture STRUCTURE of extern_connector is
-
- signal ready : std_logic;
-
-begin
- ready <= FSL_S_Exist and not FSL_M_Full;
- FSL_S_Rd <= ready;
- FSL_M_Wr <= ready;
- FSL_M_CTRL <= FSL_S_CTRL;
- FSL_M_Dout <= FSL_S_Din;
-end architecture STRUCTURE;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/component.xml
deleted file mode 100644
index 0ff79028c6af8ccddc6816c72bd4529f5702429e..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/component.xml
+++ /dev/null
@@ -1,161 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>common</spirit:library>
- <spirit:name>fifo</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>FSL_S</spirit:name>
- <spirit:busType spirit:library="busdef.push" spirit:name="push" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:abstractionType spirit:library="busdef.push" spirit:name="push_rtl" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>fifo_in</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>push</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>FSL_M</spirit:name>
- <spirit:busType spirit:library="busdef.pop" spirit:name="pop" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:abstractionType spirit:library="busdef.pop" spirit:name="pop_rtl" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>fifo_out</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>pop</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:xilinx.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>fifo</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>FSL_M</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>FSL_S</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_EXT_RESET_HIGH</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_ASYNC_CLKS</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_IMPL_STYLE</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_CONTROL</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_FSL_DWIDTH</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_FSL_DEPTH</spirit:name>
- <spirit:value>16</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_READ_CLOCK_PERIOD</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/async_fifo_bram.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/async_fifo.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/fsl_v20.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/gen_srlfifo.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/gen_sync_bram.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/gen_sync_dpram.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/sync_fifo.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/async_fifo.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/async_fifo.vhd
deleted file mode 100644
index 5a06a0806d756e8b7d41435b93c880dc9fa96b07..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/async_fifo.vhd
+++ /dev/null
@@ -1,573 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: async_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- Async_FIFO.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: Async_FIFO.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- Async_FIFO.vhd
---
--------------------------------------------------------------------------------
--- Author: goran
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- goran 2003-10-27 First Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.Std_Logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Async_FIFO is
- generic (
- WordSize : Integer := 8;
- MemSize : Integer := 16;
- Protect : Boolean := False
- );
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic
- );
-end Async_FIFO;
-
-architecture VHDL_RTL of ASync_FIFO is
-
- -----------------------------------------------------------------------------
- -- A function which tries to calculate the best Mem_Size and by that the best
- -- counting scheme
- -----------------------------------------------------------------------------
- function Calculate_Right_Mem_Size (Mem_Size : in Natural) return Integer is
- begin -- Calculate_Right_Mem_Size
- case Mem_Size is
- when 0 to 3 =>
- assert false report "To small FIFO" severity failure;
- return 0;
- when 4 to 16 => return 16;
- when 17 to 32 => return 32;
- when 33 to 64 => return 64;
- when 65 to 128 =>
- -- Do not yet need to check if to use the up/down counting scheme since
- -- there is not true 7-bit counter implemented yet
- return ((MemSize+15)/16)*16;
- when others =>
- assert false
- report "Unsupported FIFO Depth (Not yet implemented)"
- severity failure;
- return 0;
- end case;
- end Calculate_Right_Mem_Size;
-
- -----------------------------------------------------------------------------
- -- Create a resolved Boolean type (rboolean)
- -----------------------------------------------------------------------------
-
- -- Create a Boolean array type
- type boolean_array is array (natural range <>) of boolean;
-
- -- Function for resolved boolean
- -- If any boolean in the array is false, then the result is false
- function resolve_boolean( values: in boolean_array ) return boolean is
- variable result: boolean := TRUE;
- begin
- if (values'length = 1) then
- result := values(values'low);
- else
- -- coverage off
- for index in values'range loop
- if values(index) = FALSE then
- result := FALSE;
- end if;
- end loop;
- -- coverage on
- end if;
- return result;
- end function resolve_boolean;
-
- subtype rboolean is resolve_boolean boolean;
-
-
- -- Convert the FIFO memsize to memsizes in steps of 16
- constant True_Mem_Size : Integer := Calculate_Right_Mem_Size(MemSize);
-
--- component Gen_DpRAM
--- generic (
--- Use_Muxes : Boolean := False;
--- Mem_Size : Integer := 36;
--- Addr_Size : Integer := 6;
--- Data_Size : Integer := 16
--- );
--- port (
--- Reset : in Std_Logic;
--- -- Read/Write port 1
--- Addr1 : in Std_Logic_Vector(Addr_Size-1 downto 0);
--- WrClk : in Std_Logic;
--- WE : in Std_Logic;
--- DataIn : in Std_Logic_Vector(Data_Size-1 downto 0);
--- DataOut1 : out Std_Logic_Vector(Data_Size-1 downto 0);
--- -- Read port 2
--- Addr2 : in Std_Logic_Vector(Addr_Size-1 downto 0);
--- DataOut2 : out Std_Logic_Vector(Data_Size-1 downto 0)
--- );
--- end component;
-
- ----------------------------------------------------------------------
- -- Returns the vector size needed to represent the X
- -- The result is > 0
- ----------------------------------------------------------------------
- function Vec_Size( X : in Natural) return Natural is
- variable I : Natural := 1;
- begin
- while (2**I) < X loop
- I := I + 1;
- end loop;
- return I;
- end function Vec_Size;
-
- -- Declare the types and constant counting schemes
- subtype Count_Word is Std_Logic_Vector(3 downto 0);
- type Count_Array_Type is array (integer range <>) of Count_Word;
-
- -- Even if there is four bits for the Cnt8, the fourth bit will never be used
- constant Cnt8 : Count_Array_Type(0 to 7) := ( "0000","0001","0011","0010",
- "0110","0111","0101","0100");
- constant Cnt10 : Count_Array_Type(0 to 9) := ( "0000","1000","1001","0001",
- "0011","0010","0110","0111",
- "0101","0100" );
- constant Cnt12 : Count_Array_Type(0 to 11) := ( "0000","1000","1001","1011",
- "1010","0010","0011","0001",
- "0101","0111","0110","0100" );
- constant Cnt14 : Count_Array_Type(0 to 13) := ( "0000","1000","1100","1101",
- "1001","1011","1010","0010",
- "0011","0001","0101","0111",
- "0110","0100");
- constant Cnt16 : Count_Array_Type(0 to 15) := ( "0000","0001","0011","0010",
- "0110","0100","0101","0111",
- "1111","1110","1100","1101",
- "1001","1011","1010","1000");
-
- -----------------------------------------------------------------------------
- -- A function that do all the boolean equations for a counting scheme
- -- given as a parameter
- -- The synthesis tool will unroll the loops and then do the boolean equation
- -- minimization (hopefully the optimimal).
- -- At present it only handles counting scheme with 4 bits due to the
- -- Count_Array_Type definition
- -----------------------------------------------------------------------------
- function Gen_Counter(Count_Scheme : in Count_Array_Type;
- Up : in Boolean;
- Count : in Std_Logic_Vector)
- return Std_Logic_Vector is
- variable Temp : Std_Logic;
- variable L : Integer range Count_Scheme'Range;
- variable Q : Std_Logic_Vector(Count'Length-1 downto 0);
- variable Q_Temp : Std_Logic_Vector(Count'Length-1 downto 0);
- begin -- Gen_Counter
- Q := Count;
- for G in Q'Range loop
- Q_Temp(G) := '0';
- for I in Count_Scheme'range loop
- if Count_Scheme(I)(G) = '1' then
- if Up then
- L := I - 1;
- else
- if I /= Count_Scheme'High then
- L := I + 1;
- else
- L := Count_Scheme'Low;
- end if;
- end if;
- Temp := '1';
- for J in Q'Range loop
- if Count_Scheme(L)(J) = '1' then
- Temp := Temp and Q(J);
- else
- Temp := Temp and not Q(J);
- end if;
- end loop;
- Q_Temp(G) := Q_Temp(G) or Temp;
- end if;
- end loop; -- I
- end loop; -- G
- return Q_Temp;
- end Gen_Counter;
-
- ----------------------------------------------------------------------
- -- Generate the Address counter for FIFO handling
- -- generates different counters depending of the counter size
- ----------------------------------------------------------------------
- Procedure FIFO_Count( Count : inout Std_Logic_Vector;
- Incr : in Boolean;
- Up : inout Boolean;
- Change : inout Boolean) is
- variable Cnt : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- begin
- if True_Mem_Size = 16 then
- if Incr then
- Res := Gen_Counter(Cnt16,True,Cnt);
- end if;
- elsif True_Mem_Size = 32 then
- if Incr then
- if not Change and
- (( (Cnt(2 downto 0) = "100") and Up) or
- ( (Cnt(2 downto 0) = "000") and not Up)) then
- Res(4) := Cnt(3);
- Res(3) := not Cnt(4);
- Res(2 downto 0) := Cnt(2 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(4 downto 3) := Cnt(4 downto 3);
- Res(2 downto 0) := Gen_Counter(Cnt8,Up,Cnt(2 downto 0));
- end if;
- end if;
- elsif True_Mem_Size = 64 then
- if Incr then
- if not Change and
- (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
- ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
- Res(5) := Cnt(4);
- Res(4) := not Cnt(5);
- Res(3 downto 0) := Cnt(3 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(5 downto 4) := Cnt(5 downto 4);
- Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
- end if;
- end if;
- elsif True_Mem_Size = 128 then
- -- Do a 3-bit grey counter + a 4-bit grey counter
- if Incr then
- if not Change and
- (( (Cnt(3 downto 0) = Cnt16(Cnt16'High)) and Up) or
- ( (Cnt(3 downto 0) = Cnt16(Cnt16'Low)) and not Up)) then
- Res(6 downto 4) := Gen_Counter(Cnt8,True,Cnt(6 downto 4));
- Res(3 downto 0) := Cnt(3 downto 0);
- Up := not Up;
- Change := True;
- else
- Change := False;
- Res(6 downto 4) := Cnt(6 downto 4);
- Res(3 downto 0) := Gen_Counter(Cnt16,Up,Cnt(3 downto 0));
- end if;
- end if;
- else
- assert false
- report "To BIG FIFO (not yet supported)"
- severity failure;
- end if;
- Count := Res;
- end FIFO_Count;
-
- Procedure FIFO_Counter( signal Count : inout Std_Logic_Vector;
- Incr : in Boolean;
- Up : inout Boolean;
- Change : inout Boolean) is
- variable Res : Std_Logic_Vector(Count'Left-Count'Right downto 0) := Count;
- begin
- FIFO_Count(Res,Incr,Up,Change);
- Count <= Res;
- end FIFO_Counter;
-
- constant Log2_Mem_Size : Integer := Vec_Size(True_Mem_Size);
-
- -- The read and write pointers
- subtype Pointer_Type is Std_Logic_Vector(Log2_Mem_Size-1 downto 0);
- signal Write_Ptr : Pointer_Type;
- signal Read_Ptr : Pointer_Type;
- signal Write_Addr : Pointer_Type;
- signal Read_Addr : Pointer_Type;
-
- signal DataOut1 : Std_Logic_Vector(WordSize-1 downto 0); -- NOT USED
-
- signal Dir_Latched : Boolean;
- signal Direction : Boolean;
- signal Equal : Boolean;
- signal Full_I : Boolean;
- signal Empty_I : Boolean;
- signal Full_Out : Boolean;
- signal Empty_Out : Boolean;
-
- signal Read : rboolean;
- signal Write : rboolean;
-
- -----------------------------------------------------------------------------
- -- Implement the RAM with pure RTL
- -----------------------------------------------------------------------------
- type RAM_TYPE is array (natural range 0 to MemSize-1) of std_logic_vector(WordSize-1 downto 0);
- signal Memory : RAM_TYPE := (others => (others => '0'));
-
-begin
-
- -----------------------------------------------------------------------------
- -- Change the Read and Write pointer to get the FIFO addresses
- -- This will get the four lowest bits from the Read/Write pointers to be the
- -- higest bits in FIFO addresses. This assures that when the FIFO depth is
- -- not a power of 2, that the FIFO addresses is within the FIFO depth range
- -----------------------------------------------------------------------------
- Do_FIFO_Addr : process (Write_Ptr, Read_Ptr)
- begin -- process Do_FIFO_Addr
- Write_Addr(Write_Addr'High downto Write_Addr'High-3) <=
- Write_Ptr(3 downto 0);
- if Write_Ptr'Length > 4 then
- Write_Addr(Write_Addr'High-4 downto Write_Addr'Low) <=
- Write_Ptr(Write_Ptr'High downto 4);
- end if;
- Read_Addr(Read_Addr'High downto Read_Addr'High-3) <=
- Read_Ptr(3 downto 0);
- if Read_Ptr'Length > 4 then
- Read_Addr(Read_Addr'High-4 downto Read_Addr'Low) <=
- Read_Ptr(Read_Ptr'High downto 4);
- end if;
- end process Do_FIFO_Addr;
-
- ----------------------------------------------------------------------
- -- Instansiate the Dual Port memory
- ----------------------------------------------------------------------
- Write_To_Memory: process (WrClk) is
- begin -- process Write_To_Memory
- if WrClk'event and WrClk = '1' then -- rising clock edge
- if WE = '1' then
- Memory(to_integer(unsigned(Write_Addr))) <= DataIn;
- end if;
- end if;
- end process Write_To_Memory;
-
- DataOut1 <= Memory(to_integer(unsigned(Write_Addr)));
- DataOut <= Memory(to_integer(unsigned(Read_Addr)));
-
--- FIFO_MEM : Gen_DpRAM
--- generic map(
--- Use_Muxes => true,
--- Mem_Size => MemSize,
--- Addr_Size => Log2_Mem_Size,
--- Data_Size => WordSize
--- )
--- port map (
--- Reset => Reset,
--- Addr1 => Write_Addr,
--- WrClk => WrClk,
--- WE => WE,
--- DataIn => DataIn,
--- DataOut1 => DataOut1,
--- Addr2 => Read_Addr,
--- DataOut2 => DataOut
--- );
-
- Protect_FIFO : if Protect generate
- Read <= (Rd = '1') and not Empty_Out;
- Write <= (We = '1') and not Full_Out;
- end generate Protect_FIFO;
-
- Non_Protect_FIFO : if not Protect generate
- Read <= (Rd = '1');
- Write <= (We = '1');
- end generate Non_Protect_FIFO;
- ----------------------------------------------------------------------
- -- Read Pointer
- ----------------------------------------------------------------------
- Read_Ptr_Counter : process(Reset,RdClk)
- variable Up : Boolean;
- variable Change : Boolean;
- begin
- if (Reset = '1') then
- Read_Ptr <= (others => '0');
- Up := True;
- Change := False;
- elsif RdClk'Event and RdClk = '1' then
- FIFO_Counter(Read_Ptr,Read,Up,Change);
- end if;
- end process Read_Ptr_Counter;
-
- ----------------------------------------------------------------------
- -- Write Pointer
- ----------------------------------------------------------------------
- Write_Ptr_Counter : process(Reset,WrClk)
- variable Up : Boolean;
- variable Change : Boolean;
- begin
- if (Reset = '1') then
- Write_Ptr <= (others => '0');
- Up := True;
- Change := False;
- elsif WrClk'Event and WrClk = '1' then
- FIFO_Counter(Write_Ptr,Write,Up,Change);
- end if;
- end process Write_Ptr_Counter;
-
- ----------------------------------------------------------------------
- -- Flag handling
- ----------------------------------------------------------------------
-
- -------------------------------------------------------------------------
- -- Dir_Latched is false after reset and then true after the first write
- ---------------------------------------------------------------------------
- Direction_Latch : process(Reset,WE,WrClk)
- begin
- if (Reset = '1') then
- Dir_Latched <= False;
- elsif WrClk'Event and WrClk = '1' then
- Dir_Latched <= Dir_Latched or (WE = '1');
- end if;
- end process Direction_Latch;
-
- -----------------------------------------------------------------------------
- -- Trying to see if the read pointer is catching up the write pointer or
- -- vice verse
- -- The top two bits of the pointers always counts as follows
- -- 00
- -- 01
- -- 11
- -- 10
- -- 00
- -- ..
- -- So if read pointer is one step behind the write pointer => Reset = True
- -- And if write pointer is one step behind the read pointer => Set = True
- -----------------------------------------------------------------------------
- Direction_Proc : process(Read_Ptr, Write_Ptr, Dir_Latched, Direction)
- variable Set : Boolean;
- variable Clear : Boolean;
- variable Read_MSB : Std_Logic_Vector(1 downto 0);
- variable Write_MSB : Std_Logic_Vector(1 downto 0);
- begin
- Read_MSB := Read_Ptr(Read_Ptr'Left) & Read_Ptr(Read_Ptr'Left-1);
- Write_MSB := Write_Ptr(Write_Ptr'Left) & Write_Ptr(Write_Ptr'Left-1);
- if (Read_MSB = "00" and Write_MSB = "01") or
- (Read_MSB = "01" and Write_MSB = "11") or
- (Read_MSB = "11" and Write_MSB = "10") or
- (Read_MSB = "10" and Write_MSB = "00") then
- Clear := True;
- else
- Clear := False;
- end if;
- if (Write_MSB = "00" and Read_MSB = "01") or
- (Write_MSB = "01" and Read_MSB = "11") or
- (Write_MSB = "11" and Read_MSB = "10") or
- (Write_MSB = "10" and Read_MSB = "00") then
- Set := True;
- else
- Set := False;
- end if;
- Direction <= not ((not Dir_Latched) or Clear or not(Set or Direction));
- end process Direction_Proc;
-
- Equal <= (Read_Ptr = Write_Ptr);
- Full_I <= Equal and Direction;
- Empty_I <= Equal and not Direction;
-
- -- Allow Empty to go active directly since the change is due to a read
- -- which means that the Empty_I is synchronized with RdClk.
- -- But is only allow to go inactive when RdClk is High since the transaction
- -- is due to a Write and Empty_I is NOT synchronized with RdClk.
- -- By this way the Empty is not changed state just before rising edge of RdClk
- Empty_DFF : process(Empty_I,RdClk)
- begin
- if Empty_I then
- Empty_Out <= True;
- elsif RdClk'Event and RdClk = '1' then
- Empty_Out <= Empty_I;
- end if;
- end process Empty_DFF;
-
- Exists <= '0' when Empty_Out else '1';
-
- -- See above but for Full and WrClk
- Full_DFF : process(Full_I,WrClk)
- begin
- if Full_I then
- Full_Out <= True;
- elsif WrClk'Event and WrClk = '1' then
- Full_Out <= Full_I;
- end if;
- end process Full_DFF;
-
- Full <= '1' when Full_Out else '0';
-
-end VHDL_RTL;
-
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/async_fifo_bram.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/async_fifo_bram.vhd
deleted file mode 100644
index 3a35d050e89c5a144e34909262fa1338354b53f5..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/async_fifo_bram.vhd
+++ /dev/null
@@ -1,429 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: async_fifo_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_bram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: rolandp
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- rolandp 2006 New Versionuse IEEE.std_logic_unsigned.all;
-
---
--- Description:
--- Code to infer asynchronous dual port bram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity Async_FIFO_BRAM is
- generic (
- WordSize : integer := 8;
- MemSize : integer := 16;
- Protect : boolean := false
- );
- port (
- Reset : in std_logic;
- -- Clock region WrClk
- WrClk : in std_logic;
- WE : in std_logic;
- DataIn : in std_logic_vector(WordSize-1 downto 0);
- Full : out std_logic;
- -- Clock region RdClk
- RdClk : in std_logic;
- RD : in std_logic;
- DataOut : out std_logic_vector(WordSize-1 downto 0);
- Exists : out std_logic
- );
-end entity Async_FIFO_BRAM;
-
-architecture IMP of Async_FIFO_BRAM is
-
- attribute ram_style : string;
-
- function Bin2Gray(constant bin : std_logic_vector)
- return std_logic_vector is
- variable gray : std_logic_vector(bin'range);
- begin
- gray(bin'high) := bin(bin'high);
- for I in bin'high - 1 downto bin'low loop
- gray(I) := bin(I + 1) xor bin(I);
- end loop;
- return gray;
- end function Bin2Gray;
-
- function Log2(x : integer) return integer is
- variable i : integer := 0;
- begin
- -- coverage off
- if x = 0 then return 0;
- -- coverage on
- else
- while 2**i < x loop
- i := i+1;
- end loop;
- return i;
- end if;
- end function Log2;
-
- type ram_type is array (2**Log2(MemSize)-1 downto 0) of std_logic_vector(WordSize-1 downto 0);
-
- signal ram_mem : ram_type;
- attribute ram_style of ram_mem : signal is "block";
-
- signal read_enable : std_logic;
- signal write_enable : std_logic;
-
- signal read_allow : std_logic;
- signal write_allow : std_logic;
-
- signal empty_allow : std_logic;
- signal full_allow : std_logic;
-
- signal full_i : std_logic;
- signal empty : std_logic;
-
- signal emptyg : std_logic;
- signal fullg : std_logic;
-
- signal read_addr_next : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal read_lastgray : std_logic_vector(Log2(MemSize)-1 downto 0);
-
- signal write_addr : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal write_addrgray : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal write_nextgray : std_logic_vector(Log2(MemSize)-1 downto 0);
-
- signal ecomp : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal fcomp : std_logic_vector(Log2(MemSize)-1 downto 0);
- signal emuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
- signal fmuxcyo : std_logic_vector(Log2(MemSize)-2 downto 0);
-
-begin
-
- -- Assign local signals from ports
- read_enable <= RD;
- write_enable <= WE;
-
- -- Memory array
- WritePort : process (WrClk)
- begin
- if (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- ram_mem(To_integer(unsigned(write_addr))) <= DataIn;
- end if;
- end if;
- end process WritePort;
-
- ReadPort : process (RdClk)
- begin
- if (RdClk'event and RdClk = '1') then
- DataOut <= ram_mem(To_integer(unsigned(read_addr_next)));
- end if;
- end process ReadPort;
-
- ----------------------------------------------------------------
- -- Allow flags determine whether FIFO control logic can --
- -- operate. If read_enable is driven high, and the FIFO is --
- -- not Empty, then Reads are allowed. Similarly, if the --
- -- write_enable signal is high, and the FIFO is not Full, --
- -- then Writes are allowed. --
- ----------------------------------------------------------------
-
- read_allow <= (read_enable and not empty);
- write_allow <= (write_enable and not full_i);
-
- ---------------------------------------------------------------
- -- Empty flag is set on Reset (initial), or when gray --
- -- code counters are equal, or when there is one word in --
- -- the FIFO, and a Read operation is about to be performed. --
- ---------------------------------------------------------------
-
- empty_allow <= (empty or read_enable); -- Is empty or possibly going to be empty
-
- EmptyFlag : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- empty <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (empty_allow = '1') then
- empty <= emptyg;
- end if;
- end if;
- end process EmptyFlag;
-
- Exists <= not empty;
-
- ---------------------------------------------------------------
- -- Full flag is set on Reset (initial, but it is cleared --
- -- on the first valid write_clock edge after Reset is --
- -- de-asserted), or when Gray-code counters are one away --
- -- from being equal (the Write Gray-code address is equal --
- -- to the Last Read Gray-code address), or when the Next --
- -- Write Gray-code address is equal to the Last Read Gray- --
- -- code address, and a Write operation is about to be --
- -- performed. --
- ---------------------------------------------------------------
-
- full_allow <= (full_i or write_enable); -- Is full or possibly going to be full
-
- FullFlag : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- full_i <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (full_allow = '1') then
- full_i <= fullg;
- end if;
- end if;
- end process FullFlag;
-
- Full <= full_i;
-
- ----------------------------------------------------------------
- -- Generation of Read address pointers. The primary one is --
- -- binary (read_addr), and the Gray-code derivatives are --
- -- generated via pipelining the binary-to-Gray-code result. --
- -- The initial values are important, so they're in sequence. --
- -- --
- -- Grey-code addresses are used so that the registered --
- -- Full and Empty flags are always clean, and never in an --
- -- unknown state due to the asynchonous relationship of the --
- -- Read and Write clocks. In the worst case scenario, Full --
- -- and Empty would simply stay active one cycle longer, but --
- -- it would not generate an error or give false values. --
- ----------------------------------------------------------------
-
- read_addr_next <= std_logic_vector(unsigned(read_addr) + 1) when read_allow = '1' else read_addr;
-
- ReadAddrCnt : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_addr <= (others => '0');
- elsif (RdClk'event and RdClk = '1') then
- read_addr <= read_addr_next;
- end if;
- end process ReadAddrCnt;
-
- ReadNextGray : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_nextgray(read_nextgray'high-1 downto 0) <= (others => '0');
- read_nextgray(read_nextgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_nextgray <= Bin2Gray(read_addr);
- end if;
- end if;
- end process ReadNextGray;
-
- ReadAddrGray : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_addrgray(read_addrgray'high-1 downto 1) <= (others => '0');
- read_addrgray(0) <= '1';
- read_addrgray(read_addrgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_addrgray <= read_nextgray;
- end if;
- end if;
- end process ReadAddrGray;
-
- ReadLastGrey : process (RdClk, Reset)
- begin
- if (Reset = '1') then
- read_lastgray(read_lastgray'high-1 downto 2) <= (others => '0');
- read_lastgray(0) <= '1';
- read_lastgray(1) <= '1';
- read_lastgray(read_lastgray'high) <= '1';
- elsif (RdClk'event and RdClk = '1') then
- if (read_allow = '1') then
- read_lastgray <= read_addrgray;
- end if;
- end if;
- end process ReadLastGrey;
-
- ----------------------------------------------------------------
- -- Generation of Write address pointers. Identical copy of --
- -- read pointer generation above, except for names. --
- ----------------------------------------------------------------
-
- WriteAddrCnt : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_addr <= (others => '0');
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_addr <= std_logic_vector(unsigned(write_addr) + 1);
- end if;
- end if;
- end process WriteAddrCnt;
-
- WriteNextGray : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_nextgray(write_nextgray'high-1 downto 0) <= (others => '0');
- write_nextgray(write_nextgray'high) <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_nextgray <= Bin2Gray(write_addr);
- end if;
- end if;
- end process WriteNextGray;
-
- WriteAddrGray : process (WrClk, Reset)
- begin
- if (Reset = '1') then
- write_addrgray(write_addrgray'high-1 downto 0) <= (others => '0');
- write_addrgray(0) <= '1';
- write_addrgray(write_addrgray'high) <= '1';
- elsif (WrClk'event and WrClk = '1') then
- if (write_allow = '1') then
- write_addrgray <= write_nextgray;
- end if;
- end if;
- end process WriteAddrGray;
-
-----------------------------------------------------------------
--- The two conditions decoded with special carry logic are --
--- Empty and Full (gated versions). These are used to --
--- determine the next state of the Full/Empty flags. Carry --
--- logic is used for optimal speed. (The previous --
--- implementation of AlmostEmpty and AlmostFull have been --
--- wrapped into the corresponding carry chains for faster --
--- performance). --
--- --
--- When write_addrgray is equal to read_addrgray, the FIFO --
--- is Empty, and emptyg (combinatorial) is asserted. Or, --
--- when write_addrgray is equal to read_nextgray (1 word in --
--- the FIFO) then the FIFO potentially could be going Empty, --
--- so emptyg is asserted, and the Empty flip-flop enable is --
--- gated with empty_allow, which is conditioned with a valid --
--- read. --
--- --
--- Similarly, when read_lastgray is equal to write_addrgray, --
--- the FIFO is full (511 addresses). Or, when read_lastgray --
--- is equal to write_nextgray, then the FIFO potentially --
--- could be going Full, so fullg is asserted, and the Full --
--- flip-flop enable is gated with full_allow, which is --
--- conditioned with a valid write. --
--- --
--- Note: To have utilized the full address space (512) --
--- would have required extra logic to determine Full/Empty --
--- on equal addresses, and this would have slowed down the --
--- overall performance, which was the top priority. --
-----------------------------------------------------------------
-
- ECompare : process(write_addrgray, read_addrgray, read_nextgray, empty)
- begin
- for I in 0 to Log2(MemSize)-1 loop
- ecomp(I) <= (not (write_addrgray(I) xor read_addrgray(I)) and empty) or
- (not (write_addrgray(I) xor read_nextgray(I)) and not empty);
- end loop;
- end process ECompare;
-
- emuxcylow : MUXCY_L port map(DI => '0', CI => '1', S => ecomp(0), LO => emuxcyo(0));
-
- Gen_emuxcy : for I in 1 to Log2(MemSize)-2 generate
- begin
- emuxcy : MUXCY_L port map(DI => '0', CI => emuxcyo(I-1), S => ecomp(I), LO => emuxcyo(I));
- end generate Gen_emuxcy;
-
- emuxcyhigh : MUXCY_L port map(DI => '0', CI => emuxcyo(Log2(MemSize)-2), S => ecomp(Log2(MemSize)-1), LO => emptyg);
-
- FCompare : process(read_lastgray, write_addrgray, write_nextgray, full_i)
- begin
- for I in 0 to Log2(MemSize)-1 loop
- fcomp(I) <= (not (read_lastgray(I) xor write_addrgray(I)) and full_i) or
- (not (read_lastgray(I) xor write_nextgray(I)) and not full_i);
- end loop;
- end process FCompare;
-
- fmuxcylow : MUXCY_L port map (DI => '0', CI => '1', S => fcomp(0), LO => fmuxcyo(0));
-
- Gen_fmuxcy : for I in 1 to Log2(MemSize)-2 generate
- begin
- fmuxcy : MUXCY_L port map (DI => '0', CI => fmuxcyo(I-1), S => fcomp(I), LO => fmuxcyo(I));
- end generate Gen_fmuxcy;
-
- fmuxcyhigh : MUXCY_L port map (DI => '0', CI => fmuxcyo(Log2(MemSize)-2), S => fcomp(Log2(MemSize)-1), LO => fullg);
-
-end architecture IMP;
-
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/fsl_v20.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/fsl_v20.vhd
deleted file mode 100644
index f003b6e0a311702e6040fbdde02bf9c6db608a56..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/fsl_v20.vhd
+++ /dev/null
@@ -1,469 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- fsl_v20.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: fsl_v20.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2003-02-13 First Version
--- satish 2004-03-03 New Version
--- rolandp 2006-08-20 BRAM in asynch mode
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-
-library Unisim;
-use Unisim.vcomponents.all;
-
-library compaandesign_com_common_fifo_1;
-use compaandesign_com_common_fifo_1.sync_fifo;
-use compaandesign_com_common_fifo_1.async_fifo;
-
-entity fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end entity fsl_v20;
-
-architecture IMP of fsl_v20 is
-
- component Sync_FIFO is
- generic (
- C_IMPL_STYLE : Integer;
- WordSize : Integer;
- MemSize : Integer);
- port (
- Reset : in Std_Logic;
- Clk : in Std_Logic;
-
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Sync_FIFO;
-
- component Async_FIFO is
- generic (
- WordSize : Integer;
- MemSize : Integer;
- Protect : Boolean);
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Async_FIFO;
-
- component Async_FIFO_BRAM is
- generic (
- WordSize : Integer;
- MemSize : Integer;
- Protect : Boolean);
- port (
- Reset : in Std_Logic;
- -- Clock region WrClk
- WrClk : in Std_Logic;
- WE : in Std_Logic;
- DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
- Full : out Std_Logic;
- -- Clock region RdClk
- RdClk : in Std_Logic;
- RD : in Std_Logic;
- DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
- Exists : out Std_Logic);
- end component Async_FIFO_BRAM;
-
- signal sys_rst_i : std_logic;
- signal srl_time_out : std_logic;
- signal fsl_rst_i : std_logic;
- signal Data_In : std_logic_vector(0 to C_FSL_DWIDTH);
- signal Data_Out : std_logic_vector(0 to C_FSL_DWIDTH);
-
- signal fifo_full : std_logic;
- -- signal fifo_half_full : std_logic;
- -- signal fifo_half_empty : std_logic;
- signal fifo_has_data : std_logic;
-
- signal fsl_s_control_i : std_logic;
-
- signal srl_clk : std_logic;
-
-begin -- architecture IMP
-
- SYS_RST_PROC : process (SYS_Rst) is
- variable sys_rst_input : std_logic;
- begin
- if C_EXT_RESET_HIGH = 0 then
- sys_rst_i <= not SYS_Rst;
- else
- sys_rst_i <= SYS_Rst;
- end if;
- end process SYS_RST_PROC;
-
- Rst_Delay_Async: if (C_ASYNC_CLKS /= 0) generate
- srl_clk <= FSL_M_Clk;
-
- end generate Rst_Delay_Async;
-
- Rst_Delay_Sync: if (C_ASYNC_CLKS = 0) generate
- srl_clk <= FSL_Clk;
- end generate Rst_Delay_Sync;
-
- POR_SRL_I : SRL16
- generic map (
- INIT => X"FFFF")
- port map (
- D => '0',
- CLK => srl_Clk,
- A0 => '1',
- A1 => '1',
- A2 => '1',
- A3 => '1',
- Q => srl_time_out);
-
- POR_FF_I : FDS
- port map (
- Q => fsl_rst_i,
- D => srl_time_out,
- C => srl_Clk,
- S => sys_rst_i);
-
- FSL_Rst <= fsl_rst_i;
-
-
- -----------------------------------------------------------------------------
- -- Width is 1, so implement a registers
- -----------------------------------------------------------------------------
- Only_Register : if (C_FSL_DEPTH = 1) generate
- signal fsl_s_exists_i : std_logic;
- signal fsl_m_full_i : std_logic;
- begin
-
- -- FSL_S_Clk and FSL_M_Clk are the same
- Sync_Clocks: if (C_ASYNC_CLKS = 0) generate
-
- FIFO : process (FSL_Clk) is
- variable fifo_full : std_logic;
- begin -- process FIFO
- if FSL_Clk'event and FSL_Clk = '1' then -- rising clock edge
- if fsl_rst_i = '1' then -- synchronous reset (active high)
- fifo_full := '0';
- Fsl_m_full_i <= '1';
- Fsl_s_exists_i <= '0';
- else
- if (fifo_full = '0') then -- Empty
- if (FSL_M_Write = '1') then
- fifo_full := '1';
- FSL_S_Data <= FSL_M_Data;
- fsl_s_control_i <= FSL_M_Control;
- end if;
- end if;
- if (fifo_full = '1') then -- Has data
- if (FSL_S_Read = '1') then
- fifo_full := '0';
- end if;
- end if;
- Fsl_m_full_i <= fifo_full;
- Fsl_s_exists_i <= fifo_full;
- end if;
- end if;
- end process FIFO;
- end generate Sync_Clocks;
-
- FSL_S_Exists <= fsl_s_exists_i;
- FSL_Has_Data <= fsl_s_exists_i;
-
- FSL_M_Full <= fsl_m_full_i;
- FSL_Full <= fsl_m_full_i;
-
- FSL_S_Control <= fsl_s_control_i when C_USE_CONTROL /= 0 else '0';
- FSL_Control_IRQ <= fsl_s_control_i and fsl_s_exists_i when C_USE_CONTROL /= 0 else '0';
-
- end generate Only_Register;
-
- Using_FIFO: if (C_FSL_DEPTH > 1) generate
- begin
- -- Map Master Data/Control signal
- Data_In(0 to C_FSL_DWIDTH-1) <= FSL_M_Data;
-
- -- Map Slave Data/Control signal
- FSL_S_Data <= Data_Out(0 to C_FSL_DWIDTH-1);
-
- -- SRL FIFO BASED IMPLEMENTATION
- Sync_FIFO_Gen : if (C_ASYNC_CLKS = 0) generate
- Use_Control: if (C_USE_CONTROL /= 0) generate
-
- Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
- fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
-
- Sync_FIFO_I1 : Sync_FIFO
- generic map (
- C_IMPL_STYLE => C_IMPL_STYLE,
- WordSize => C_FSL_DWIDTH + 1,
- MemSize => C_FSL_DEPTH)
- port map (
- Reset => fsl_rst_i,
- Clk => FSL_Clk,
- WE => FSL_M_Write,
- DataIn => Data_In,
- Full => fifo_full,
- RD => FSL_S_Read,
- DataOut => Data_Out,
- Exists => fifo_has_data);
- end generate Use_Control;
-
- Use_Data: if (C_USE_CONTROL = 0) generate
-
- fsl_s_control_i <= '0';
-
- Sync_FIFO_I1 : Sync_FIFO
- generic map (
- C_IMPL_STYLE => C_IMPL_STYLE,
- WordSize => C_FSL_DWIDTH,
- MemSize => C_FSL_DEPTH)
- port map (
- Reset => fsl_rst_i,
- Clk => FSL_Clk,
- WE => FSL_M_Write,
- DataIn => Data_In(0 to C_FSL_DWIDTH-1),
- Full => fifo_full,
- RD => FSL_S_Read,
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1),
- Exists => fifo_has_data);
-
- end generate Use_Data;
- end generate Sync_FIFO_Gen;
-
- Async_FIFO_Gen: if (C_ASYNC_CLKS /= 0) generate
-
- Use_Control: if (C_USE_CONTROL /= 0) generate
-
- Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
- fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
-
- Use_DPRAM1: if (C_IMPL_STYLE = 0) generate
- -- LUT RAM implementation
- Async_FIFO_I1: Async_FIFO
- generic map (
- WordSize => C_FSL_DWIDTH + 1, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_DPRAM1;
-
- Use_BRAM1: if (C_IMPL_STYLE /= 0) generate
- -- BRAM implementation
- Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
- generic map (
- WordSize => C_FSL_DWIDTH + 1, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_BRAM1;
-
- end generate Use_Control;
-
- Use_Data: if (C_USE_CONTROL = 0) generate
-
- fsl_s_control_i <= '0';
-
- Use_DPRAM0: if (C_IMPL_STYLE = 0) generate
- -- LUT RAM implementation
- Async_FIFO_I1 : Async_FIFO
- generic map (
- WordSize => C_FSL_DWIDTH, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_DPRAM0;
-
- Use_BRAM0: if (C_IMPL_STYLE /= 0) generate
- -- BRAM implementation
- Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
- generic map (
- WordSize => C_FSL_DWIDTH, -- [Integer]
- MemSize => C_FSL_DEPTH, -- [Integer]
- Protect => true) -- [Boolean]
- port map (
- Reset => fsl_rst_i, -- [in Std_Logic]
- -- Clock region WrClk
- WrClk => FSL_M_Clk, -- [in Std_Logic]
- WE => FSL_M_Write, -- [in Std_Logic]
- DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
- Full => fifo_full, -- [out Std_Logic]
- -- Clock region RdClk
- RdClk => FSL_S_Clk, -- [in Std_Logic]
- RD => FSL_S_Read, -- [in Std_Logic]
- DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
- Exists => fifo_has_data); -- [out Std_Logic]
- end generate Use_BRAM0;
-
- end generate Use_Data;
-
- end generate Async_FIFO_Gen;
-
- FSL_M_Full <= fifo_full or fsl_rst_i; -- Inhibit writes during reset by
- -- forcing full to '1'
- FSL_S_Exists <= fifo_has_data;
-
- FSL_Full <= fifo_full;
- FSL_Has_Data <= fifo_has_data;
-
- FSL_S_Control <= fsl_s_control_i;
- FSL_Control_IRQ <= fsl_s_control_i and fifo_has_data;
-
- end generate Using_FIFO;
-
-end architecture IMP;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_srlfifo.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_srlfifo.vhd
deleted file mode 100644
index 529f49e665de6b94a7fc034f25f710763a976576..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_srlfifo.vhd
+++ /dev/null
@@ -1,220 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: gen_srlfifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- srl_fifo.vhd - Entity and architecture
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Filename: srl_fifo.vhd
---
--- Description:
---
--- VHDL-Standard: VHDL'93
--------------------------------------------------------------------------------
--- Structure:
--- srl_fifo.vhd
---
--------------------------------------------------------------------------------
--- Author: goran
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- goran 2003-02-13 First Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity SRL_FIFO is
- generic (
- C_DATA_BITS : integer := 8;
- C_DEPTH : integer := 16
- );
- port (
- Clk : in std_logic;
- Reset : in std_logic;
- FIFO_Write : in std_logic;
- Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Read : in std_logic;
- Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Full : out std_logic;
- -- FIFO_Half_Full : out std_logic;
- -- FIFO_Half_Empty : out std_logic;
- Data_Exists : out std_logic
- );
-
-end entity SRL_FIFO;
-
-library UNISIM;
-use UNISIM.VCOMPONENTS.all;
-
-architecture IMP of SRL_FIFO is
-
- signal Addr : std_logic_vector(0 to 3);
- signal buffer_Full : std_logic;
- signal buffer_Empty : std_logic;
-
- signal next_Data_Exists : std_logic;
- signal data_Exists_I : std_logic;
-
- signal valid_Write : std_logic;
-
- signal hsum_A : std_logic_vector(0 to 3);
- signal sum_A : std_logic_vector(0 to 3);
- signal addr_cy : std_logic_vector(0 to 3);
-
- signal buffer_full_early : std_logic;
-
-begin -- architecture IMP
-
--- buffer_Full <= '1' when (Addr = "1111") else '0';
-
- buffer_full_early <= '1' when (sum_A = "1111") else '0';
-
- FDRE_I1: FDRE
- port map (
- Q => buffer_Full, -- [out std_logic]
- C => Clk, -- [in std_logic]
- CE => data_Exists_I, -- [in std_logic]
- D => buffer_full_early, -- [in std_logic]
- R => Reset); -- [in std_logic]
-
- FIFO_Full <= buffer_Full;
-
- -- FIFO_Half_Full <= Addr(3);
- -- FIFO_Half_Empty <= not Addr(3);
-
- buffer_Empty <= '1' when (Addr = "0000") else '0';
-
- next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
- (buffer_Empty and FIFO_Write) or
- (data_Exists_I and not FIFO_Read);
-
- Data_Exists_DFF : process (Clk) is
- begin -- process Data_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- data_Exists_I <= '0';
- else
- data_Exists_I <= next_Data_Exists;
- end if;
- end if;
- end process Data_Exists_DFF;
-
- Data_Exists <= data_Exists_I;
-
- valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
-
- addr_cy(0) <= valid_Write;
-
- Addr_Counters : for I in 0 to 3 generate
-
- hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-
- -- Don't need the last muxcy, addr_cy(4) is not used anywhere
- Used_MuxCY: if I < 3 generate
- MUXCY_L_I : MUXCY_L
- port map (
- DI => addr(I), -- [in std_logic]
- CI => addr_cy(I), -- [in std_logic]
- S => hsum_A(I), -- [in std_logic]
- LO => addr_cy(I+1)); -- [out std_logic]
- end generate Used_MuxCY;
-
- XORCY_I : XORCY
- port map (
- LI => hsum_A(I), -- [in std_logic]
- CI => addr_cy(I), -- [in std_logic]
- O => sum_A(I)); -- [out std_logic]
-
- FDRE_I : FDRE
- port map (
- Q => addr(I), -- [out std_logic]
- C => Clk, -- [in std_logic]
- CE => data_Exists_I, -- [in std_logic]
- D => sum_A(I), -- [in std_logic]
- R => Reset); -- [in std_logic]
-
- end generate Addr_Counters;
-
- FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
- SRL16E_I : SRL16E
- generic map (
- INIT => x"0000")
- port map (
- CE => valid_Write, -- [in std_logic]
- D => Data_In(I), -- [in std_logic]
- Clk => Clk, -- [in std_logic]
- A0 => Addr(0), -- [in std_logic]
- A1 => Addr(1), -- [in std_logic]
- A2 => Addr(2), -- [in std_logic]
- A3 => Addr(3), -- [in std_logic]
- Q => Data_Out(I)); -- [out std_logic]
- end generate FIFO_RAM;
-
-end architecture IMP;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_sync_bram.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_sync_bram.vhd
deleted file mode 100644
index 6b2a0690de0b64ac4dcf6273ff03e77274d96573..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_sync_bram.vhd
+++ /dev/null
@@ -1,129 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: gen_sync_bram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_bram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--- Description:
--- Code to infer synchronous dual port bram and separate read/write clock dual
--- port bram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-entity Sync_BRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- -- Write port
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- -- Read port
- dpra_en : in std_logic;
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
-end Sync_BRAM;
-
-architecture syn of Sync_BRAM is
- type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
- -- signal ram_mem : ram_type := (others => (others => '0'));
- signal ram_mem : ram_type;
- signal read_a : std_logic_vector(C_AWIDTH-1 downto 0);
- signal read_dpra : std_logic_vector(C_AWIDTH-1 downto 0);
-begin
- process (clk)
- begin
- if (clk'event and clk = '1') then
- if (we = '1') then
- ram_mem(conv_integer(a)) <= di;
- end if;
- read_a <= a;
- if (dpra_en = '1') then
- read_dpra <= dpra;
- end if;
- end if;
- end process;
- dpo <= ram_mem(conv_integer(read_dpra));
-end syn;
-
-
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_sync_dpram.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_sync_dpram.vhd
deleted file mode 100644
index e967febf4a701ebe7417a8de3038e6726fbc7243..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/gen_sync_dpram.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: gen_sync_dpram.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- gen_sync_dpram.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--- Description:
--- Code to infer synchronous dual port lut ram
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity Sync_DPRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
-end Sync_DPRAM;
-
-architecture syn of Sync_DPRAM is
- type ram_type is array ((2**C_AWIDTH)-1 downto 0) of std_logic_vector ((C_DWIDTH-1) downto 0);
- -- signal RAM : ram_type := (others => (others => '0'));
- signal RAM : ram_type;
-begin
- process (clk)
- begin
- if (clk'event and clk = '1') then
- if (we = '1') then
- RAM(conv_integer(a)) <= di;
- end if;
- end if;
- end process;
- dpo <= RAM(conv_integer(dpra));
-end syn;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/sync_fifo.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/sync_fifo.vhd
deleted file mode 100644
index 6f23d89cd2238314efbe6b58b7751d6534e37976..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/fifo/1/hdlsrc/sync_fifo.vhd
+++ /dev/null
@@ -1,397 +0,0 @@
--------------------------------------------------------------------------------
--- $Id: sync_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
--------------------------------------------------------------------------------
--- sync_fifo.vhd - Entity and architecture
--------------------------------------------------------------------------------
---
--- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES
---
--------------------------------------------------------------------------------
--- Author: satish
--- Revision: $Revision: 1.1.2.1 $
--- Date: $Date: 2010/10/28 11:17:56 $
---
--- History:
--- satish 2004-03-24 New Version
---
--------------------------------------------------------------------------------
--- Naming Conventions:
--- active low signals: "*_n"
--- clock signals: "clk", "clk_div#", "clk_#x"
--- reset signals: "rst", "rst_n"
--- generics: "C_*"
--- user defined types: "*_TYPE"
--- state machine next state: "*_ns"
--- state machine current state: "*_cs"
--- combinatorial signals: "*_com"
--- pipelined or register delay signals: "*_d#"
--- counter signals: "*cnt*"
--- clock enable signals: "*_ce"
--- internal version of output port "*_i"
--- device pins: "*_pin"
--- ports: - Names begin with Uppercase
--- processes: "*_PROCESS"
--- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.Std_Logic_1164.all;
-use IEEE.numeric_std.all;
-
-library compaandesign_com_common_fifo_1;
-use compaandesign_com_common_fifo_1.all;
-
-entity Sync_FIFO is
- generic (
- C_IMPL_STYLE : integer := 0;
- WordSize : integer := 8;
- MemSize : integer := 16
- );
- port (
- Reset : in std_logic;
- Clk : in std_logic;
-
- WE : in std_logic;
- DataIn : in std_logic_vector(WordSize-1 downto 0);
- Full : out std_logic;
- RD : in std_logic;
- DataOut : out std_logic_vector(WordSize-1 downto 0);
- Exists : out std_logic
- );
-end Sync_FIFO;
-
-architecture VHDL_RTL of Sync_FIFO is
-
- function log2(x : natural) return integer is
- variable i : integer := 0;
- begin
- -- coverage off
- if x = 0 then return 0;
- -- coverage on
- else
- while 2**i < x loop
- i := i+1;
- end loop;
- return i;
- end if;
- end function log2;
-
- constant AddrWidth : integer := log2(MemSize);
- signal Read_Address : std_logic_vector(0 to AddrWidth-1);
- signal Write_Address : std_logic_vector(0 to AddrWidth-1);
-
- component SRL_FIFO is
- generic (
- C_DATA_BITS : integer;
- C_DEPTH : integer);
- port (
- Clk : in std_logic;
- Reset : in std_logic;
- FIFO_Write : in std_logic;
- Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Read : in std_logic;
- Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
- FIFO_Full : out std_logic;
- -- FIFO_Half_Full : out std_logic;
- -- FIFO_Half_Empty : out std_logic;
- Data_Exists : out std_logic);
- end component SRL_FIFO;
-
- component Sync_DPRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
- end component;
-
- component Sync_BRAM is
- generic (
- C_DWIDTH : integer := 32;
- C_AWIDTH : integer := 16
- );
- port (
- clk : in std_logic;
- -- Write port
- we : in std_logic;
- a : in std_logic_vector(C_AWIDTH-1 downto 0);
- di : in std_logic_vector(C_DWIDTH-1 downto 0);
- -- Read port
- dpra_en : in std_logic;
- dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
- dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
- );
- end component;
-
- signal read_bram_enable : std_logic;
- signal DataOut_BRAM : std_logic_vector(WordSize-1 downto 0);
-
-
-begin
-
- FSL_Flag_Handle : if ((MemSize > 16) or (C_IMPL_STYLE /= 0)) generate
- signal read_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
- signal write_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
-
- signal full_i : std_logic;
- signal exists_i : std_logic;
- signal read_addr_incr : std_logic;
- signal first_write_on_empty_fifo : std_logic;
- signal last_word : std_logic;
-
- signal fifo_length : natural range 0 to MemSize;
- begin
-
- -- FIFO length handling
- Fifo_Length_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- fifo_length <= 0;
- else
- -- write and no read => increment length
- -- don't increment length when FULL
- if (WE = '1' and RD = '0' and full_i = '0') then
- fifo_length <= fifo_length + 1;
- -- read and no write => decrement length
- -- don't decrement length when EMPTY
- elsif (WE = '0' and RD = '1' and exists_i = '1') then
- fifo_length <= fifo_length - 1;
- end if;
- end if;
- end if;
- end process Fifo_Length_Handle;
-
- ---------------------------------------------------------------------------
- -- Need special handling for BRAM based fifo since there is one extra delay
- -- reading out data from it.
- -- We are pipelining the reading by making read_addr be one read ahead and
- -- are holding the data on the BRAM output by enabling/disabling the BRAM
- -- enable signal
- ---------------------------------------------------------------------------
- Rd_Delay_For_Bram : if (C_IMPL_STYLE /= 0) generate
- signal fall_through_data : std_logic_vector(WordSize-1 downto 0);
- signal use_fall_through : std_logic;
- begin
-
- -------------------------------------------------------------------------
- -- Need to detect when writing into an empty FIFO,
- -------------------------------------------------------------------------
- First_Write : process (Clk) is
- begin -- process First_Write
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- first_write_on_empty_fifo <= '0';
- else
- first_write_on_empty_fifo <= WE and not exists_i;
- end if;
- end if;
- end process First_Write;
-
- -------------------------------------------------------------------------
- -- Read out BRAM contents on the first word written in an empty FIFO and
- -- all other FIFO read except when the last word is read since the "real"
- -- FIFO is actually empty at this time since the last word is on the
- -- output of the BRAM
- -------------------------------------------------------------------------
- last_word <= '1' when (fifo_length = 1) else '0';
- read_bram_enable <= first_write_on_empty_fifo or (RD and (not last_word or WE));
-
- read_addr_incr <= read_bram_enable;
-
- -------------------------------------------------------------------------
- -- The exists flag is now if the BRAM output has valid data and not the
- -- content of the FIFO
- -------------------------------------------------------------------------
- FIFO_Exists_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if Reset = '1' then -- synchronous reset (active high)
- Exists <= '0';
- else
- if (first_write_on_empty_fifo = '1') then
- Exists <= '1';
- elsif ((RD = '1') and (WE = '0') and (last_word = '1')) then
- Exists <= '0';
- end if;
- end if;
- end if;
- end process FIFO_Exists_DFF;
-
- -------------------------------------------------------------------------
- -- Data output with fallthrough
- -------------------------------------------------------------------------
- use_fall_through_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if ((RD and (not WE)) = '1') or (Reset = '1') then -- synchronous reset (active high)
- use_fall_through <= '0';
- elsif (RD and not last_word) = '1' then
- use_fall_through <= '0';
- elsif (RD = '1') then
--- The equation (RD and WE and last_word) = '1' can be reduced to (RD = '1')
- use_fall_through <= '1';
- end if;
- end if;
- end process use_fall_through_DFF;
-
- fall_through_data_DFF : process (Clk) is
- begin -- process FIFO_Exists_DFF
- if Clk'event and Clk = '1' then -- rising clock edge
- if (RD and WE and last_word) = '1' then
- fall_through_data <= DataIn;
- end if;
- end if;
- end process fall_through_data_DFF;
-
- DataOut <= fall_through_data when (use_fall_through = '1') else DataOut_BRAM;
-
- end generate Rd_Delay_For_Bram;
-
- Rd_No_Delay : if (C_IMPL_STYLE = 0) generate
- read_addr_incr <= RD;
- Exists <= exists_i;
- end generate Rd_No_Delay;
-
- -- Set Full and empty flags
- full_i <= '1' when (fifo_length = MemSize) else '0';
- exists_i <= '1' when (fifo_length /= 0) else '0';
-
- Full <= full_i;
-
- -- Increment Read Address Pointer
- Read_Addr_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- read_addr_ptr <= 0;
- elsif (read_addr_incr = '1') then
- read_addr_ptr <= (read_addr_ptr + 1) mod (2 ** AddrWidth);
- end if;
- end if;
- end process Read_Addr_Handle;
-
- -- Increment Write Address Pointer
- Write_Addr_Handle : process (Clk)
- begin
- if (Clk'event and Clk = '1') then
- if (Reset = '1') then
- write_addr_ptr <= 0;
- elsif (WE = '1') then
- write_addr_ptr <= (write_addr_ptr + 1) mod (2 ** AddrWidth);
- end if;
- end if;
- end process Write_Addr_Handle;
-
- Write_Address <= std_logic_vector(to_unsigned(write_addr_ptr, AddrWidth));
- Read_Address <= std_logic_vector(to_unsigned(read_addr_ptr, AddrWidth));
-
- end generate FSL_Flag_Handle;
-
-
- Sync_FIFO_I : if (C_IMPL_STYLE = 0) generate
- srl_fifo_i : if (MemSize <= 16) generate
- FSL_FIFO : SRL_FIFO
- generic map (
- C_DATA_BITS => WordSize,
- C_DEPTH => MemSize)
- port map (
- Clk => Clk,
- Reset => Reset,
- FIFO_Write => WE, -- Master Write Signal
- Data_In => DataIn, -- Master Data
- FIFO_Read => RD, -- Slave Read Signal
- Data_Out => DataOut, -- Slave Data
- FIFO_Full => Full, -- FIFO full signal
- -- FIFO_Half_Full => open,
- -- FIFO_Half_Empty => open,
- Data_Exists => Exists); -- Slave Data exists
- end generate srl_fifo_i;
-
- dpram_fifo_i : if (MemSize > 16) generate
- DPRAM_FIFO : SYNC_DPRAM
- generic map (
- C_DWIDTH => WordSize,
- C_AWIDTH => AddrWidth)
- port map (
- clk => Clk,
- we => WE,
- a => Write_Address,
- dpra => Read_Address,
- di => DataIn,
- dpo => DataOut);
- end generate dpram_fifo_i;
-
- end generate Sync_FIFO_I;
-
- Sync_BRAM_FIFO : if (C_IMPL_STYLE /= 0) generate
- Sync_BRAM_I1 : Sync_BRAM
- generic map (
- C_DWIDTH => WordSize, -- [integer]
- C_AWIDTH => AddrWidth) -- [integer]
- port map (
- clk => Clk, -- [in std_logic]
-
- -- Write port
- we => WE, -- [in std_logic]
- a => Write_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
- di => DataIn, -- [in std_logic_vector(C_DWIDTH-1 downto 0)]
-
- -- Read port
- dpra_en => read_bram_enable, -- [in std_logic]
- dpra => Read_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
- dpo => DataOut_BRAM); -- [out std_logic_vector(C_DWIDTH-1 downto 0)]
- end generate Sync_BRAM_FIFO;
-
-end VHDL_RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/component.xml
deleted file mode 100644
index 5ef64accadbf7bc443be1cb52a38cdebf2ae5019..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/component.xml
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>common</spirit:library>
- <spirit:name>hwnode</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:xilinx.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>hwnode</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/controller.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/counter.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/it_mod.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/it_mul.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/parameters.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/read_mux.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/read_mmux.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/write_demux.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/controller.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/controller.vhd
deleted file mode 100644
index 9c232e661419837d2702374caea8658f59558351..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/controller.vhd
+++ /dev/null
@@ -1,107 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity CONTROLLER is
- generic(
- N_STAGES : natural := 1; -- number of pipeline stages or delay
- BLOCKING : natural := 0 -- '1'-block the pipeline if there is no input data
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
-
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
-
- CLK : in std_logic;
- RST : in std_logic
- );
-end CONTROLLER;
-
-architecture RTL of CONTROLLER is
-
- signal p_en : std_logic_vector(N_STAGES downto 0); -- Enable signals to the execution pipline stages
- signal blocked : std_logic; -- pipeline is blocked on Write
- signal pipe : std_logic_vector(N_STAGES downto 0); -- delay pipeline
- signal execute_pipe : std_logic_vector(N_STAGES downto 0); -- reverse signal of pipe
-
- function reverse_any_vector (a: in std_logic_vector)
- return std_logic_vector is variable result: std_logic_vector(a'RANGE);
- alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
- begin
- for i in aa'RANGE loop
- result(i) := aa(i);
- end loop;
- return result;
- end; -- function reverse_any_vector
-
-
- begin
- --
- Pipe_Fill: process( CLK, RST )
- begin
- if ( RST = '1' ) then
- pipe <= (others => '0');
- elsif ( rising_edge(CLK) ) then
- --
- BUBBLE_COMPRESS:
- for i in N_STAGES downto 1 loop
- if ( p_en(i)='1' ) then
- pipe(i) <= pipe(i-1) and not STALL_FRONT(i-1);
- end if;
- end loop;
- --
- if ( p_en(0)='1' ) then
- pipe(0) <= EXIST;
- end if;
-
- end if;
- end process Pipe_Fill;
-
- Pipe_Reverse: process(pipe, RST)
- begin
- if (RST = '1') then
- execute_pipe <= (others => '0');
- else
- execute_pipe <= reverse_any_vector(pipe);
- end if;
- end process Pipe_Reverse;
-
- --p_en(N_STAGES-1 downto 0) <= not pipe(N_STAGES-1 downto 0) or p_en(N_STAGES downto 1);
- p_en(N_STAGES-1 downto 0) <= p_en(N_STAGES downto 1) and not STALL_BACK(N_STAGES-1 downto 0);
- p_en(N_STAGES) <= not pipe(N_STAGES) or not FULL;
- --
- WRITE <= pipe(N_STAGES) and not FULL;
- READ <= EXIST and p_en(0);
- ENABLE_EX(N_STAGES-1 downto 0) <= pipe(N_STAGES-1 downto 0) and p_en(N_STAGES downto 1);
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/counter.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/counter.vhd
deleted file mode 100644
index c99fec6272cd8e9197976bf15f552a2fe43f89cf..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/counter.vhd
+++ /dev/null
@@ -1,89 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity counter is
- generic(
- C_STEP : natural := 1;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
-end counter;
-
-architecture RTL of counter is
-
- signal sl_counter : unsigned(C_WIDTH-1 downto 0);
- signal sl_register : unsigned(C_WIDTH-1 downto 0);
- signal sl_LOWER_BND : unsigned(C_WIDTH-1 downto 0);
- signal sl_UPPER_BND : unsigned(C_WIDTH-1 downto 0);
- signal sl_last_count : std_logic;
- signal sl_done : std_logic;
-
-begin
-
- ITERATOR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_counter);
- REG_CNTR(C_WIDTH-1 downto 0) <= STD_LOGIC_VECTOR(sl_register);
-
- sl_LOWER_BND <= UNSIGNED(LOWER_BND(C_WIDTH-1 downto 0));
- sl_UPPER_BND <= UNSIGNED(UPPER_BND(C_WIDTH-1 downto 0));
-
-
- sl_counter <= sl_LOWER_BND when (sl_done='1' or RST='1' or LOAD='1') else (sl_register + C_STEP);
- --sl_last_count <= '1' when (sl_counter >= sl_UPPER_BND) else '0';
- sl_last_count <= '1' when (sl_register >= sl_UPPER_BND) else '0';
- sl_done <= sl_last_count;
- --
- DONE <= sl_done;
-
- REG_PRCS : process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST='1' or LOAD ='1' ) then
- sl_register <= sl_LOWER_BND;
- --sl_done <= sl_last_count; -- special case: (sl_LOWER_BND == sl_UPPER_BND)
- elsif( ENABLE='1' ) then
- sl_register <= sl_counter;
- --sl_done <= sl_last_count;
- end if;
- end if;
- end process;
-
-end RTL;
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/it_mod.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/it_mod.vhd
deleted file mode 100644
index 1dea20fb8f3cb2c4c475f15255a204dc8804a252..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/it_mod.vhd
+++ /dev/null
@@ -1,96 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-
-entity it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
-end it_mod;
-
-architecture RTL of it_mod is
- signal sl_reg : unsigned(C_WIDTH-1 downto 0);
- signal sl_step : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_STEP,C_WIDTH);
- signal sl_init : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_INIT,C_WIDTH);
- signal sl_mod : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_MOD ,C_WIDTH);
--- signal a1 : unsigned(C_WIDTH downto 0);
--- signal a2 : unsigned(C_WIDTH downto 0);
-begin
- --
- -- Checks
- assert (2**C_WIDTH >= C_MOD)
- report "Parameter C_MOD (=" & integer'image(C_MOD) & ") bitwidth exceeds the output bitwidth (C_WIDTH=" & integer'image(C_WIDTH) & ")"
- severity ERROR;
- --
- assert (C_MOD >= C_STEP)
- report "Parameter C_STEP (=" & integer'image(C_STEP) & ") greater than parameter C_MOD (=" & integer'image(C_MOD) & ")"
- severity ERROR;
- --
- assert (C_MOD >= C_INIT)
- report "Parameter C_INIT (=" & integer'image(C_INIT) & ") greater than parameter C_MOD (=" & integer'image(C_MOD) & ")"
- severity ERROR;
-
-
- --
- REG_PRCS : process(CLK, RST)
- variable a1 : unsigned(C_WIDTH downto 0);
- variable a2 : signed(C_WIDTH downto 0);
- begin
- if rising_edge(CLK) then
- --if( RST='1' or LOAD='1') then
- if( RST='1' ) then
- sl_reg <= sl_init;
- elsif( ENABLE='1' ) then
- a1 := ("0"&sl_reg) + ("0"&sl_step);
- a2 := SIGNED(a1) - SIGNED("0"&sl_mod);
- if ( LOAD='1' ) then
- sl_reg <= sl_init;
- elsif (a2(a2'High)='1') then
- sl_reg <= a1(C_WIDTH-1 downto 0);
- else
- sl_reg <= UNSIGNED(a2(C_WIDTH-1 downto 0));
- end if;
- end if;
- end if;
- end process;
- --
- MODULE <= STD_LOGIC_VECTOR(sl_reg);
- --
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/it_mul.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/it_mul.vhd
deleted file mode 100644
index ad9e36ed3c5057843490d51f41155f9a2b106726..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/it_mul.vhd
+++ /dev/null
@@ -1,80 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-
-entity it_mul is
- generic(
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MUL : out std_logic_vector(C_WIDTH-1 downto 0)
- );
-end it_mul;
-
-architecture RTL of it_mul is
- signal sl_counter : unsigned(C_WIDTH-1 downto 0);
- signal sl_step : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_STEP,C_WIDTH);
- signal sl_init : unsigned(C_WIDTH-1 downto 0) := TO_UNSIGNED(C_INIT,C_WIDTH);
-begin
- --
- -- Checks
- assert (2**C_WIDTH > C_INIT)
- report "Parameter C_INIT (=" & integer'image(C_INIT) & ") bitwidth exceeds the output bitwidth (C_WIDTH=" & integer'image(C_WIDTH) & ")"
- severity ERROR;
- --
- assert (2**C_WIDTH > C_STEP)
- report "Parameter C_STEP (=" & integer'image(C_STEP) & ") bitwidth exceeds the output bitwidth (C_WIDTH=" & integer'image(C_WIDTH) & ")"
- severity ERROR;
- --
- REG_PRCS : process(CLK, RST)
- begin
- if rising_edge(CLK) then
- --if( RST='1' or LOAD='1') then
- if( RST='1' ) then
- sl_counter <= sl_init;
- elsif( ENABLE='1' ) then
- if ( LOAD='1') then
- sl_counter <= sl_init;
- else
- sl_counter <= sl_counter + sl_step;
- end if;
- end if;
- end if;
- end process;
- --
- MUL <= STD_LOGIC_VECTOR(sl_counter);
- --
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/parameters.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/parameters.vhd
deleted file mode 100644
index a24600241a345c4e6031f9d3ee35778523a1fdb4..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/parameters.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity parameters is
- generic (
- PAR_WIDTH : natural;
- PAR_BITWIDTH : natural;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural := 0;
- N_SYNC_OUT : natural := 0;
- N_PAR : natural
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0) := (others => '0');
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
- PARAMETERS : out std_logic_vector(PAR_BITWIDTH-1 downto 0)
- );
-end parameters;
-
-architecture RTL of parameters is
-
- --constant N_PAR : natural := PAR_VECTOR'Length-2; -- The last two elements in PAR_VECTOR are always a dummy component
- -- we will always read all the paramerets in parallel
- --constant N_PAR : natural := 1;
-
- signal sl_tmp_parameters : std_logic_vector(N_PAR*PAR_WIDTH-1 downto 0);
- signal sl_update : std_logic;
- signal sl_halt : std_logic;
- signal sl_sof : std_logic;
- signal sl_det_0, sl_det_1, sl_PARAM_LD : std_logic;
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- type state_type is (s_idle, s_update_rd, s_update_wr);
- signal state : state_type;
-
- signal delay_cnt : integer;
-
- type sic is array (N_SYNC_IN downto 0) of natural;
- signal sync_in_cnt : sic;
- signal sync_in_f : std_logic_vector(N_SYNC_IN downto 0);
- signal sync_in_a : std_logic;
- signal sync_in_o : std_logic;
-
-signal switch_p : std_logic;
-
-begin
-
- GenLabel1 : if N_PAR > 0 generate
-
- PENDING_RD <= sl_pending_rd;
- PENDING_WR <= sl_pending_wr;
- sl_update_ack_rd <= UPDATE_ACK_RD;
- sl_update_ack_wr <= UPDATE_ACK_WR;
-
- GenLabelSo : if N_SYNC_OUT > 0 generate
- sync_out_prcss : process(CLK)
- begin
- if rising_edge( CLK ) then
- for i in 0 to N_SYNC_OUT loop
- SYNC_OUT(i) <= sl_update;
- end loop;
- end if;
- end process;
- end generate; -- GenLabelSo
-
- GenLabelSi1 : if N_SYNC_IN = 1 generate
- sync_in_a <= SYNC_IN(0);
- end generate; -- GenLabelSi
-
- GenLabelSi2 : if N_SYNC_IN = 2 generate
- sync_in_a <= SYNC_IN(0) or SYNC_IN(1);
- end generate; -- GenLabelSi
-
-
- HALT <= sl_update;
- sl_sof <= HALTED;
-
- -- Rising_edge detection of PARAM_LD signal --------------------
- Edge_det_prcss : process(CLK)
- begin
- if falling_edge( CLK ) then
- sl_det_0 <= PARAM_LD;
- sl_det_1 <= sl_det_0;
- end if;
- end process;
-
- sl_PARAM_LD <= sl_det_0 and not(sl_det_1);
-
- -- Update the parameters (from the temp buffer) ----------------
-
- FSM : process(CLK, RST)
- begin
- if rising_edge(CLK) then
- if( RST='1' ) then
- state <= s_idle;
- PARAMETERS(PAR_BITWIDTH-1 downto 0) <= STD_LOGIC_VECTOR(to_signed(10,PAR_BITWIDTH));
- sl_pending_rd <= '0';
- sl_pending_wr <= '0';
- switch_p <= '0';
- else
- case (state) is
- when s_idle =>
- if (sync_in_a ='1' and N_SYNC_IN > 0) then
- PARAMETERS(PAR_BITWIDTH-1 downto 0) <= PARAM_DT;
- sl_pending_rd <= '1';
- state <= s_update_rd;
- end if;
- when s_update_rd =>
- if(sl_update_ack_rd = '1') then
- sl_pending_rd <= '0';
- sl_pending_wr <= '1';
- state <= s_update_wr;
- end if;
- when s_update_wr =>
- if(sl_update_ack_wr = '1') then
- sl_pending_wr <= '0';
- state <= s_idle;
- end if;
- when others => state <= s_idle;
- end case;
- end if;
- end if;
- end process;
-
- end generate; -- GenLabel1
-
-end RTL;
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/read_mmux.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/read_mmux.vhd
deleted file mode 100644
index 92a72cb2bc4475251cb86decac16e37b16aa75e3..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/read_mmux.vhd
+++ /dev/null
@@ -1,288 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_fifo_1;
-use compaandesign_com_common_fifo_1.all;
-
-entity read_mmux is
- generic(
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32;
- C_IMPL_STYLE : integer := 0;
- C_FSL_DWIDTH : natural := 32;
- C_FSL_DEPTH : natural := 64
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
- CLK : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
-
- RST : in std_logic;
- OBTAIN_OOMX : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE_OOMX : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end read_mmux;
-
-architecture RTL of read_mmux is
-
-signal fsl_m_control : std_logic;
-signal fsl_m_clk : std_logic;
-signal fsl_write : std_logic;
-signal fsl_data_write : std_logic_vector(0 to C_FSL_DWIDTH-1);
-signal fsl_m_full : std_logic;
-signal fsl_read : std_logic;
-signal fsl_data_read : std_logic_vector(0 to C_FSL_DWIDTH-1);
-signal fsl_s_clk : std_logic;
-signal fsl_s_control : std_logic;
-signal fsl_s_exists : std_logic;
-
-signal sl_read : std_logic;
-signal sl_exist : std_logic;
- signal sl_avail : std_logic;
-
-component fsl_v20 is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic
- );
-end component fsl_v20;
-
-
-
-begin
-
- -- REUSE_READ => OBTAIN
- -- REUSE => RELEASE
-
- EXIST <= READ_EN and sl_exist;
- sl_read <= READ_EN and READ;
- READ_ST <= (sl_read and sl_exist) or (sl_avail);
-
- DEMUX_GEN : for i in 0 to N_PORTS-1 generate
- READS(i) <= EXISTS(i) and CONTROL(i) and sl_read and OBTAIN_OOMX(i);
- fsl_read <= not OBTAIN_OOMX(i) and (sl_read );
- fsl_write <= not RELEASE_OOMX(i) and (sl_read );
- end generate;
-
- MUX_PRCSS : process(CONTROL, RELEASE_OOMX, OBTAIN_OOMX, IN_PORTS, fsl_data_read)
- begin
- OUT_PORT <= (others=>'0');
- -- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
-
- -- Extra check giving feedback that sizing FIFO is very tight or too small
- assert fsl_m_full = '0'
- report "Internal FIFO is FULL!!!"
- severity WARNING;
-
- for i in 0 to N_PORTS-1 loop
-
- -- If control is high, we need data
- if( CONTROL(i) = '1' ) then
-
- -- peek (take the token fron the fsl and send it to the output and back to fsl)
- -- obtained is hoog, en release hoog
- -- Should not happen
- if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '1') then
-
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- --assert false
- -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
- -- severity FAILURE;
-
- sl_avail <= '0';
- -- sl_exist <= EXISTS(i);
-
- --OUT_PORT <= fsl_data_read;
- --fsl_data_write <= fsl_data_read;
- end if;
-
- -- peek last (read from the fifo without rewriting to the fsl)
- -- obtained is hoog, en release laag
- -- Read from external FIFO and store locally.
- if( OBTAIN_OOMX(i) = '1' and RELEASE_OOMX(i) = '0') then
-
- -- read from outside and forward
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
-
- -- and put a copy in the local FIFO
- fsl_data_write <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
-
- sl_avail <= '0';
- -- sl_exist <= EXISTS(i);
-
- --OUT_PORT <= fsl_data_read;
- --fsl_data_write <= fsl_data_read;
- end if;
-
- -- take first (take the first token from te input and store it to the fsl)
- -- obtained is laag, en release hoog
-
- if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '1') then
-
- -- read from the internal FIFO, and let the FIFO run empty
- OUT_PORT <= fsl_data_read;
- sl_avail <= '1';
- -- sl_exist <= '1' ;
-
- end if;
-
- --take (take from the input and wirte to the output)
- -- obtained is laag, en release laag
- if( OBTAIN_OOMX(i) = '0' and RELEASE_OOMX(i) = '0') then
-
- -- steady state...
- -- read from internal FIFO
- OUT_PORT <= fsl_data_read;
-
- -- and put the value back in the FIFO
- fsl_data_write <= fsl_data_read;
-
- sl_avail <= '1';
- -- sl_exist <= '1';
-
- end if;
- end if;
-
- end loop;
- end process;
-
-
- MUX_EXIST : process(EXISTS, OBTAIN_OOMX, CONTROL)
- begin
- -- The default value needs to be '1'. See the node's top-level: sl_exist <= sl_exist_1 and sl_exist_0;
- --EXIST <= '0';
- -- sl_exist <= '0';
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1' ) then
- --EXIST <= EXISTS(i);
- sl_exist <= (EXISTS(i) and OBTAIN_OOMX(i)) or (not OBTAIN_OOMX(i));
-
- -- Problem hier is dat EXISTS door FIFO wordt gestuurd. Dus in interne FIFO, moet deze hoog worden, ongeacht wat externe FIFO zegt...
- -- sl_exist <= '1' when ((EXISTS(i)='1' and (REUSE_READ(i) = '1')) or (REUSE_READ(i)='0')) else '0';
-
-
- end if;
- end loop;
- end process;
-
-
- -- Checks
- process(CONTROL)
- variable c : integer;
- begin
- c := 0;
- for i in 0 to CONTROL'Length-1 loop
- if (CONTROL(i)='1') then
- c := c + 1;
- end if;
- end loop;
- assert (c <= 1)
- report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
- severity ERROR;
- end process;
-
-
- fsl_m_control <= '0';
- fsl_m_clk <= '0';
- fsl_s_clk <= '0';
- fsl_s_control <= '0';
-
- fsl_cirular : fsl_v20
- generic map (
- C_EXT_RESET_HIGH => 1,
- C_ASYNC_CLKS =>0,
- C_USE_CONTROL => 1,
- C_IMPL_STYLE => C_IMPL_STYLE,
- C_FSL_DWIDTH => C_FSL_DWIDTH,
- C_FSL_DEPTH => C_FSL_DEPTH
- )
- port map (
- -- Clock and reset signals
- FSL_Clk => CLK,
- SYS_Rst => RST,
- FSL_Rst => open,
- -- FSL master signals
- FSL_M_Clk => fsl_m_clk,
- FSL_M_Data => fsl_data_write,
- FSL_M_Control => fsl_m_control,
- FSL_M_Write => fsl_write,
- FSL_M_Full => fsl_m_full,
- -- FSL slave signals
- FSL_S_Clk => fsl_s_clk,
- FSL_S_Data => fsl_data_read,
- FSL_S_Control => fsl_s_control,
- FSL_S_Read => fsl_read,
- FSL_S_Exists => fsl_s_exists,
- -- FIFO status signals
- FSL_Full => open,
- FSL_Has_Data => open
- );
-
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/read_mux.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/read_mux.vhd
deleted file mode 100644
index 266ea323d4c5706496f5419cfed887b5035a94bc..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/read_mux.vhd
+++ /dev/null
@@ -1,128 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity read_mux is
- generic(
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- --CLK : in std_logic;
-
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end read_mux;
-
-architecture RTL of read_mux is
- signal sl_read : std_logic;
- signal sl_exist : std_logic;
- signal TMP : std_logic_vector(PORT_WIDTH-1 downto 0);
-begin
- EXIST <= READ_EN and sl_exist;
- sl_read <= READ_EN and READ;
- READ_ST <= sl_read and sl_exist;
-
- DEMUX_GEN : for i in 0 to N_PORTS-1 generate
- --
- -- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read and (not SOFS(i) or SOF);
- -- The Reorder work showed problems as a result of SOFS signal. For now switched off until
- -- its use becomes clear again. BK 31mar14
- --
- READS(i) <= EXISTS(i) and CONTROL(i) and RELEASE(i) and sl_read;
- end generate;
-
- MUX_DATA : process(CONTROL, IN_PORTS, OBTAIN, RELEASE, TMP)
- begin
- OUT_PORT <= IN_PORTS(PORT_WIDTH-1 downto 0);
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1') then
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '0') then
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- TMP <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH); -- keep a copy of the value
- end if ;
-
- if( OBTAIN(i) = '0' and RELEASE(i) = '0') then
- OUT_PORT <= TMP;
- end if ;
-
- if( OBTAIN(i) = '0' and RELEASE(i) = '1') then
- OUT_PORT <= TMP;
- end if ;
-
- if( OBTAIN(i) = '1' and RELEASE(i) = '1') then
- --assert false
- -- report "Phase in which OBTAIN and RELEASE are both 1 should never be reached"
- -- severity WARNING;
- OUT_PORT <= IN_PORTS((i+1)*PORT_WIDTH-1 downto (i)*PORT_WIDTH);
- end if ;
- end if;
- end loop;
- end process;
-
- MUX_EXIST : process(EXISTS, READ, CONTROL)
- begin
- sl_exist <= '0';
- for i in 0 to N_PORTS-1 loop
- if( CONTROL(i) = '1' ) then
- sl_exist <= EXISTS(i);
- end if;
- end loop;
- end process;
-
-
- -- Checks. For simulation only
- process(CONTROL)
- variable c : integer;
- begin
- c := 0;
- for i in 0 to CONTROL'Length-1 loop
- if (CONTROL(i)='1') then
- c := c + 1;
- end if;
- end loop;
- assert (c <= 1)
- report "Signal CONTROL contains more than one bit that is set to '1' ! The CONTROL signal must be one-hot encoded. "
- severity ERROR;
- end process;
-
-end RTL;
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/write_demux.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/write_demux.vhd
deleted file mode 100644
index dc27a86a1572bed45fda1d1dbccca5722ef98d2b..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/hwnode/1/hdlsrc/write_demux.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
- -- COPYRIGHT NOTICE (NOT TO BE REMOVED):
- --
- -- This file, or parts of it, or modified versions of it, may not be
- -- copied, reproduced or transmitted in any form, including
- -- reprinting, translation, photocopying or microfilming, or by any
- -- means, electronic, mechanical or otherwise, or stored in a
- -- retrieval system, or used for any purpose, without the prior
- -- written permission of all Owners unless it is explicitly marked as
- -- having Classification `Public'.
- --
- -- Classification: Restricted.
- --
- -- Owners of this file give notice:
- -- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
- -- All rights, including copyrights, reserved.
- --
- -- This file contains or may contain restricted information and is
- -- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
- -- Notice(s) above do not evidence any actual or intended publication
- -- of such source code. This file is additionally subject to the
- -- conditions listed in the RESTRICTIONS file and is with NO WARRANTY.
- --
- -- END OF COPYRIGHT NOTICE
- --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity write_demux is
- generic(
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
-
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
-end write_demux;
-
-
-architecture RTL of write_demux is
-
- signal sl_full : std_logic;
- signal sl_write : std_logic;
-
-begin
- --
- GEN : for i in 0 to N_PORTS-1 generate
- WRITES(i) <= CONTROL(i) and sl_write;
- end generate;
- --
- process(CONTROL,FULLS)
- variable a : std_logic;
- variable b : std_logic;
- begin
- a := '0';
- for i in 0 to N_PORTS-1 loop
- a := a or ( CONTROL(i) and FULLS(i) );
- end loop;
- sl_full <= a;
- end process;
- --
- sl_write <= WRITE_EN and WRITE;
- FULL <= (not WRITE_EN) or sl_full;
- WRITE_ST <= not sl_full and sl_write;
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/wire_connector/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/wire_connector/1/component.xml
deleted file mode 100644
index 14fcb485fefdbb2f962d9f243cb73b759ce8b6bd..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/wire_connector/1/component.xml
+++ /dev/null
@@ -1,83 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>common</spirit:library>
- <spirit:name>wire_connector</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:xilinx.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>wire_connector</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>FSL_S</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>FSL_M</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:resolve="generated">C_FSL_DWIDTH</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>RESET_HIGH</spirit:name>
- <spirit:value>0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>C_FSL_DWIDTH</spirit:name>
- <spirit:value>31</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/wire_connector.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/wire_connector/1/hdlsrc/wire_connector.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/wire_connector/1/hdlsrc/wire_connector.vhd
deleted file mode 100644
index 7e2ea3d072eb2e0c7d7d65bd85e9ab25d5c499e7..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/common/wire_connector/1/hdlsrc/wire_connector.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--- COPYRIGHT NOTICE (NOT TO BE REMOVED):
---
--- This file, or parts of it, or modified versions of it, may not be
--- copied, reproduced or transmitted in any form, including
--- reprinting, translation, photocopying or microfilming, or by any
--- means, electronic, mechanical or otherwise, or stored in a
--- retrieval system, or used for any purpose, without the prior
--- written permission of all Owners unless it is explicitly marked as
--- having Classification `Public'.
---
--- Classification: Restricted.
---
--- Owners of this file give notice:
--- (c) Copyright 2005 - 2009 Compaan Design bv, The Netherlands
--- All rights, including copyrights, reserved.
---
--- This file contains or may contain restricted information and is
--- UNPUBLISHED PROPRIETARY SOURCE CODE OF THE Owners. The Copyright
--- Notice(s) above do not evidence any actual or intended publication
--- of such source code. This file is additionally subject to the
--- conditions listed in the RESTRICTIONS file and is with NOWARRANTY.
---
--- END OF COPYRIGHT NOTICE
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity wire_connector is
- generic (
- C_EXT_RESET_HIGH : integer := 1;
- C_ASYNC_CLKS : integer := 0;
- C_IMPL_STYLE : integer := 0;
- C_USE_CONTROL : integer := 1;
- C_FSL_DWIDTH : integer := 32;
- C_FSL_DEPTH : integer := 16;
- C_READ_CLOCK_PERIOD : integer := 0
- );
- port (
- -- Clock and reset signals
- FSL_Clk : in std_logic;
- SYS_Rst : in std_logic;
- FSL_Rst : out std_logic;
-
- -- FSL master signals
- FSL_M_Clk : in std_logic;
- FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_M_Control : in std_logic;
- FSL_M_Write : in std_logic;
- FSL_M_Full : out std_logic;
-
- -- FSL slave signals
- FSL_S_Clk : in std_logic;
- FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
- FSL_S_Control : out std_logic;
- FSL_S_Read : in std_logic;
- FSL_S_Exists : out std_logic;
-
- -- FIFO status signals
- FSL_Full : out std_logic;
- FSL_Has_Data : out std_logic;
- FSL_Control_IRQ : out std_logic
- );
-end wire_connector;
-
-architecture STRUCTURE of wire_connector is
-
- signal ready : std_logic;
-
-begin
-
- ready <= FSL_M_Write ;
- FSL_S_Exists <= ready;
- FSL_S_Control <= FSL_M_Control;
- FSL_S_Data <= FSL_M_Data;
-
-end architecture STRUCTURE;
\ No newline at end of file
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/control_if/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/control_if/1/component.xml
deleted file mode 100644
index d12847655076e8b3fe51ac9f42dafd6dcb50820a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/control_if/1/component.xml
+++ /dev/null
@@ -1,90 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>control_if</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:compaandesign.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>control_if</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>PARAM_DT</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAM_LD</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAMETERS_IN</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAMETERS_IN_LD</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>RESET_HIGH</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>QUANT</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/control_if.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
- <spirit:description>This node implements the control interface when involving synchronized parameters</spirit:description>
-</spirit:component>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/control_if/1/hdlsrc/control_if.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/control_if/1/hdlsrc/control_if.vhd
deleted file mode 100644
index 835eeb33924d907a5994a3b90b565d0974705fe2..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/control_if/1/hdlsrc/control_if.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
--- File automatically generated by KpnMapper
--- For control_if
-
-library ieee;
-use ieee.std_logic_1164.all;
-
---
--- ============================================
--- = PAMETER CONTROLLER =
--- ============================================
---
-
-entity control_if is
- generic (
- RESET_HIGH : natural := 1;
- QUANT : natural := 32
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAM_LD : out std_logic;
- PARAM_DT : out std_logic_vector((QUANT-1) downto 0);
- --
- PARAMETERS_IN_LD : in std_logic;
- PARAMETERS_IN : in std_logic_vector((QUANT-1) downto 0)
-
- );
-end control_if;
-
-architecture fsl_test of control_if is
-
- signal sl_RST : std_logic;
- signal sl_load : std_logic;
- signal sl_data : std_logic_vector((QUANT-1) downto 0);
-
-begin
-
- sl_RST <= RST when (RESET_HIGH=1) else not RST;
-
- process(CLK)
- begin
- if (rising_edge(CLK)) then
- if (sl_RST='1') then
- sl_load <= '0';
- sl_data <= (others=>'0');
- else
- if (sl_load = '1') then
- sl_load <= '0';
- else
- if (PARAMETERS_IN_LD='1') then
- sl_load <= '1';
- sl_data <= PARAMETERS_IN((QUANT-1) downto 0);
- end if;
- end if;
- end if;
- end if;
- end process;
-
- PARAM_LD <= sl_load;
- PARAM_DT <= sl_DATA;
-
-end architecture fsl_test;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/functions/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/functions/1/component.xml
deleted file mode 100644
index 444202a694993fd0c99826e543e29d1d3a0c96e9..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/functions/1/component.xml
+++ /dev/null
@@ -1,41 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>functions</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:compaandesign.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>functions</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- </spirit:fileSet>
- </spirit:fileSets>
-</spirit:component>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/component.xml
deleted file mode 100644
index 066cc5f32bd1abbc540178767bb27d48e4c83406..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/component.xml
+++ /dev/null
@@ -1,163 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>hwn_nd_1</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:compaandesign.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>ND_1</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>data_in</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- <spirit:description>Port is connected to link </spirit:description>
- </spirit:port>
- <spirit:port>
- <spirit:name>ND_1OP_1</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ND_1OP_1_d1</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAM_DT</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAM_LD</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>STOP</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ERROR</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>BLOCK_RD</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>RESET_HIGH</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>PAR_WIDTH</spirit:name>
- <spirit:value>16</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>QUANT</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="BOOLEAN">
- <spirit:name>WRAP</spirit:name>
- <spirit:value>true</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_1_execution_unit.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_1.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/hwn_nd_1_compaan_outlinedproc0.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
- <spirit:description>This node implements function compaan_outlinedproc0</spirit:description>
- <spirit:parameters>
- <spirit:parameter name="data_in">STIM_hwn_nd_1_tmp1</spirit:parameter>
- </spirit:parameters>
-</spirit:component>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp0.txt b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp0.txt
deleted file mode 100644
index 1f993000487386975f7f2ac4126b8593c1ee65a2..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp0.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-101
-206
-161
-91
-145
-222
-230
-204
-11
-98
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp1.txt b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp1.txt
deleted file mode 100644
index 74cc835bc385584973d0b7d7b5c9ec5eea80538c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/STIM_hwn_nd_1_tmp1.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-1
-1
-1
-1
-1
-1
-1
-1
-1
-1
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/hwn_nd_1_compaan_outlinedproc0.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/hwn_nd_1_compaan_outlinedproc0.vhd
deleted file mode 100644
index e771cad6c5997fb71af85381f7b58d2250401cae..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/hwn_nd_1_compaan_outlinedproc0.vhd
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-
-entity hwn_nd_1_compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end hwn_nd_1_compaan_outlinedproc0;
-
-architecture RTL of hwn_nd_1_compaan_outlinedproc0 is
-
- component hwn_nd_1_compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : hwn_nd_1_compaan_outlinedproc0_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_i => it_i,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd
deleted file mode 100644
index 74462c10597147f304dd60ccb4a19240411f5fdf..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/hwn_nd_1_compaan_outlinedproc0_pipeline.vhd
+++ /dev/null
@@ -1,152 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines an TEST implementation of a
--- function Test pipeline (containig file traces)
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library std;
-use std.textio.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity hwn_nd_1_compaan_outlinedproc0_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end hwn_nd_1_compaan_outlinedproc0_pipeline;
-
-architecture RTL of hwn_nd_1_compaan_outlinedproc0_pipeline is
-
- type type_err_array is array(natural range<>) of boolean;
- --
- constant error_int : integer := -1;
- constant reset_int : integer := 0;
- --
- -- Path to the stimuli directory
- constant STIM_DIR : string := "C:\Users\kienhuis\Documents\workspace\ipcore_trace\.\ipxact\compaandesign.com\ipcore2RTL\hwn_nd_1\1\hdlsrc/";
- -- Stimuli file for input "tmp1"
- constant STIM_FILE_tmp1 : string := "STIM_hwn_nd_1_tmp1.txt";
- -- Stimuli file for output "tmp0"
- constant STIM_FILE_tmp0 : string := "STIM_hwn_nd_1_tmp0.txt";
- --
- -- Function that reads stimuli from a text file
- impure function FREAD_STIM(file F : TEXT) return INTEGER is
- variable X : INTEGER;
- variable IN_LINE : LINE;
- begin
- if (endfile(F)) then
- return error_int;
- else
- readline(F ,IN_LINE);
- read(IN_LINE, X);
- deallocate(IN_LINE);
- return X;
- end if;
- return error_int;
- end;
- --
- signal cntr_i : integer := 0;
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
- signal ipr_tmp1_ref : std_logic_vector(31 downto 0);
- -- Iterator registers
- signal itr_i : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Output registers
- signal opr2_tmp0 : std_logic_vector(31 downto 0);
- signal s2_tmp0 : integer;
- -- Ppipeline signals
- signal error_pipe : type_err_array(2 downto 0);
- signal ee : boolean;
-
-begin
-
- PIPE_REGS : process(CLK)
- file STIM_tmp1 : TEXT open READ_MODE is STIM_DIR&STIM_FILE_tmp1;
- file STIM_tmp0 : TEXT open READ_MODE is STIM_DIR&STIM_FILE_tmp0;
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- cntr_i <= 0;
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- ipr_tmp1_ref <= STD_LOGIC_VECTOR(TO_SIGNED(FREAD_STIM(STIM_tmp1),32));
- -- Iterator Registers
- itr_i <= it_i;
- --
- cntr_i <= cntr_i + 1;
- end if;
- -- Pipeline Depth: 3 stages
- -- The min. depth of a test pipeline is 2 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- error_pipe(0) <= ee;
- end if;
- -- STAGE_1
- if( EN(1) = '1' ) then
- error_pipe(1) <= error_pipe(0);
- end if;
- -- STAGE_2
- if( EN(2) = '1' ) then
- if(error_pipe(1)) then
- opr2_tmp0 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int,32));
- else
- opr2_tmp0 <= STD_LOGIC_VECTOR(TO_SIGNED(FREAD_STIM(STIM_tmp0),32));
- end if;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= opr2_tmp0;
- --
- -- PIPE_COMB:
- ee <= false
- or (ipr_tmp1 /= ipr_tmp1_ref);
- --
- process(CLK)
- begin
-
- assert ee = false
- report "ERROR IN PIPELINE hwn_nd_1_compaan_outlinedproc0_pipeline of ipcore OCCURED at " & integer'image(cntr_i)
- severity FAILURE;
-
- if (rising_edge(CLK)) then
- if (RST='1') then
- ERROR <= '0';
- elsif (ee) then
- ERROR <= '1';
- end if;
- end if;
- end process;
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1.vhd
deleted file mode 100644
index 6077a5e25ca9b336dd6eb6673919ee45db75c773..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1.vhd
+++ /dev/null
@@ -1,505 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-entity ipcore2RTL_hwn_nd_1 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- data_in_Rd : out std_logic;
- data_in_Din : in std_logic_vector(31 downto 0);
- data_in_Exist : in std_logic;
- data_in_CLK : out std_logic;
- data_in_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_2 : out_0
- ND_1OP_1_Wr : out std_logic;
- ND_1OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_Full : in std_logic;
- ND_1OP_1_CLK : out std_logic;
- ND_1OP_1_CTRL : out std_logic;
-
- -- ED_4 : out_0
- ND_1OP_1_d1_Wr : out std_logic;
- ND_1OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_1OP_1_d1_Full : in std_logic;
- ND_1OP_1_d1_CLK : out std_logic;
- ND_1OP_1_d1_CTRL : out std_logic;
-
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_hwn_nd_1 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 1; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 2; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 3; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := false; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural:=1;
- N_SYNC_OUT : natural:=1;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0);
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
-
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(1*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- signal s_in : std_logic_vector(0 downto 0);
- signal s_out : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- data_in_CLK <= CLK;
- ND_1OP_1_CLK <= CLK;
- ND_1OP_1_d1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 1,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(0 downto 0),
- READS => sl_READS(0 downto 0),
- SOFS => sl_CTRLS(0 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(0 downto 0),
- OBTAIN => sl_obtain_rd(0 downto 0),
- RELEASE => sl_release_rd(0 downto 0)
- );
-
- data_in_Rd <= sl_READS(0);
-
- sl_IN_PORTS_0 <= data_in_Din;
-
- sl_EXISTS(0) <= data_in_Exist ;
- sl_CTRLS(0) <= data_in_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- PENDING => sl_pending_rd,
- UPDATE_ACK => sl_update_ack_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 2
- )
- port map (
- WRITES => sl_WRITES(1 downto 0),
- FULLS => sl_FULLS(1 downto 0),
- CONTROL => sl_lortnoc_wr(1 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_1OP_1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- ND_1OP_1_CTRL <= sl_sof_wr ;
- ND_1OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_1OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- ND_1OP_1_d1_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- ND_1OP_1_d1_CTRL <= sl_sof_wr ;
- ND_1OP_1_d1_Wr <= sl_WRITES(1);
- sl_FULLS(1) <= ND_1OP_1_d1_Full;
- sl_lortnoc_wr(1) <= sl_control_wr(1);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- PENDING => sl_pending_wr,
- UPDATE_ACK => sl_update_ack_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_1
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_SYNC_IN => 0,
- N_SYNC_OUT => 0,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- SYNC_IN => s_in,
- SYNC_OUT => s_out,
- PENDING_RD => sl_pending_rd,
- PENDING_WR => sl_pending_wr,
- UPDATE_ACK_RD => sl_update_ack_rd,
- UPDATE_ACK_WR => sl_update_ack_wr,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
deleted file mode 100644
index e9f0a6844dec3c0d357315451bd7776bcc28f38d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
+++ /dev/null
@@ -1,274 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- alias load_i : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "data_in[i]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
-
- sl_loop_i <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_i_rg>=0;
- e1 <= -sl_loop_i_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port in_1 : EXTERNAL
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "data_in[i]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
deleted file mode 100644
index c45a3b8394e5f605946844893eedb2090251896f..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_eval_logic_wr.vhd
+++ /dev/null
@@ -1,266 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_1 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "out_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_i, sl_high_i : integer;
- signal sl_loop_i, sl_loop_i_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_i : std_logic is sl_cntr_en(0);
- --
- alias load_i : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_i : std_logic;
-
- signal e0 : boolean;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments (WRITE)
-
- sl_loop_i <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_i_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_i <= 0;
- sl_high_i <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_i,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_i,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= sl_loop_i_rg=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : ED_2
- sl_CONTROL(0) <= sl_fire and b2std((e0));
-
- -- Convert FIFO Write Port out_2 : ED_4
- sl_CONTROL(1) <= sl_fire and b2std((e0));
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "out_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_execution_unit.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_execution_unit.vhd
deleted file mode 100644
index 85ed335da630440acddb930720ff8d63c0bcb17d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_1/1/hdlsrc/ipcore2RTL_hwn_nd_1_execution_unit.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc0"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_1 is
-
- component hwn_nd_1_compaan_outlinedproc0 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_i : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : hwn_nd_1_compaan_outlinedproc0
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_i => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/component.xml
deleted file mode 100644
index 089ff7b2220e230e5d9242400fa1f0551b7c23a7..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/component.xml
+++ /dev/null
@@ -1,176 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>hwn_nd_2</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:compaandesign.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>ND_2</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>ND_2IP_1</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- <spirit:description>Port is connected to link BUS_ED_1</spirit:description>
- </spirit:port>
- <spirit:port>
- <spirit:name>ND_2IP_2</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- <spirit:description>Port is connected to link BUS_ED_2</spirit:description>
- </spirit:port>
- <spirit:port>
- <spirit:name>ND_2OP_1</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ND_2OP_1_d1</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAM_DT</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAM_LD</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>STOP</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ERROR</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>BLOCK_RD</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>RESET_HIGH</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>PAR_WIDTH</spirit:name>
- <spirit:value>16</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>QUANT</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="BOOLEAN">
- <spirit:name>WRAP</spirit:name>
- <spirit:value>true</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_2_execution_unit.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_2.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/hwn_nd_2_transformer.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/hwn_nd_2_transformer_pipeline.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
- <spirit:description>This node implements function transformer</spirit:description>
- <spirit:parameters>
- </spirit:parameters>
-</spirit:component>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/STIM_hwn_nd_2_a.txt b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/STIM_hwn_nd_2_a.txt
deleted file mode 100644
index eb4bc455d0b7361e61074ab5ed7c98a9d3c2de14..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/STIM_hwn_nd_2_a.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-101
-48
-209
-27
-177
-104
-183
-4
-177
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/STIM_hwn_nd_2_b.txt b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/STIM_hwn_nd_2_b.txt
deleted file mode 100644
index 9a7c031a53a73fbdb80b89a31c21277ec44ac699..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/STIM_hwn_nd_2_b.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-48
-209
-27
-177
-104
-183
-4
-177
-201
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/hwn_nd_2_transformer.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/hwn_nd_2_transformer.vhd
deleted file mode 100644
index 747da93faabd459a1efd37430710f632e55def5b..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/hwn_nd_2_transformer.vhd
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-
-entity hwn_nd_2_transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end hwn_nd_2_transformer;
-
-architecture RTL of hwn_nd_2_transformer is
-
- component hwn_nd_2_transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : hwn_nd_2_transformer_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_a => ip_a,
- -- Iterators
- it_j => it_j,
- -- Outputs
- op_b => op_b,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/hwn_nd_2_transformer_pipeline.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/hwn_nd_2_transformer_pipeline.vhd
deleted file mode 100644
index ce8773aee96ea8a90edf26cc32d7ad6a96a50eff..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/hwn_nd_2_transformer_pipeline.vhd
+++ /dev/null
@@ -1,152 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines an TEST implementation of a
--- function Test pipeline (containig file traces)
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library std;
-use std.textio.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity hwn_nd_2_transformer_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end hwn_nd_2_transformer_pipeline;
-
-architecture RTL of hwn_nd_2_transformer_pipeline is
-
- type type_err_array is array(natural range<>) of boolean;
- --
- constant error_int : integer := -1;
- constant reset_int : integer := 0;
- --
- -- Path to the stimuli directory
- constant STIM_DIR : string := "C:\Users\kienhuis\Documents\workspace\ipcore_trace\.\ipxact\compaandesign.com\ipcore2RTL\hwn_nd_2\1\hdlsrc/";
- -- Stimuli file for input "a"
- constant STIM_FILE_a : string := "STIM_hwn_nd_2_a.txt";
- -- Stimuli file for output "b"
- constant STIM_FILE_b : string := "STIM_hwn_nd_2_b.txt";
- --
- -- Function that reads stimuli from a text file
- impure function FREAD_STIM(file F : TEXT) return INTEGER is
- variable X : INTEGER;
- variable IN_LINE : LINE;
- begin
- if (endfile(F)) then
- return error_int;
- else
- readline(F ,IN_LINE);
- read(IN_LINE, X);
- deallocate(IN_LINE);
- return X;
- end if;
- return error_int;
- end;
- --
- signal cntr_i : integer := 0;
- -- Input registers
- signal ipr_a : std_logic_vector(31 downto 0);
- signal ipr_a_ref : std_logic_vector(31 downto 0);
- -- Iterator registers
- signal itr_j : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Output registers
- signal opr2_b : std_logic_vector(31 downto 0);
- signal s2_b : integer;
- -- Ppipeline signals
- signal error_pipe : type_err_array(2 downto 0);
- signal ee : boolean;
-
-begin
-
- PIPE_REGS : process(CLK)
- file STIM_a : TEXT open READ_MODE is STIM_DIR&STIM_FILE_a;
- file STIM_b : TEXT open READ_MODE is STIM_DIR&STIM_FILE_b;
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- cntr_i <= 0;
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_a <= ip_a;
- ipr_a_ref <= STD_LOGIC_VECTOR(TO_SIGNED(FREAD_STIM(STIM_a),32));
- -- Iterator Registers
- itr_j <= it_j;
- --
- cntr_i <= cntr_i + 1;
- end if;
- -- Pipeline Depth: 3 stages
- -- The min. depth of a test pipeline is 2 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- error_pipe(0) <= ee;
- end if;
- -- STAGE_1
- if( EN(1) = '1' ) then
- error_pipe(1) <= error_pipe(0);
- end if;
- -- STAGE_2
- if( EN(2) = '1' ) then
- if(error_pipe(1)) then
- opr2_b <= STD_LOGIC_VECTOR(TO_SIGNED(error_int,32));
- else
- opr2_b <= STD_LOGIC_VECTOR(TO_SIGNED(FREAD_STIM(STIM_b),32));
- end if;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_b <= opr2_b;
- --
- -- PIPE_COMB:
- ee <= false
- or (ipr_a /= ipr_a_ref);
- --
- process(CLK)
- begin
-
- assert ee = false
- report "ERROR IN PIPELINE hwn_nd_2_transformer_pipeline of ipcore OCCURED at " & integer'image(cntr_i)
- severity FAILURE;
-
- if (rising_edge(CLK)) then
- if (RST='1') then
- ERROR <= '0';
- elsif (ee) then
- ERROR <= '1';
- end if;
- end if;
- end process;
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2.vhd
deleted file mode 100644
index 3bd8f6a8aaf2c3b67f03887db7f637467314e56d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2.vhd
+++ /dev/null
@@ -1,515 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-entity ipcore2RTL_hwn_nd_2 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_1 : in_0
- ND_2IP_1_Rd : out std_logic;
- ND_2IP_1_Din : in std_logic_vector(31 downto 0);
- ND_2IP_1_Exist : in std_logic;
- ND_2IP_1_CLK : out std_logic;
- ND_2IP_1_CTRL : in std_logic;
-
- -- ED_2 : in_0
- ND_2IP_2_Rd : out std_logic;
- ND_2IP_2_Din : in std_logic_vector(31 downto 0);
- ND_2IP_2_Exist : in std_logic;
- ND_2IP_2_CLK : out std_logic;
- ND_2IP_2_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- -- ED_1 : out_0
- ND_2OP_1_Wr : out std_logic;
- ND_2OP_1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_Full : in std_logic;
- ND_2OP_1_CLK : out std_logic;
- ND_2OP_1_CTRL : out std_logic;
-
- -- ED_3 : out_0
- ND_2OP_1_d1_Wr : out std_logic;
- ND_2OP_1_d1_Dout : out std_logic_vector(31 downto 0);
- ND_2OP_1_d1_Full : in std_logic;
- ND_2OP_1_d1_CLK : out std_logic;
- ND_2OP_1_d1_CTRL : out std_logic;
-
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_hwn_nd_2 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 2; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 2; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 3; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := false; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- a
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- b
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural:=1;
- N_SYNC_OUT : natural:=1;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0);
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
-
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(2*32-1 downto 0); -- a
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- a
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- b
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- signal s_in : std_logic_vector(0 downto 0);
- signal s_out : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_2IP_1_CLK <= CLK;
- ND_2IP_2_CLK <= CLK;
- ND_2OP_1_CLK <= CLK;
- ND_2OP_1_d1_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "a"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 2,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(1 downto 0),
- READS => sl_READS(1 downto 0),
- SOFS => sl_CTRLS(1 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(1 downto 0),
- OBTAIN => sl_obtain_rd(1 downto 0),
- RELEASE => sl_release_rd(1 downto 0)
- );
-
- ND_2IP_1_Rd <= sl_READS(0);
- ND_2IP_2_Rd <= sl_READS(1);
-
- sl_IN_PORTS_0 <= ND_2IP_2_Din & ND_2IP_1_Din;
-
- sl_EXISTS <= ND_2IP_2_Exist & ND_2IP_1_Exist ;
- sl_CTRLS <= ND_2IP_2_CTRL & ND_2IP_1_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- PENDING => sl_pending_rd,
- UPDATE_ACK => sl_update_ack_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "b"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 2
- )
- port map (
- WRITES => sl_WRITES(1 downto 0),
- FULLS => sl_FULLS(1 downto 0),
- CONTROL => sl_lortnoc_wr(1 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- ND_2OP_1_Dout <= sl_out_port_0; -- Func. Output param. "b"
- ND_2OP_1_CTRL <= sl_sof_wr ;
- ND_2OP_1_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= ND_2OP_1_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- ND_2OP_1_d1_Dout <= sl_out_port_0; -- Func. Output param. "b"
- ND_2OP_1_d1_CTRL <= sl_sof_wr ;
- ND_2OP_1_d1_Wr <= sl_WRITES(1);
- sl_FULLS(1) <= ND_2OP_1_d1_Full;
- sl_lortnoc_wr(1) <= sl_control_wr(1);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- PENDING => sl_pending_wr,
- UPDATE_ACK => sl_update_ack_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_2
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_SYNC_IN => 0,
- N_SYNC_OUT => 0,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- SYNC_IN => s_in,
- SYNC_OUT => s_out,
- PENDING_RD => sl_pending_rd,
- PENDING_WR => sl_pending_wr,
- UPDATE_ACK_RD => sl_update_ack_rd,
- UPDATE_ACK_WR => sl_update_ack_wr,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) or sl_READS(1) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
deleted file mode 100644
index 489c3fc8878f18d9fa8ac9f20abbd75674b9c479..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
+++ /dev/null
@@ -1,284 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_2 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_j, sl_high_j : integer;
- signal sl_loop_j, sl_loop_j_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_j : std_logic is sl_cntr_en(0);
- alias load_j : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_j : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "in_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
- signal sl_obtain1 : std_logic;
- signal sl_release1 : std_logic;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
-
- sl_loop_j <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_j_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_j <= 1;
- sl_high_j <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_j_rg-2>=0;
- e1 <= sl_loop_j_rg-1=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port ND_2IP_1 Argument in_1 : ED_1 : 0 of type IOMM
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- -- Convert FIFO Read Port ND_2IP_2 Argument in_2 : ED_2 : 1 of type IOMM
- sl_obtain1 <= ('1'); -- set obtain/release to const value; not used
- sl_release1 <= ('1');
-
- sl_CONTROL(1) <= sl_fire and b2std((e1));
- OBTAIN(1) <= sl_obtain1;
- RELEASE(1) <= sl_release1;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "in_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
deleted file mode 100644
index 48b8d922b70e841ff4619037978b2aa7fcd665c1..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_eval_logic_wr.vhd
+++ /dev/null
@@ -1,266 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_2 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "out_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_j, sl_high_j : integer;
- signal sl_loop_j, sl_loop_j_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_j : std_logic is sl_cntr_en(0);
- --
- alias load_j : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_j : std_logic;
-
- signal e0 : boolean;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments (WRITE)
-
- sl_loop_j <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_j_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_j <= 1;
- sl_high_j <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_j,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_j,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= -sl_loop_j_rg + 8>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : ED_1
- sl_CONTROL(0) <= sl_fire and b2std((e0));
-
- -- Convert FIFO Write Port out_2 : ED_3
- sl_CONTROL(1) <= sl_fire and ('1');
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "out_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_execution_unit.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_execution_unit.vhd
deleted file mode 100644
index 1e728b316371967e38efb94c73df5b78a109bea1..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_2/1/hdlsrc/ipcore2RTL_hwn_nd_2_execution_unit.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "transformer"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "a"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "b"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_2 is
-
- component hwn_nd_2_transformer is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_a : in std_logic_vector(31 downto 0);
- -- Iterators
- it_j : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_b : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : hwn_nd_2_transformer
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_a => IN_PORT_0,
- -- Iterators
- it_j => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_b => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/component.xml
deleted file mode 100644
index 4033c052a1dc7bc4eaae88d050bfa7140690b7b4..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/component.xml
+++ /dev/null
@@ -1,164 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>hwn_nd_3</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:compaandesign.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>ND_3</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>ND_3IP_3</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- <spirit:description>Port is connected to link BUS_ED_3</spirit:description>
- </spirit:port>
- <spirit:port>
- <spirit:name>ND_3IP_4</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- <spirit:description>Port is connected to link BUS_ED_4</spirit:description>
- </spirit:port>
- <spirit:port>
- <spirit:name>data_out</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAM_DT</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>PARAM_LD</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>STOP</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>ERROR</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>BLOCK_RD</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>RESET_HIGH</spirit:name>
- <spirit:value>1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>PAR_WIDTH</spirit:name>
- <spirit:value>16</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="NATURAL">
- <spirit:name>QUANT</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="BOOLEAN">
- <spirit:name>WRAP</spirit:name>
- <spirit:value>true</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_3_execution_unit.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/ipcore2RTL_hwn_nd_3.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/hwn_nd_3_compaan_outlinedproc1.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>hdlsrc/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
- <spirit:description>This node implements function compaan_outlinedproc1</spirit:description>
- <spirit:parameters>
- <spirit:parameter name="data_out">STIM_hwn_nd_3_tmp0</spirit:parameter>
- </spirit:parameters>
-</spirit:component>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp0.txt b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp0.txt
deleted file mode 100644
index af6fcc10f2f6919db11f23e3f20096ed703a4cb5..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp0.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-171
-83
-245
-234
-191
-49
-73
-135
-103
-39
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp1.txt b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp1.txt
deleted file mode 100644
index af81c5987e0249dffd0920f14180f981657f286a..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/STIM_hwn_nd_3_tmp1.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-101
-48
-209
-27
-177
-104
-183
-4
-177
-201
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/hwn_nd_3_compaan_outlinedproc1.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/hwn_nd_3_compaan_outlinedproc1.vhd
deleted file mode 100644
index 8557d6b6a5359e26ecd166cfc560d92952c5172c..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/hwn_nd_3_compaan_outlinedproc1.vhd
+++ /dev/null
@@ -1,158 +0,0 @@
--- File automatically generated by KpnMapper
--- This file descibes the orignal Function
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-
-entity hwn_nd_3_compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end hwn_nd_3_compaan_outlinedproc1;
-
-architecture RTL of hwn_nd_3_compaan_outlinedproc1 is
-
- component hwn_nd_3_compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
-
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
- end component;
-
- component CONTROLLER is
- generic (
- N_STAGES : natural := 1;
- BLOCKING : natural := 0
- );
- port (
- READ : out std_logic;
- EXIST : in std_logic;
- WRITE : out std_logic;
- FULL : in std_logic;
- --
- ENABLE_EX : out std_logic_vector(N_STAGES-1 downto 0);
- STALL_FRONT : in std_logic_vector(N_STAGES-1 downto 0);
- STALL_BACK : in std_logic_vector(N_STAGES-1 downto 0);
- --
- CLK : in std_logic;
- RST : in std_logic
- );
- end component;
-
- constant c_BLOCKING : natural := 1;
-
- signal sl_EXIST : std_logic;
- signal sl_READ : std_logic;
- signal sl_FULL : std_logic;
- signal sl_WRITE : std_logic;
- signal sl_EN : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_FRONT : std_logic_vector(c_STAGES-1 downto 0);
- signal sl_STALL_BACK : std_logic_vector(c_STAGES-1 downto 0);
- --
-
- --
-
- --
-
-begin
-
- -- if all arguments exist, and we do not stop reading, make sl_EXIST high mean you can fire
- sl_EXIST <= '1' when ((STOP_RD='0') and (EXIST=(EXIST'range=>'1'))) else '0';
- -- Functional Evaluation. Only when all signals are high, we can set READF high.
- READF <= (READF'range =>sl_READ);
- sl_FULL <= '0' when ((STOP_WR='0') and (FULL =(FULL'range =>'0'))) else '1';
- WRITEF <= (WRITEF'range=>sl_WRITE);
-
- PIPELINE : hwn_nd_3_compaan_outlinedproc1_pipeline
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- CLK => CLK,
- RST => RST,
- -- Inputs
- ip_tmp1 => ip_tmp1,
- -- Iterators
- it_x => it_x,
- -- Outputs
- op_tmp0 => op_tmp0,
- --
- ENi => sl_READ,
- EN => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- ERROR => ERROR
- );
-
- CTRL : CONTROLLER
- generic map (
- N_STAGES => c_STAGES,
- BLOCKING => c_BLOCKING
- )
- port map (
- RST => RST,
- CLK => CLK,
- READ => sl_READ,
- EXIST => sl_EXIST,
- --
- ENABLE_EX => sl_EN,
- STALL_FRONT => sl_STALL_FRONT,
- STALL_BACK => sl_STALL_BACK,
- --
- WRITE => sl_WRITE,
- FULL => sl_FULL
- );
-
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd
deleted file mode 100644
index 0aba07e73b95e942362a52d520e4d1d26e49a709..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/hwn_nd_3_compaan_outlinedproc1_pipeline.vhd
+++ /dev/null
@@ -1,152 +0,0 @@
--- File automatically generated by KpnMapper
--- This file defines an TEST implementation of a
--- function Test pipeline (containig file traces)
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library std;
-use std.textio.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity hwn_nd_3_compaan_outlinedproc1_pipeline is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- --
- ENi : in std_logic;
- EN : in std_logic_vector(c_STAGES-1 downto 0);
- STALL_FRONT : out std_logic_vector(c_STAGES-1 downto 0);
- STALL_BACK : out std_logic_vector(c_STAGES-1 downto 0);
- ERROR : out std_logic
- );
-end hwn_nd_3_compaan_outlinedproc1_pipeline;
-
-architecture RTL of hwn_nd_3_compaan_outlinedproc1_pipeline is
-
- type type_err_array is array(natural range<>) of boolean;
- --
- constant error_int : integer := -1;
- constant reset_int : integer := 0;
- --
- -- Path to the stimuli directory
- constant STIM_DIR : string := "C:\Users\kienhuis\Documents\workspace\ipcore_trace\.\ipxact\compaandesign.com\ipcore2RTL\hwn_nd_3\1\hdlsrc/";
- -- Stimuli file for input "tmp1"
- constant STIM_FILE_tmp1 : string := "STIM_hwn_nd_3_tmp1.txt";
- -- Stimuli file for output "tmp0"
- constant STIM_FILE_tmp0 : string := "STIM_hwn_nd_3_tmp0.txt";
- --
- -- Function that reads stimuli from a text file
- impure function FREAD_STIM(file F : TEXT) return INTEGER is
- variable X : INTEGER;
- variable IN_LINE : LINE;
- begin
- if (endfile(F)) then
- return error_int;
- else
- readline(F ,IN_LINE);
- read(IN_LINE, X);
- deallocate(IN_LINE);
- return X;
- end if;
- return error_int;
- end;
- --
- signal cntr_i : integer := 0;
- -- Input registers
- signal ipr_tmp1 : std_logic_vector(31 downto 0);
- signal ipr_tmp1_ref : std_logic_vector(31 downto 0);
- -- Iterator registers
- signal itr_x : std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- -- Output registers
- signal opr2_tmp0 : std_logic_vector(31 downto 0);
- signal s2_tmp0 : integer;
- -- Ppipeline signals
- signal error_pipe : type_err_array(2 downto 0);
- signal ee : boolean;
-
-begin
-
- PIPE_REGS : process(CLK)
- file STIM_tmp1 : TEXT open READ_MODE is STIM_DIR&STIM_FILE_tmp1;
- file STIM_tmp0 : TEXT open READ_MODE is STIM_DIR&STIM_FILE_tmp0;
- begin
- if rising_edge(CLK) then
- if (RST='1') then
- -- Something to reset?
- cntr_i <= 0;
- else
- if( ENi = '1' ) then
- -- Input Registers
- ipr_tmp1 <= ip_tmp1;
- ipr_tmp1_ref <= STD_LOGIC_VECTOR(TO_SIGNED(FREAD_STIM(STIM_tmp1),32));
- -- Iterator Registers
- itr_x <= it_x;
- --
- cntr_i <= cntr_i + 1;
- end if;
- -- Pipeline Depth: 3 stages
- -- The min. depth of a test pipeline is 2 stages
- -- STAGE_0
- if( EN(0) = '1' ) then
- error_pipe(0) <= ee;
- end if;
- -- STAGE_1
- if( EN(1) = '1' ) then
- error_pipe(1) <= error_pipe(0);
- end if;
- -- STAGE_2
- if( EN(2) = '1' ) then
- if(error_pipe(1)) then
- opr2_tmp0 <= STD_LOGIC_VECTOR(TO_SIGNED(error_int,32));
- else
- opr2_tmp0 <= STD_LOGIC_VECTOR(TO_SIGNED(FREAD_STIM(STIM_tmp0),32));
- end if;
- end if;
- end if;
- end if;
- end process; -- PIPE_REGS
- --
- -- Output
- op_tmp0 <= opr2_tmp0;
- --
- -- PIPE_COMB:
- ee <= false
- or (ipr_tmp1 /= ipr_tmp1_ref);
- --
- process(CLK)
- begin
-
- assert ee = false
- report "ERROR IN PIPELINE hwn_nd_3_compaan_outlinedproc1_pipeline of ipcore OCCURED at " & integer'image(cntr_i)
- severity FAILURE;
-
- if (rising_edge(CLK)) then
- if (RST='1') then
- ERROR <= '0';
- elsif (ee) then
- ERROR <= '1';
- end if;
- end if;
- end process;
- STALL_FRONT <= (others=>'0');
- STALL_BACK <= (others=>'0');
-end RTL;
-
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3.vhd
deleted file mode 100644
index 7ea05fccd52a97df059fcbf7a5c56ae48cab79e0..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3.vhd
+++ /dev/null
@@ -1,500 +0,0 @@
--- HWN Entity File automatically generated by KpnMapper
--- Top level file for a Hardware Accelerator
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-
-entity ipcore2RTL_hwn_nd_3 is
- generic (
- RESET_HIGH : natural := 1;
- PAR_WIDTH : natural := 16;
- QUANT : natural := 32;
- WRAP : boolean := true
- );
- port (
-
- -- Dataflow input interfaces
- -- ED_3 : in_0
- ND_3IP_3_Rd : out std_logic;
- ND_3IP_3_Din : in std_logic_vector(31 downto 0);
- ND_3IP_3_Exist : in std_logic;
- ND_3IP_3_CLK : out std_logic;
- ND_3IP_3_CTRL : in std_logic;
-
- -- ED_4 : in_0
- ND_3IP_4_Rd : out std_logic;
- ND_3IP_4_Din : in std_logic_vector(31 downto 0);
- ND_3IP_4_Exist : in std_logic;
- ND_3IP_4_CLK : out std_logic;
- ND_3IP_4_CTRL : in std_logic;
-
- -- Dataflow output interfaces
- data_out_Wr : out std_logic;
- data_out_Dout : out std_logic_vector(31 downto 0);
- data_out_Full : in std_logic;
- data_out_CLK : out std_logic;
- data_out_CTRL : out std_logic;
-
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- RST : in std_logic;
- CLK : in std_logic;
- STOP : out std_logic;
- ERROR : out std_logic;
- BLOCK_RD : out std_logic
- );
-end ipcore2RTL_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_hwn_nd_3 is
- --
- -- ====================================
- -- = Constants declaration =
- -- ====================================
- -- Setting the parameters of the HW Node
- constant c_IN_PORTS : natural := 2; -- number of input ports of a HW node
- constant c_OUT_PORTS : natural := 1; -- number of output ports of a HW node
- constant c_IN_FUNC_VAR : natural := 1; -- number of input ports of a HW IP
- constant c_OUT_FUNC_VAR : natural := 1; -- number of output ports of a HW IP
- constant c_COUNTERS : natural := 1; -- number of iterators
- -- ===========================================
- -- = Iterators run from Inner to Outer loop =
- -- ===========================================
- constant c_CNTR_QUANT : natural := 5;
- constant c_CNTR_STEPS : t_counter_step := ( 0=>1, others=>1 );
- constant c_CNTR_WIDTHS : t_counter_width := ( 0=>5, others=>10 );
- constant c_STAGES : natural := 3; -- number of pipeline stages or delay
- constant c_IP_RESET : natural := 1; -- active level of the HW IP reset signal
- constant c_WRAP : boolean := false; -- Operation mode: Single_Shot (false) or Continuous (true)
- constant c_PAR_NUMBER : natural := 0; -- number of global parameters
- constant c_N_PAR : natural := 0; -- indicates if parameters are used (1) or not (0)
- constant c_PAR_BITWIDTH : natural := 1; -- aggregate bitwidth of the parameter vector
- constant c_PAR_VECTOR : t_par_vector:= ( -- (Lower Bound, Upper Bound, Default Value, Bitwidth)
- (0,0,0,0), (0,0,0,0) -- two dummy elements
- );
- --
- -- ====================================
- -- = Components declaration =
- -- ====================================
- component ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- READ_ST : in std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
- end component;
-
- component READ_MUX is
- generic (
- N_PORTS : natural := 1;
- PORT_WIDTH : natural := 32
- );
- port(
- IN_PORTS : in std_logic_vector(N_PORTS*PORT_WIDTH-1 downto 0);
- EXISTS : in std_logic_vector(N_PORTS-1 downto 0);
- READS : out std_logic_vector(N_PORTS-1 downto 0);
- SOFS : in std_logic_vector(N_PORTS-1 downto 0);
-
- OUT_PORT : out std_logic_vector(PORT_WIDTH-1 downto 0);
- EXIST : out std_logic;
- READ : in std_logic;
- SOF : in std_logic;
-
- READ_EN : in std_logic;
- READ_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0);
- OBTAIN : in std_logic_vector(N_PORTS-1 downto 0);
- RELEASE : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- WRITE_ST : in std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
- end component;
-
- component WRITE_DEMUX is
- generic (
- N_PORTS : natural := 1
- );
- port(
- WRITES : out std_logic_vector(N_PORTS-1 downto 0);
- WRITE : in std_logic;
-
- FULLS : in std_logic_vector(N_PORTS-1 downto 0);
- FULL : out std_logic;
-
- WRITE_EN : in std_logic;
- WRITE_ST : out std_logic;
- CONTROL : in std_logic_vector(N_PORTS-1 downto 0)
- );
- end component;
-
- component ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
-
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT -1 downto 0);
- -- Func. Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- tmp1
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Func. Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- tmp0
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- component PARAMETERS is
- generic (
- PAR_WIDTH : natural:=16;
- PAR_BITWIDTH : natural:=1;
- PAR_VECTOR : t_par_vector;
- N_SYNC_IN : natural:=1;
- N_SYNC_OUT : natural:=1;
- N_PAR : natural:=0
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- HALT : out std_logic;
- HALTED : in std_logic;
-
- SYNC_IN : in std_logic_vector(N_SYNC_IN downto 0);
- SYNC_OUT : out std_logic_vector(N_SYNC_OUT downto 0);
-
- PENDING_RD : out std_logic;
- PENDING_WR : out std_logic;
- UPDATE_ACK_RD : in std_logic;
- UPDATE_ACK_WR : in std_logic;
-
- PARAM_DT : in std_logic_vector(PAR_WIDTH-1 downto 0);
- PARAM_LD : in std_logic;
-
- PARAMETERS : out std_logic_vector(0 downto 0)
- );
- end component;
-
- --
- -- ====================================
- -- = Signals declaration =
- -- ====================================
- --
- -- HW Node Input Ports
- signal sl_IN_PORTS_0 : std_logic_vector(2*32-1 downto 0); -- tmp1
- signal sl_EXISTS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_READS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_CTRLS : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_control_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_obtain_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- signal sl_release_rd : std_logic_vector(c_IN_PORTS-1 downto 0);
- --
- -- Func. Input parameters
- signal sl_in_port_0 : std_logic_vector(31 downto 0); -- tmp1
- signal sl_exist : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_en : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- signal sl_read_st : std_logic_vector(c_IN_FUNC_VAR-1 downto 0);
- --
- signal sl_REG_CNTRS_RD : std_logic_vector(c_COUNTERS*c_CNTR_QUANT-1 downto 0);
- --
- -- HW Node Output Ports
- signal sl_WRITES : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_FULLS : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_control_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- signal sl_lortnoc_wr : std_logic_vector(c_OUT_PORTS-1 downto 0);
- --
- -- Func. Output parameters
- signal sl_out_port_0 : std_logic_vector(31 downto 0); -- tmp0
- signal sl_full : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_en : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- signal sl_write_st : std_logic_vector(c_OUT_FUNC_VAR-1 downto 0);
- --
- --
- signal sl_halt : std_logic;
- signal sl_halted : std_logic;
- signal sl_halt_wr : std_logic;
- signal sl_halt_rd : std_logic;
- signal sl_done_wr : std_logic;
- signal sl_done_rd : std_logic;
- signal sl_stop_wr : std_logic;
- signal sl_stop_rd : std_logic;
- signal sl_fire_wr : std_logic;
- signal sl_fire_rd : std_logic;
- signal sl_sof_wr : std_logic;
- signal sl_sof_rd : std_logic;
- signal sl_error : std_logic;
-
- --
- -- Parameter related signals
- signal sl_parameters : std_logic_vector(0 downto 0);
-
- signal sl_pending_rd : std_logic;
- signal sl_pending_wr : std_logic;
- signal sl_update_ack_rd : std_logic;
- signal sl_update_ack_wr : std_logic;
-
- signal s_in : std_logic_vector(0 downto 0);
- signal s_out : std_logic_vector(0 downto 0);
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when RESET_HIGH=1 else not RST;
- ND_3IP_3_CLK <= CLK;
- ND_3IP_4_CLK <= CLK;
- data_out_CLK <= CLK;
-
- --
- -- ==========================================================
- -- = HWN Input related modules =
- -- ==========================================================
- -- Func. Input param. "tmp1"
- RD_MUX_0 : READ_MUX
- generic map (
- N_PORTS => 2,
- PORT_WIDTH => 32
- )
- port map (
- IN_PORTS => sl_IN_PORTS_0,
- EXISTS => sl_EXISTS(1 downto 0),
- READS => sl_READS(1 downto 0),
- SOFS => sl_CTRLS(1 downto 0),
-
- OUT_PORT => sl_in_port_0,
- EXIST => sl_exist(0),
- READ => sl_read(0),
- SOF => sl_sof_rd,
-
- READ_EN => sl_read_en(0),
- READ_ST => sl_read_st(0),
- CONTROL => sl_control_rd(1 downto 0),
- OBTAIN => sl_obtain_rd(1 downto 0),
- RELEASE => sl_release_rd(1 downto 0)
- );
-
- ND_3IP_3_Rd <= sl_READS(0);
- ND_3IP_4_Rd <= sl_READS(1);
-
- sl_IN_PORTS_0 <= ND_3IP_4_Din & ND_3IP_3_Din;
-
- sl_EXISTS <= ND_3IP_4_Exist & ND_3IP_3_Exist ;
- sl_CTRLS <= ND_3IP_4_CTRL & ND_3IP_3_CTRL ;
-
- EVAL_RD : ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3
- generic map (
- N_IN_PORTS => c_IN_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- REG_CNTRS => sl_REG_CNTRS_RD,
- READ_EN => sl_read_en,
- READ_ST => sl_read_st,
- HALT => sl_halt_rd,
- PENDING => sl_pending_rd,
- UPDATE_ACK => sl_update_ack_rd,
- FIRE => sl_fire_rd,
- DONE => sl_done_rd,
- STOP => sl_stop_rd,
- SOF => sl_sof_rd,
- CONTROL => sl_control_rd,
- OBTAIN => sl_obtain_rd,
- RELEASE => sl_release_rd
- );
-
- --
- -- ==========================================================
- -- = HWN Output related modules =
- -- ==========================================================
- --
- -- Func. Output param. "tmp0"
- DEMUX_0 : WRITE_DEMUX
- generic map (
- N_PORTS => 1
- )
- port map (
- WRITES => sl_WRITES(0 downto 0),
- FULLS => sl_FULLS(0 downto 0),
- CONTROL => sl_lortnoc_wr(0 downto 0),
- WRITE => sl_write(0),
- FULL => sl_full(0),
- WRITE_EN => sl_write_en(0),
- WRITE_ST => sl_write_st(0)
- );
- --
- data_out_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
- data_out_CTRL <= sl_sof_wr ;
- data_out_Wr <= sl_WRITES(0);
- sl_FULLS(0) <= data_out_Full;
- sl_lortnoc_wr(0) <= sl_control_wr(0);
- --
- --
- EVAL_WR : ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3
- generic map (
- N_OUT_PORTS => c_OUT_PORTS,
- WRAP => c_WRAP,
- N_CNTRS => c_COUNTERS,
- QUANT => c_CNTR_QUANT,
- CNTR_STEP => c_CNTR_STEPS,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- PARAMETERS => sl_parameters,
- WRITE_EN => sl_write_en,
- WRITE_ST => sl_write_st,
- HALT => sl_halt_wr,
- PENDING => sl_pending_wr,
- UPDATE_ACK => sl_update_ack_wr,
- FIRE => sl_fire_wr,
- DONE => sl_done_wr,
- STOP => sl_stop_wr,
- SOF => sl_sof_wr,
- CONTROL => sl_control_wr
- );
-
- --
- -- ==========================================================
- -- = HWN Execution Unit =
- -- ==========================================================
- EX : ipcore2RTL_EXECUTION_UNIT_hwn_nd_3
- generic map (
- N_INPORTS => c_IN_FUNC_VAR,
- N_OUTPORTS => c_OUT_FUNC_VAR,
- IP_RESET => c_IP_RESET,
- QUANT => QUANT,
- c_STAGES => c_STAGES,
- N_CNTRS => c_COUNTERS,
- CNTR_QUANT => c_CNTR_QUANT,
- CNTR_WIDTH => c_CNTR_WIDTHS
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Iterators
- REG_CNTRS_RD => sl_REG_CNTRS_RD,
- -- Func. Input parameters
- IN_PORT_0 => sl_in_port_0,
- READ => sl_read,
- EXIST => sl_exist,
- -- Func. Output parameters
- OUT_PORT_0 => sl_out_port_0,
- WRITE => sl_write,
- FULL => sl_full,
- --
- STOP_WR => sl_stop_wr,
- STOP_RD => sl_stop_rd,
- ERROR => sl_error
- );
-
- PAR_LOAD : PARAMETERS
- generic map (
- PAR_WIDTH => PAR_WIDTH,
- PAR_BITWIDTH => c_PAR_BITWIDTH,
- PAR_VECTOR => c_PAR_VECTOR,
- N_SYNC_IN => 0,
- N_SYNC_OUT => 0,
- N_PAR => c_N_PAR
- )
- port map(
- RST => sl_RST,
- CLK => CLK,
- HALT => sl_halt,
- HALTED => sl_halted,
- PARAM_DT => PARAM_DT,
- PARAM_LD => PARAM_LD,
- SYNC_IN => s_in,
- SYNC_OUT => s_out,
- PENDING_RD => sl_pending_rd,
- PENDING_WR => sl_pending_wr,
- UPDATE_ACK_RD => sl_update_ack_rd,
- UPDATE_ACK_WR => sl_update_ack_wr,
- PARAMETERS => sl_parameters
- );
-
- sl_halt_rd <= sl_halt;
- sl_halt_wr <= sl_halt and sl_stop_rd;
- sl_halted <= sl_sof_rd;
- STOP <= sl_done_wr;
- ERROR <= sl_error;
- BLOCK_RD <= not ( ( sl_READS(0) or sl_READS(1) ) );
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
deleted file mode 100644
index 2b0ac1fb797a010aa9cd5d2630c65d86f3f37a50..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
+++ /dev/null
@@ -1,284 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- generic (
- N_IN_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- REG_CNTRS : out std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- READ_EN : out std_logic_vector(0 downto 0);
- READ_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_IN_PORTS-1 downto 0);
- OBTAIN : out std_logic_vector(N_IN_PORTS-1 downto 0);
- RELEASE : out std_logic_vector(N_IN_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_RD_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_sof : std_logic;
- signal sl_eof : std_logic;
-
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- alias load_x : std_logic is sl_load(0);
-
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_IN_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function input parameter "in_0", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
-
- signal e0, e1 : boolean;
-
- signal sl_obtain0 : std_logic;
- signal sl_release0 : std_logic;
- signal sl_obtain1 : std_logic;
- signal sl_release1 : std_logic;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
-
- -- define control variables
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
-
- sl_loop_x <= TO_INTEGER(SIGNED(sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED(sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
- -- Special definitions
-
- -- Entity and control variables
- -- Release matrix expressions
- e0 <= sl_loop_x_rg-1>=0;
- e1 <= sl_loop_x_rg=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Read Port ND_3IP_3 Argument in_1 : ED_3 : 0 of type IOMM
- sl_obtain0 <= ('1'); -- set obtain/release to const value; not used
- sl_release0 <= ('1');
-
- sl_CONTROL(0) <= sl_fire and b2std((e0));
- OBTAIN(0) <= sl_obtain0;
- RELEASE(0) <= sl_release0;
-
- -- Convert FIFO Read Port ND_3IP_4 Argument in_2 : ED_4 : 1 of type IOMM
- sl_obtain1 <= ('1'); -- set obtain/release to const value; not used
- sl_release1 <= ('1');
-
- sl_CONTROL(1) <= sl_fire and b2std((e1));
- OBTAIN(1) <= sl_obtain1;
- RELEASE(1) <= sl_release1;
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function input parameter "in_0", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- READ_EN <= (others=>'1') when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= READ_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when (sl_enables=(sl_enables'range=>'1')) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_RD : for i in 0 to N_CNTRS-1 generate
- CNTR_RD : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- REG_CNTRS <= sl_reg_cntrs;
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1') or (sl_no_request='0'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame
- SOF <= sl_sof; -- Start-of-frame
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
deleted file mode 100644
index e8342a6399762e8fac28437d6604df218a6ba446..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_eval_logic_wr.vhd
+++ /dev/null
@@ -1,264 +0,0 @@
--- File automatically generated by KpnMapper
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_hwnode_1;
-use compaandesign_com_common_hwnode_1.all;
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-entity ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- generic (
- N_OUT_PORTS : natural := 1;
- WRAP : boolean := true;
- N_CNTRS : natural := 1;
- QUANT : natural := 32;
- CNTR_STEP : t_counter_step := ( 0=> 1, 1=> 1, 2=>1, others=> 1 );
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- PARAMETERS : in std_logic_vector(0 downto 0);
- WRITE_EN : out std_logic_vector(0 downto 0);
- WRITE_ST : in std_logic_vector(0 downto 0);
- HALT : in std_logic;
- PENDING : in std_logic;
- UPDATE_ACK : out std_logic;
- FIRE : out std_logic;
- DONE : out std_logic;
- STOP : out std_logic;
- SOF : out std_logic;
- CONTROL : out std_logic_vector(N_OUT_PORTS-1 downto 0)
- );
-end ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3;
-
-architecture RTL of ipcore2RTL_EVAL_LOGIC_WR_hwn_nd_3 is
- --
- component counter is
- generic(
- C_STEP : natural := 10;
- C_WIDTH : natural := 10
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- ENABLE : in std_logic;
- LOAD : in std_logic;
- LOWER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- UPPER_BND : in std_logic_vector(C_WIDTH-1 downto 0);
- ITERATOR : out std_logic_vector(C_WIDTH-1 downto 0);
- REG_CNTR : out std_logic_vector(C_WIDTH-1 downto 0);
- DONE : out std_logic
- );
- end component;
- --
- component it_mod is
- generic(
- C_MOD : natural := 10;
- C_WIDTH : natural := 10;
- C_INIT : natural := 1;
- C_STEP : natural := 1
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- LOAD : in std_logic;
- ENABLE : in std_logic;
- MODULE : out std_logic_vector(C_WIDTH-1 downto 0)
- );
- end component;
- --
- -- Multirate related signals
- signal sl_mr_en : std_logic_vector(0 downto 0);
- signal sl_mr_done : std_logic_vector(0 downto 0);
- signal sl_mr_lock : std_logic_vector(0 downto 0);
- signal sl_enables : std_logic_vector(0 downto 0);
- signal sl_enable : std_logic;
- signal ENABLE : std_logic;
- -- Function output parameter "data_out[x]", multirate=1
- constant sl_mr_lbnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- constant sl_mr_ubnd_0 : std_logic_vector(0 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,1));
- --
- -- Parameter related signals
- --
- -- Iterator (counter) related signals
- signal sl_low_x, sl_high_x : integer;
- signal sl_loop_x, sl_loop_x_rg : integer;
- signal sl_lower_bnd, sl_upper_bnd : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- signal sl_iterators, sl_reg_cntrs : std_logic_vector(N_CNTRS*QUANT-1 downto 0);
- --
- signal sl_cntr_en : std_logic_vector(N_CNTRS downto 0);
- signal sl_done : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_done_all : std_logic;
- signal sl_load : std_logic_vector(N_CNTRS-1 downto 0);
- signal sl_stop : std_logic;
- signal sl_fire : std_logic;
- signal sl_eof : std_logic;
- signal sl_sof : std_logic;
- --
- -- Special Control signal
- signal sl_CONTROL : std_logic_vector(N_OUT_PORTS-1 downto 0);
- signal sl_no_request : std_logic;
- --
- -- alias signals
- alias update_x : std_logic is sl_cntr_en(0);
- --
- alias load_x : std_logic is sl_load(0);
- -- Trigger signals
- signal sl_trigger_x : std_logic;
-
- signal e0, e1 : boolean;
-
- signal sl_halt : std_logic;
- signal sl_update_ack : std_logic;
- signal sl_pending : std_logic;
-
- -- define state machine variables
- type state_type is (s_idle, s_halt, s_update, s_reset_1, s_reset_2, s_reset_3);
- signal state : state_type;
- -- define control variables
- -- MOD related signals
-
-
-begin
-
- -- =============================================
- -- = MOD Functions
- -- =============================================
- -- END of MOD definitions
- --
- -- Parameter related signal assignments (WRITE)
-
- sl_loop_x <= TO_INTEGER(SIGNED( sl_iterators(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
- sl_loop_x_rg <= TO_INTEGER(SIGNED( sl_reg_cntrs(CNTR_WIDTH(0)+0*QUANT-1 downto 0*QUANT)));
-
- -- Const bounds for-loops
- sl_low_x <= 0;
- sl_high_x <= 9;
-
-
- sl_lower_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_low_x,QUANT));
-
- sl_upper_bnd(1*QUANT-1 downto 0*QUANT) <= STD_LOGIC_VECTOR(TO_UNSIGNED(sl_high_x,QUANT));
-
- -- Special definitions
-
- -- Entity and control variables
- e0 <= sl_loop_x_rg>=0;
- e1 <= -sl_loop_x_rg + 9>=0;
-
- sl_fire <= ('1');
-
- -- Convert FIFO Write Port out_1 : EXTERNAL
- sl_CONTROL(0) <= sl_fire and b2std((e0 and e1));
-
- FIRE <= sl_fire;
-
- --
- -- =============================================
- -- = Multirate
- -- =============================================
- -- Function output parameter "data_out[x]", multirate=1
- CNTR_MR0 : counter
- generic map (
- C_STEP => 1,
- C_WIDTH => 1
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_mr_en(0),
- LOAD => '0',
- LOWER_BND => sl_mr_lbnd_0,
- UPPER_BND => sl_mr_ubnd_0,
- ITERATOR => open,
- REG_CNTR => open,
- DONE => sl_mr_done(0)
- );
- --
- WRITE_EN <= (not sl_mr_lock) when ((sl_stop='0') and (sl_fire='1')) else (others=>'0');
- sl_mr_en <= (not sl_mr_lock) and WRITE_ST;
- sl_enables <= sl_mr_lock or (sl_mr_done and sl_mr_en);
- sl_enable <= '1' when ( sl_enables=(sl_enables'range=>'1') ) else '0'; -- and_reduce
- ENABLE <= sl_enable or (not sl_fire);
- --
- LOCK_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_mr_lock <= (others=>'0');
- else
- if (ENABLE='1') then
- sl_mr_lock <= (others=>'0');
- else
- for i in 0 to 0 loop
- if (sl_mr_done(i)='1' and sl_mr_en(i)='1') then
- sl_mr_lock(i) <= '1';
- end if;
- end loop;
- end if;
- end if;
- end if;
- end process;
- -- END of Multirate definitions
- --
- -- =============================================
- -- = Iterators
- -- =============================================
- GEN_CNTR_WR : for i in 0 to N_CNTRS-1 generate
- CNTR_WR : counter
- generic map (
- C_STEP => CNTR_STEP(i),
- C_WIDTH => CNTR_WIDTH(i)
- )
- port map (
- CLK => CLK,
- RST => RST,
- ENABLE => sl_cntr_en(i),
- LOAD => sl_load(i),
- LOWER_BND => sl_lower_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- UPPER_BND => sl_upper_bnd(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- ITERATOR => sl_iterators(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- REG_CNTR => sl_reg_cntrs(i*QUANT+CNTR_WIDTH(i)-1 downto i*QUANT),
- DONE => sl_done(i)
- );
- end generate;
- --
- DONE_PRCS: process(CLK)
- begin
- if rising_edge(CLK) then
- if( RST = '1' ) then
- sl_stop <= '0';
- sl_done_all <= '0';
- sl_sof <= '1';
- else
- if (sl_cntr_en(N_CNTRS)='1' and (WRAP=false or sl_halt='1')) then
- sl_stop <= '1';
- elsif (WRAP=true and sl_halt='0') then
- sl_stop <= '0';
- end if;
- if (sl_stop='0') then
- sl_done_all <= sl_cntr_en(N_CNTRS);
- end if;
- if (ENABLE='1') then
- sl_sof <= sl_eof;
- end if;
- end if;
- end if;
- end process;
- --
- sl_no_request <= '0' when (sl_CONTROL=(sl_CONTROL'range =>'0')) else '1';
- CONTROL <= sl_CONTROL;
- --
- DONE <= sl_done_all; -- '1' in the clock cycle when the counters roll over (from the last point in the space to the firts pont)
- STOP <= sl_stop; -- '1' = The couter stoped after the end of the itteration space.
- sl_cntr_en(0) <= '0' when (sl_stop='1') else
- '1' when (((sl_fire='0') or (ENABLE='1'))) else '0';
- sl_cntr_en(N_CNTRS downto 1) <= sl_cntr_en(N_CNTRS-1 downto 0) and sl_done(N_CNTRS-1 downto 0);
- sl_eof <= sl_cntr_en(N_CNTRS); -- End-of-frame (combinatorial; beter not use it outside)
- SOF <= sl_sof; -- Start-of-frame (FF)
- --
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_execution_unit.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_execution_unit.vhd
deleted file mode 100644
index f1c3a57edf93e1e2280158d063d801b60555b90d..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/hwn_nd_3/1/hdlsrc/ipcore2RTL_hwn_nd_3_execution_unit.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
--- Execute Unit automatically generated by KpnMapper
--- Function "compaan_outlinedproc1"
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library compaandesign_com_common_common_1;
-use compaandesign_com_common_common_1.hw_node_pkg.all;
-
-
-entity ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
- generic (
- N_INPORTS : natural := 1;
- N_OUTPORTS : natural := 1;
- IP_RESET : natural := 1;
- QUANT : natural := 32;
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Funtion Input parameters
- IN_PORT_0 : in std_logic_vector(31 downto 0); -- Param. "tmp1"
- READ : out std_logic_vector(N_INPORTS-1 downto 0);
- EXIST : in std_logic_vector(N_INPORTS-1 downto 0);
- -- Iterators
- REG_CNTRS_RD : in std_logic_vector(N_CNTRS*CNTR_QUANT-1 downto 0);
- -- Funtion Output parameters
- OUT_PORT_0 : out std_logic_vector(31 downto 0); -- Param. "tmp0"
- WRITE : out std_logic_vector(N_OUTPORTS-1 downto 0);
- FULL : in std_logic_vector(N_OUTPORTS-1 downto 0);
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
-end ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 ;
-
--- Laura implementation
-architecture Laura of ipcore2RTL_EXECUTION_UNIT_hwn_nd_3 is
-
- component hwn_nd_3_compaan_outlinedproc1 is
- generic (
- c_STAGES : natural := 1;
- N_CNTRS : natural := 1;
- CNTR_QUANT : natural := 32;
- CNTR_WIDTH : t_counter_width := ( 0=>10, 1=>10, 2=>9, others=>10 )
- );
- port (
- RST : in std_logic;
- CLK : in std_logic;
- -- Inputs
- ip_tmp1 : in std_logic_vector(31 downto 0);
- -- Iterators
- it_x : in std_logic_vector(CNTR_WIDTH(0)-1 downto 0);
- EXIST : in std_logic_vector(0 downto 0);
- READF : out std_logic_vector(0 downto 0);
- -- Outputs
- op_tmp0 : out std_logic_vector(31 downto 0);
- FULL : in std_logic_vector(0 downto 0);
- WRITEF: out std_logic_vector(0 downto 0);
- --
- STOP_RD : in std_logic;
- STOP_WR : in std_logic;
- ERROR : out std_logic
- );
- end component;
-
- signal sl_RST : std_logic;
-
-begin
-
- sl_RST <= RST when IP_RESET=1 else not RST;
-
- FUNC : hwn_nd_3_compaan_outlinedproc1
- generic map (
- c_STAGES => c_STAGES,
- N_CNTRS => N_CNTRS,
- CNTR_QUANT => CNTR_QUANT,
- CNTR_WIDTH => CNTR_WIDTH
- )
- port map (
- RST => sl_RST,
- CLK => CLK,
- -- Inputs
- ip_tmp1 => IN_PORT_0,
- -- Iterators
- it_x => REG_CNTRS_RD(0*CNTR_QUANT+CNTR_WIDTH(0)-1 downto 0*CNTR_QUANT),
- EXIST => EXIST,
- READF => READ,
- -- Outputs
- op_tmp0 => OUT_PORT_0,
- FULL => FULL,
- WRITEF=> WRITE,
- --
- STOP_RD => STOP_RD,
- STOP_WR => STOP_WR,
- ERROR => ERROR
- );
-
-end Laura;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/register_rf/1/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/register_rf/1/component.xml
deleted file mode 100644
index 19967b057841361a57699da4f1f589cd58be2e64..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/register_rf/1/component.xml
+++ /dev/null
@@ -1,92 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>register_rf</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>vhdlsource</spirit:name>
- <spirit:envIdentifier>:compaandesign.com:</spirit:envIdentifier>
- <spirit:language spirit:strict="true">vhdl</spirit:language>
- <spirit:modelName>register_rf</spirit:modelName>
- <spirit:fileSetRef>sourceCode</spirit:fileSetRef>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>18</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>read_data</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>read_en</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>write_en</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>write_data</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:fileSets>
- <spirit:fileSet>
- <spirit:name>sourceCode</spirit:name>
- <spirit:file>
- <spirit:name>hdlsrc/register_rf.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileSet>
- </spirit:fileSets>
- <spirit:description>This node implements the parameter register file</spirit:description>
-</spirit:component>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/register_rf/1/hdlsrc/register_rf.vhd b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/register_rf/1/hdlsrc/register_rf.vhd
deleted file mode 100644
index 38a6dd8770213aec9210e54343d78dd974956622..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/register_rf/1/hdlsrc/register_rf.vhd
+++ /dev/null
@@ -1,30 +0,0 @@
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity register_rf is
-
-port (
- rst : in std_logic;
- clk : in std_logic;
- --
-
- -- Interface to PCIe
- address : in std_logic_vector(18 downto 0);
- read_data : out std_logic_vector(31 downto 0);
- read_en : in std_logic;
- write_en : in std_logic;
- write_data : in std_logic_vector(31 downto 0)
- --
-);
-end register_rf;
-
-architecture RTL of register_rf is
-
- signal sl_read_data : std_logic_vector(32-1 downto 0) := (others=>'0');
-
-begin
- read_data <= (others => '0');
-
-end RTL;
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/system/component.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/system/component.xml
deleted file mode 100644
index b6c11ac5528ca223bad9ed6c44e0f4150fb790b1..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/system/component.xml
+++ /dev/null
@@ -1,178 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:component xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>ipcore</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>data_in</spirit:name>
- <spirit:busType spirit:library="busdef.pop" spirit:name="pop" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:abstractionType spirit:library="busdef.pop" spirit:name="pop_rtl" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>fifo_out</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>data_in</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>data_out</spirit:name>
- <spirit:busType spirit:library="busdef.push" spirit:name="push" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:abstractionType spirit:library="busdef.push" spirit:name="push_rtl" spirit:vendor="compaandesign.com" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>fifo_in</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>data_out</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- </spirit:busInterface>
- </spirit:busInterfaces>
- <spirit:model>
- <spirit:views>
- <spirit:view>
- <spirit:name>ipcore-design</spirit:name>
- <spirit:envIdentifier>::Hierarchy</spirit:envIdentifier>
- <spirit:hierarchyRef spirit:vendor="compaandesign.com" spirit:library="ipcore2RTL" spirit:name="design_ipcore" spirit:version="1"/>
- </spirit:view>
- </spirit:views>
- <spirit:ports>
- <spirit:port>
- <spirit:name>data_in</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>data_out</spirit:name>
- <spirit:wire>
- <spirit:qualifier>
- <spirit:isData>true</spirit:isData>
- </spirit:qualifier>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>TEST_STOP</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>2</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>TEST_ERROR</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>2</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>TEST_FIFO_FULL</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>3</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>TEST_BLOCK_RD</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>2</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>address</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>18</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>read_data</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>read_en</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>write_en</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>write_data</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>31</spirit:left>
- <spirit:right>0</spirit:right>
- </spirit:vector>
- </spirit:wire>
- </spirit:port>
- </spirit:ports>
- </spirit:model>
-</spirit:component>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/system/design.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/system/design.xml
deleted file mode 100644
index bd97d648099f22f743fae4e7c09e53d6707c2353..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/ipcore2RTL/system/design.xml
+++ /dev/null
@@ -1,270 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:design xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>design_ipcore</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>hwn_nd_1</spirit:instanceName>
- <spirit:componentRef spirit:library="ipcore2RTL" spirit:name="hwn_nd_1" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="RESET_HIGH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PAR_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="QUANT">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="WRAP">false</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>hwn_nd_2</spirit:instanceName>
- <spirit:componentRef spirit:library="ipcore2RTL" spirit:name="hwn_nd_2" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="RESET_HIGH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PAR_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="QUANT">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="WRAP">false</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>hwn_nd_3</spirit:instanceName>
- <spirit:componentRef spirit:library="ipcore2RTL" spirit:name="hwn_nd_3" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="RESET_HIGH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PAR_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="QUANT">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="WRAP">false</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>control_if</spirit:instanceName>
- <spirit:componentRef spirit:library="ipcore2RTL" spirit:name="control_if" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="RESET_HIGH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="QUANT">1</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>register_rf</spirit:instanceName>
- <spirit:componentRef spirit:library="ipcore2RTL" spirit:name="register_rf" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="RESET_HIGH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="QUANT">1</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>ed_1</spirit:instanceName>
- <spirit:componentRef spirit:library="common" spirit:name="fifo" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DEPTH">5</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DWIDTH">31</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>ed_2</spirit:instanceName>
- <spirit:componentRef spirit:library="common" spirit:name="fifo" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DEPTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DWIDTH">31</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>ed_3</spirit:instanceName>
- <spirit:componentRef spirit:library="common" spirit:name="fifo" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DEPTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DWIDTH">31</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- <spirit:componentInstance>
- <spirit:instanceName>ed_4</spirit:instanceName>
- <spirit:componentRef spirit:library="common" spirit:name="fifo" spirit:vendor="compaandesign.com" spirit:version="1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DEPTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="C_FSL_DWIDTH">31</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- </spirit:componentInstances>
- <spirit:interconnections>
- <!-- TO DO, CONNEXTIONS -->
- <spirit:interconnection>
- <spirit:name>ed_2_out</spirit:name>
- <spirit:activeInterface spirit:busRef="ND_1OP_1" spirit:componentRef="hwn_nd_1"/>
- <spirit:activeInterface spirit:busRef="FSL_M" spirit:componentRef="ed_2"/>
- </spirit:interconnection>
- <spirit:interconnection>
- <spirit:name>ed_4_out</spirit:name>
- <spirit:activeInterface spirit:busRef="ND_1OP_1_d1" spirit:componentRef="hwn_nd_1"/>
- <spirit:activeInterface spirit:busRef="FSL_M" spirit:componentRef="ed_4"/>
- </spirit:interconnection>
- <spirit:interconnection>
- <spirit:name>ed_1_in</spirit:name>
- <spirit:activeInterface spirit:busRef="FSL_S" spirit:componentRef="ed_1"/>
- <spirit:activeInterface spirit:busRef="ND_2IP_1" spirit:componentRef="hwn_nd_2"/>
- </spirit:interconnection>
- <spirit:interconnection>
- <spirit:name>ed_2_in</spirit:name>
- <spirit:activeInterface spirit:busRef="FSL_S" spirit:componentRef="ed_2"/>
- <spirit:activeInterface spirit:busRef="ND_2IP_2" spirit:componentRef="hwn_nd_2"/>
- </spirit:interconnection>
- <spirit:interconnection>
- <spirit:name>ed_1_out</spirit:name>
- <spirit:activeInterface spirit:busRef="ND_2OP_1" spirit:componentRef="hwn_nd_2"/>
- <spirit:activeInterface spirit:busRef="FSL_M" spirit:componentRef="ed_1"/>
- </spirit:interconnection>
- <spirit:interconnection>
- <spirit:name>ed_3_out</spirit:name>
- <spirit:activeInterface spirit:busRef="ND_2OP_1_d1" spirit:componentRef="hwn_nd_2"/>
- <spirit:activeInterface spirit:busRef="FSL_M" spirit:componentRef="ed_3"/>
- </spirit:interconnection>
- <spirit:interconnection>
- <spirit:name>ed_3_in</spirit:name>
- <spirit:activeInterface spirit:busRef="FSL_S" spirit:componentRef="ed_3"/>
- <spirit:activeInterface spirit:busRef="ND_3IP_3" spirit:componentRef="hwn_nd_3"/>
- </spirit:interconnection>
- <spirit:interconnection>
- <spirit:name>ed_4_in</spirit:name>
- <spirit:activeInterface spirit:busRef="FSL_S" spirit:componentRef="ed_4"/>
- <spirit:activeInterface spirit:busRef="ND_3IP_4" spirit:componentRef="hwn_nd_3"/>
- </spirit:interconnection>
- </spirit:interconnections>
- <spirit:adHocConnections>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_1_STOP</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_1" spirit:portRef="STOP" />
- <spirit:externalPortReference spirit:portRef="TEST_STOP" spirit:left="0" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_1_ERROR</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_1" spirit:portRef="ERROR" />
- <spirit:externalPortReference spirit:portRef="TEST_ERROR" spirit:left="0" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_1_BLOCK_RD</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_1" spirit:portRef="BLOCK_RD" />
- <spirit:externalPortReference spirit:portRef="TEST_BLOCK_RD" spirit:left="0" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_2_STOP</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_2" spirit:portRef="STOP" />
- <spirit:externalPortReference spirit:portRef="TEST_STOP" spirit:left="1" spirit:right="1" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_2_ERROR</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_2" spirit:portRef="ERROR" />
- <spirit:externalPortReference spirit:portRef="TEST_ERROR" spirit:left="1" spirit:right="1" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_2_BLOCK_RD</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_2" spirit:portRef="BLOCK_RD" />
- <spirit:externalPortReference spirit:portRef="TEST_BLOCK_RD" spirit:left="1" spirit:right="1" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_3_STOP</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_3" spirit:portRef="STOP" />
- <spirit:externalPortReference spirit:portRef="TEST_STOP" spirit:left="2" spirit:right="2" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_3_ERROR</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_3" spirit:portRef="ERROR" />
- <spirit:externalPortReference spirit:portRef="TEST_ERROR" spirit:left="2" spirit:right="2" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>hwn_nd_3_BLOCK_RD</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_3" spirit:portRef="BLOCK_RD" />
- <spirit:externalPortReference spirit:portRef="TEST_BLOCK_RD" spirit:left="2" spirit:right="2" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>ed_1_FIFO_FULL</spirit:name>
- <spirit:internalPortReference spirit:componentRef="ed_1" spirit:portRef="FSL_FULL" />
- <spirit:externalPortReference spirit:portRef="TEST_FIFO_FULL" spirit:left="0" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>ed_2_FIFO_FULL</spirit:name>
- <spirit:internalPortReference spirit:componentRef="ed_2" spirit:portRef="FSL_FULL" />
- <spirit:externalPortReference spirit:portRef="TEST_FIFO_FULL" spirit:left="1" spirit:right="1" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>ed_3_FIFO_FULL</spirit:name>
- <spirit:internalPortReference spirit:componentRef="ed_3" spirit:portRef="FSL_FULL" />
- <spirit:externalPortReference spirit:portRef="TEST_FIFO_FULL" spirit:left="2" spirit:right="2" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>ed_4_FIFO_FULL</spirit:name>
- <spirit:internalPortReference spirit:componentRef="ed_4" spirit:portRef="FSL_FULL" />
- <spirit:externalPortReference spirit:portRef="TEST_FIFO_FULL" spirit:left="3" spirit:right="3" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>PARAM_DT</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_1" spirit:portRef="PARAM_DT" spirit:left="0" spirit:right="0" />
- <spirit:internalPortReference spirit:componentRef="hwn_nd_2" spirit:portRef="PARAM_DT" spirit:left="0" spirit:right="0" />
- <spirit:internalPortReference spirit:componentRef="hwn_nd_3" spirit:portRef="PARAM_DT" spirit:left="0" spirit:right="0" />
- <spirit:internalPortReference spirit:componentRef="control_if" spirit:portRef="PARAM_DT" spirit:left="0" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>PARAM_LD</spirit:name>
- <spirit:internalPortReference spirit:componentRef="hwn_nd_1" spirit:portRef="PARAM_LD" />
- <spirit:internalPortReference spirit:componentRef="hwn_nd_2" spirit:portRef="PARAM_LD" />
- <spirit:internalPortReference spirit:componentRef="hwn_nd_3" spirit:portRef="PARAM_LD" />
- <spirit:internalPortReference spirit:componentRef="control_if" spirit:portRef="PARAM_LD" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>PARAMETERS</spirit:name>
- <spirit:internalPortReference spirit:componentRef="control_if" spirit:portRef="PARAMETERS_IN" spirit:left="0" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>PARAMETERS_LD</spirit:name>
- <spirit:internalPortReference spirit:componentRef="control_if" spirit:portRef="PARAMETERS_IN_LD" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>address</spirit:name>
- <spirit:internalPortReference spirit:componentRef="register_rf" spirit:portRef="address" spirit:left="18" spirit:right="0" />
- <spirit:externalPortReference spirit:portRef="address" spirit:left="18" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>read_data</spirit:name>
- <spirit:internalPortReference spirit:componentRef="register_rf" spirit:portRef="read_data" spirit:left="31" spirit:right="0" />
- <spirit:externalPortReference spirit:portRef="read_data" spirit:left="31" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>write_data</spirit:name>
- <spirit:internalPortReference spirit:componentRef="register_rf" spirit:portRef="write_data" spirit:left="31" spirit:right="0" />
- <spirit:externalPortReference spirit:portRef="write_data" spirit:left="31" spirit:right="0" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>read_en</spirit:name>
- <spirit:internalPortReference spirit:componentRef="register_rf" spirit:portRef="read_en" />
- <spirit:externalPortReference spirit:portRef="read_en" />
- </spirit:adHocConnection>
- <spirit:adHocConnection>
- <spirit:name>write_en</spirit:name>
- <spirit:internalPortReference spirit:componentRef="register_rf" spirit:portRef="write_en" />
- <spirit:externalPortReference spirit:portRef="write_en" />
- </spirit:adHocConnection>
- </spirit:adHocConnections>
- <spirit:hierConnections>
- <spirit:hierConnection spirit:interfaceRef="data_in">
- <spirit:activeInterface spirit:componentRef="hwn_nd_1" spirit:busRef="data_in"/>
- </spirit:hierConnection>
- <spirit:hierConnection spirit:interfaceRef="data_out">
- <spirit:activeInterface spirit:componentRef="hwn_nd_3" spirit:busRef="data_out"/>
- </spirit:hierConnection>
- </spirit:hierConnections>
-</spirit:design>
diff --git a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/system.xml b/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/system.xml
deleted file mode 100644
index 33e79a2f4e246045b59597e2c5ed2c46042c1237..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/ipxact/compaandesign.com/system.xml
+++ /dev/null
@@ -1,26 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
-<!--
-// Copyright 2009 Compaan Design bv, The Netherlands
-// All rights, including copyrights, reserved.
-// www.compaandesign.com
-//
-// THIS WORK FORMS PART OF A SPIRIT CONSORTIUM SPECIFICATION.
-// USE OF THESE MATERIALS ARE GOVERNED BY
-// THE LEGAL TERMS AND CONDITIONS OUTLINED IN THE SPIRIT
-// SPECIFICATION DISCLAIMER AVAILABLE FROM
-// www.spiritconsortium.org
-//
-// This source file is provided on an AS IS basis. The SPIRIT Consortium disclaims
-// ANY WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF
-// MERCHANTABILITY AND FITNESS FOR USE FOR A PARTICULAR PURPOSE.
-// The user of the source file shall indemnify and hold The SPIRIT Consortium harmless
-// from any damages or liability arising out of the use thereof or the performance or
-// implementation or partial implementation of the schema.
--->
-<spirit:designConfiguration xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4/index.xsd" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>compaandesign.com</spirit:vendor>
- <spirit:library>ipcore2RTL</spirit:library>
- <spirit:name>design_system</spirit:name>
- <spirit:version>1</spirit:version>
- <spirit:designRef spirit:vendor="compaandesign.com" spirit:library="ipcore2RTL" spirit:name="ipcore" spirit:version="1"/>
-</spirit:designConfiguration>
diff --git a/applications/compaan/libraries/ipcore_trace/script_altera.tcl b/applications/compaan/libraries/ipcore_trace/script_altera.tcl
deleted file mode 100644
index 92ef236ae8c91d065f88f6adc964cc0bec7c1ae2..0000000000000000000000000000000000000000
--- a/applications/compaan/libraries/ipcore_trace/script_altera.tcl
+++ /dev/null
@@ -1,37 +0,0 @@
-set case "ipcore"
-set buildDir "."
-
-set winOS [string compare -nocase -length 3 $env(os.name) "win" ]
-set linuxOS [string compare -nocase -length 3 $env(os.name) "lin" ]
-
-file delete -force ipxact
-file delete -force vhdl
-file delete -force traces
-file delete -force altera
-
-set cwd [ pwd ]
-puts "Starting Compaan Compiler in directory: $cwd"
-
-cfront -f "${buildDir}/${case}.c" -o "${buildDir}" --tosc "${case}_main.c"
-
-set p [file exists ${case}_outline_keep.xml ]
-if {$p == 1} {
- puts "COPY OUTLINE IN"
- file delete ${case}_outline.xml
- file copy ${case}_outline_keep.xml ${case}_outline.xml
-}
-
-dfanalyzer -f "${buildDir}/${case}.ast" -o "${buildDir}/${case}.sac" --outline "${buildDir}/${case}_outline.xml" --optimize --performance
-polybuilder -f "${buildDir}/${case}.sac" -o "${buildDir}/${case}.rdg" --remove-control
-kpnbuilder -f "${buildDir}/${case}.rdg" -o "${buildDir}/${case}.bld" --outline "${buildDir}/${case}_outline.xml"
-kpntransform -f "${buildDir}/${case}.bld" -o "${buildDir}/${case}.trn" -s -d -M -m -S --nooomx
-kpnratematcher -f "${buildDir}/${case}.trn" -o "${buildDir}/${case}.kpn" -x
-tracebuilder -f "${buildDir}/${case}.ast" -o "${buildDir}/traces/${case}.trc" --outline "${buildDir}/${case}_outline.xml"
-kpnmapper -k "${buildDir}/${case}.kpn" -o "${buildDir}/ipxact" --outline "${buildDir}/${case}_outline.xml" --trace "${buildDir}/traces/${case}.trc" --property simtime=100000 --ipxact
-archgen --genaltera -f "${buildDir}/ipxact/compaandesign.com/system.xml" -o "${buildDir}/astron" --repository c:/Users/Bart/projects/ --test
-
-#cd altera
-#if { [catch { exec c:/altera/14.1/modelsim_ae/win32aloem/vsim -c -do modelsim_system.do}] } {
-# puts "$::errorInfo\n"
-#}
-#cd ..
\ No newline at end of file
diff --git a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
index ed813c89479b738a9e0520dad9d75085851a0dff..1d9ddb1c1d1eb3288c172fd31f57cef95f7d0099 100644
--- a/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
+++ b/applications/compaan/libraries/src/vhdl/compaandesign_com/ipcore2RTL/hwn_nd_3/1/ipcore2RTL_hwn_nd_3.vhd
@@ -360,6 +360,7 @@ begin
WRITE_ST => sl_write_st(0)
);
--
+ --data_out_Dout <= sl_out_port_0; -- Func. Output param. "tmp0"
data_out_Dout <= PARAM_DT; -- Func. Output param. "tmp0"
data_out_CTRL <= sl_sof_wr ;
data_out_Wr <= sl_WRITES(0);