diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
index 7d51b6de5106aa1aba3e13cdbc4d1f0111a39cff..682eae39fa5f7eb2d91ef0ce9eef37adbbf1025b 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream.vhd
@@ -48,10 +48,6 @@ ENTITY ddr_stream IS
ddr_ref_clk : IN STD_LOGIC;
ddr_ref_rst : IN STD_LOGIC;
- -- Clock outputs
- ddr_out_clk : OUT STD_LOGIC;
- ddr_out_rst : OUT STD_LOGIC;
-
-- MM interface
reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_io_ddr_miso : OUT t_mem_miso;
@@ -72,10 +68,6 @@ ENTITY ddr_stream IS
reg_diag_rx_seq_mosi : IN t_mem_mosi;
reg_diag_rx_seq_miso : OUT t_mem_miso;
- -- DDR3 pass on termination control from master to slave controller
- term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
- term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
-
-- SO-DIMM Memory Bank I = ddr3_I
phy_3_in : IN t_tech_ddr3_phy_in;
phy_3_io : INOUT t_tech_ddr3_phy_io;
@@ -86,27 +78,18 @@ END ddr_stream;
ARCHITECTURE str OF ddr_stream IS
- CONSTANT c_wr_data_w : NATURAL := g_st_dat_w;
- CONSTANT c_rd_data_w : NATURAL := g_st_dat_w;
CONSTANT c_data_w : NATURAL := g_st_dat_w;
CONSTANT c_wr_fifo_depth : NATURAL := 1024; -- >=16 , defined at DDR side of the FIFO.
CONSTANT c_rd_fifo_depth : NATURAL := 1024; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
- CONSTANT c_use_bg : BOOLEAN := FALSE;
- CONSTANT c_use_tx_seq : BOOLEAN := TRUE;
CONSTANT c_use_db : BOOLEAN := FALSE;
- CONSTANT c_use_rx_seq : BOOLEAN := TRUE;
CONSTANT c_buf_nof_data : NATURAL := 1024;
- CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_seq_dat_w : NATURAL := 16;
- SIGNAL en_sync : STD_LOGIC;
-
- SIGNAL out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
- SIGNAL out_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0); -- Output SOSI that contains the waveform data
- SIGNAL in_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); -- Default xon='1'
- SIGNAL in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL en_sync : STD_LOGIC;
+ SIGNAL ctlr_clk : STD_LOGIC;
+ SIGNAL ctlr_rst : STD_LOGIC;
BEGIN
@@ -141,11 +124,11 @@ BEGIN
ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk,
- ctlr_rst_out => ddr_out_rst,
+ ctlr_clk_out => ctlr_clk,
+ ctlr_rst_out => ctlr_rst,
- ctlr_clk_in => dp_clk,
- ctlr_rst_in => dp_rst,
+ ctlr_clk_in => ctlr_clk,
+ ctlr_rst_in => ctlr_rst,
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
@@ -155,9 +138,9 @@ BEGIN
wr_fifo_usedw => OPEN,
rd_fifo_usedw => OPEN,
- -- DDR3 pass on termination control from master to slave controller
- term_ctrl_out => term_ctrl_out,
- term_ctrl_in => term_ctrl_in,
+ -- DDR3 pass on signals from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
-- DDR3 PHY external interface
phy3_in => phy_3_in,
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 99361ae5bb7070cbfed07d6b606466a82e4afb1e..aba251b9d3e53bdc5ad33af98f67711efc713f38 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -123,10 +123,12 @@ ARCHITECTURE str OF unb1_test IS
CONSTANT c_use_back : BOOLEAN := FALSE; -- however SI_FN_[0..2] do connect to copper connectors of single board unb
-- Revision controlled constants
- CONSTANT c_use_1GbE : BOOLEAN := g_design_name="unb1_test_1GbE" OR g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
- CONSTANT c_use_10GbE : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
- CONSTANT c_use_ddr_MB_I : BOOLEAN := g_design_name="unb1_test_ddr_MB_I" OR g_design_name="unb1_test_ddr_MB_I_II" OR g_design_name="unb1_test_all";
- CONSTANT c_use_ddr_MB_II : BOOLEAN := g_design_name="unb1_test_ddr_MB_II" OR g_design_name="unb1_test_ddr_MB_I_II" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_1GbE : BOOLEAN := g_design_name="unb1_test_1GbE" OR g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_10GbE : BOOLEAN := g_design_name="unb1_test_10GbE" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_ddr_4g_MB_I : BOOLEAN := g_design_name="unb1_test_ddr_MB_I" OR g_design_name="unb1_test_ddr_MB_I_II" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_ddr_4g_MB_II : BOOLEAN := g_design_name="unb1_test_ddr_MB_II" OR g_design_name="unb1_test_ddr_MB_I_II" OR g_design_name="unb1_test_all";
+ CONSTANT c_use_ddr_16g_MB_I : BOOLEAN := g_design_name="unb1_test_ddr_16g_MB_I" OR g_design_name="unb1_test_ddr_16g_MB_I_II";
+ CONSTANT c_use_ddr_16g_MB_II : BOOLEAN := g_design_name="unb1_test_ddr_16g_MB_II" OR g_design_name="unb1_test_ddr_16g_MB_I_II";
-- max useful peripherals (FIXME read these constants from board lib)
@@ -135,8 +137,8 @@ ARCHITECTURE str OF unb1_test IS
-- ddr
CONSTANT c_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- CONSTANT c_use_MB_I : NATURAL := sel_a_b(c_use_ddr_MB_I,1,0); -- 1: use MB_I 0: do not use
- CONSTANT c_use_MB_II : NATURAL := sel_a_b(c_use_ddr_MB_II,1,0); -- 1: use MB_II 0: do not use
+ CONSTANT c_use_MB_I : NATURAL := sel_a_b((c_use_ddr_4g_MB_I OR c_use_ddr_16g_MB_I),1,0); -- 1: use MB_I 0: do not use
+ CONSTANT c_use_MB_II : NATURAL := sel_a_b((c_use_ddr_4g_MB_II OR c_use_ddr_16g_MB_II),1,0); -- 1: use MB_II 0: do not use
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1,
sel_a_b(c_use_front,1, 0),
@@ -155,8 +157,10 @@ ARCHITECTURE str OF unb1_test IS
CONSTANT c_data_w_64 : NATURAL := c_xgmii_data_w; -- 10GbE
-- ddr
- CONSTANT c_ddr_master : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
- CONSTANT c_ddr_slave : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_slave;
+ CONSTANT c_ddr_4g_master : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master;
+ CONSTANT c_ddr_16g_master : t_c_tech_ddr := c_tech_ddr3_16g_dual_rank_800m;
+ CONSTANT c_ddr_4g_slave : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_slave;
+
-- Block generator constants
CONSTANT c_bg_block_size : NATURAL := 900;
@@ -358,7 +362,7 @@ ARCHITECTURE str OF unb1_test IS
-- DDR3 pass on termination control from master to slave controller
SIGNAL term_ctrl_out : t_tech_ddr3_phy_terminationcontrol;
- SIGNAL term_ctrl_in : t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
+ SIGNAL term_ctrl_in : t_tech_ddr3_phy_terminationcontrol;
BEGIN
@@ -390,7 +394,7 @@ BEGIN
g_aux => c_unb1_board_aux,
g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => TRUE,
+ g_dp_clk_use_pll => FALSE,
g_xo_clk_use_pll => TRUE
)
PORT MAP (
@@ -410,8 +414,8 @@ BEGIN
epcs_clk => epcs_clk,
epcs_clk_out => epcs_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => OPEN,
+ dp_clk => OPEN,
dp_pps => OPEN,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
@@ -497,9 +501,7 @@ BEGIN
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-
- --dp_clk <= CLK;
- --dp_rst <= mm_rst;
+-- END GENERATE;
-----------------------------------------------------------------------------
-- MM master
@@ -886,13 +888,53 @@ BEGIN
END GENERATE;
END GENERATE;
+ gen_ddr_stream_4g_MB_I : IF c_use_ddr_4g_MB_I = TRUE GENERATE
+ u_ddr_stream_4g_MB_I : ENTITY work.ddr_stream
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_tech_ddr => c_ddr_4g_master,
+ g_st_dat_w => c_data_w_64
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- blockgen mm
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- SO-DIMM Memory Bank
+ phy_3_in => MB_I_IN,
+ phy_3_io => MB_I_IO,
+ phy_3_ou => MB_I_OU
+ );
+ END GENERATE;
- gen_ddr_stream_MB_I : IF c_use_ddr_MB_I = TRUE GENERATE
- u_ddr_stream_MB_I : ENTITY work.ddr_stream
+ gen_ddr_stream_4g_MB_II : IF c_use_ddr_4g_MB_II = TRUE GENERATE
+ u_ddr_stream_4g_MB_II : ENTITY work.ddr_stream
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
- g_tech_ddr => c_ddr_master,
+ g_tech_ddr => c_ddr_4g_master,
g_st_dat_w => c_data_w_64
)
PORT MAP (
@@ -905,9 +947,46 @@ BEGIN
ddr_ref_clk => CLK,
ddr_ref_rst => ddr_ref_rst,
- -- Clock outputs
- ddr_out_clk => OPEN,
- ddr_out_rst => OPEN,
+ -- blockgen mm
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- SO-DIMM Memory Bank
+ phy_3_in => MB_II_IN,
+ phy_3_io => MB_II_IO,
+ phy_3_ou => MB_II_OU
+ );
+ END GENERATE;
+
+ gen_ddr_stream_16g_MB_I : IF c_use_ddr_16g_MB_I = TRUE GENERATE
+ u_ddr_stream_16g_MB_I : ENTITY work.ddr_stream
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_tech_ddr => c_ddr_16g_master,
+ g_st_dat_w => c_data_w_64
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
-- blockgen mm
reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
@@ -925,10 +1004,6 @@ BEGIN
reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
- -- DDR3 pass on termination control from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
-- SO-DIMM Memory Bank
phy_3_in => MB_I_IN,
phy_3_io => MB_I_IO,
@@ -936,12 +1011,12 @@ BEGIN
);
END GENERATE;
- gen_ddr_stream_MB_II : IF c_use_ddr_MB_II = TRUE GENERATE
- u_ddr_stream_MB_II : ENTITY work.ddr_stream
+ gen_ddr_stream_16g_MB_II : IF c_use_ddr_16g_MB_II = TRUE GENERATE
+ u_ddr_stream_16g_MB_II : ENTITY work.ddr_stream
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
- g_tech_ddr => c_ddr_master,
+ g_tech_ddr => c_ddr_16g_master,
g_st_dat_w => c_data_w_64
)
PORT MAP (
@@ -954,10 +1029,6 @@ BEGIN
ddr_ref_clk => CLK,
ddr_ref_rst => ddr_ref_rst,
- -- Clock outputs
- ddr_out_clk => OPEN,
- ddr_out_rst => OPEN,
-
-- blockgen mm
reg_diag_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
reg_diag_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
@@ -974,10 +1045,6 @@ BEGIN
reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
- -- DDR3 pass on termination control from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
-- SO-DIMM Memory Bank
phy_3_in => MB_II_IN,
phy_3_io => MB_II_IO,