diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd
index 2d358352c2e3aedba69d1a6093fceabc66ddd262..2d31350834b0724da55a52ff43f73542b7a16a59 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd
@@ -40,7 +40,7 @@ ENTITY tb_tech_mac_10_receiver IS
PORT (
mm_init : IN STD_LOGIC;
total_header : IN t_network_total_header;
- clk_156 : IN STD_LOGIC;
+ rx_clk : IN STD_LOGIC;
rx_sosi : IN t_dp_sosi;
rx_siso : OUT t_dp_siso;
rx_toggle : OUT STD_LOGIC -- toggle after every received packet
@@ -59,12 +59,12 @@ BEGIN
rx_siso <= c_dp_siso_hold;
WHILE mm_init/='0' LOOP
- WAIT UNTIL rising_edge(clk_156);
+ WAIT UNTIL rising_edge(rx_clk);
END LOOP;
-- Receive forever
WHILE TRUE LOOP
- proc_tech_mac_10g_rx_packet(total_header, g_data_type, clk_156, rx_sosi, rx_siso);
+ proc_tech_mac_10g_rx_packet(total_header, g_data_type, rx_clk, rx_sosi, rx_siso);
i_rx_toggle <= NOT i_rx_toggle;
END LOOP;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd
index 16510cfde03df0a6b9296ac89ba014846509cbaa..7c857af61fee0d2e66304bf176aa774e7bf76bdc 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd
@@ -57,7 +57,7 @@ ENTITY tb_tech_mac_10g_transmitter IS
PORT (
mm_init : IN STD_LOGIC;
total_header : IN t_network_total_header;
- clk_156 : IN STD_LOGIC;
+ tx_clk : IN STD_LOGIC;
tx_siso : IN t_dp_siso;
tx_sosi : OUT t_dp_sosi;
link_fault : OUT STD_LOGIC;
@@ -84,8 +84,8 @@ BEGIN
link_fault <= '0';
tx_sosi <= c_dp_sosi_rst;
- proc_common_wait_until_low(clk_156, mm_init);
- proc_common_wait_some_cycles(clk_156, 10);
+ proc_common_wait_until_low(tx_clk, mm_init);
+ proc_common_wait_some_cycles(tx_clk, 10);
-- Loopback txp->rxp so use promiscuous mode or use DST_MAC = c_src_mac to send to itself
@@ -95,28 +95,28 @@ BEGIN
-- . For I>46 the payload length is I and empty = 4 - (I mod 4)
FOR I IN 0 TO c_nof_pkt1-1 LOOP
- proc_tech_mac_10g_tx_packet(total_header, g_pkt_length_arr1(I), g_data_type, c_rl, c_nof_tx_not_valid, clk_156, tx_en, tx_siso, tx_sosi);
- proc_common_wait_some_cycles(clk_156, 0);
+ proc_tech_mac_10g_tx_packet(total_header, g_pkt_length_arr1(I), g_data_type, c_rl, c_nof_tx_not_valid, tx_clk, tx_en, tx_siso, tx_sosi);
+ proc_common_wait_some_cycles(tx_clk, 0);
END LOOP;
- proc_common_wait_some_cycles(clk_156, g_pkt_length_arr1(c_nof_pkt1-1)/c_tech_mac_10g_symbols_per_beat);
- proc_common_wait_some_cycles(clk_156, 100);
+ proc_common_wait_some_cycles(tx_clk, g_pkt_length_arr1(c_nof_pkt1-1)/c_tech_mac_10g_symbols_per_beat);
+ proc_common_wait_some_cycles(tx_clk, 100);
IF g_verify_link_recovery=TRUE THEN
-- Model a link fault to verify Rx recovery
link_fault <= '1';
- proc_common_wait_some_cycles(clk_156, 1000);
+ proc_common_wait_some_cycles(tx_clk, 1000);
-- Remove the link fault and wait for tx_siso.xon to recover
link_fault <= '0';
- proc_common_wait_some_cycles(clk_156, 500);
+ proc_common_wait_some_cycles(tx_clk, 500);
FOR I IN 0 TO c_nof_pkt2-1 LOOP
- proc_tech_mac_10g_tx_packet(total_header, g_pkt_length_arr2(I), g_data_type, c_rl, c_nof_tx_not_valid, clk_156, tx_en, tx_siso, tx_sosi);
- proc_common_wait_some_cycles(clk_156, 0);
+ proc_tech_mac_10g_tx_packet(total_header, g_pkt_length_arr2(I), g_data_type, c_rl, c_nof_tx_not_valid, tx_clk, tx_en, tx_siso, tx_sosi);
+ proc_common_wait_some_cycles(tx_clk, 0);
END LOOP;
- proc_common_wait_some_cycles(clk_156, g_pkt_length_arr2(c_nof_pkt2-1)/c_tech_mac_10g_symbols_per_beat);
- proc_common_wait_some_cycles(clk_156, 100);
+ proc_common_wait_some_cycles(tx_clk, g_pkt_length_arr2(c_nof_pkt2-1)/c_tech_mac_10g_symbols_per_beat);
+ proc_common_wait_some_cycles(tx_clk, 100);
END IF;
tx_end <= '1';
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
index 088c3775de684998e62bb57005336314987f443c..cb4dedbbc773ec58eadd953329812d26caf6256a 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
@@ -38,10 +38,10 @@ ENTITY tb_tech_mac_10_verify_rx_at_eop IS
g_pkt_length_arr : t_nat_natural_arr
);
PORT (
- tx_clk_156 : IN STD_LOGIC;
- tx_sosi : IN t_dp_sosi;
- rx_clk_156 : IN STD_LOGIC;
- rx_sosi : IN t_dp_sosi
+ tx_clk : IN STD_LOGIC;
+ tx_sosi : IN t_dp_sosi;
+ rx_clk : IN STD_LOGIC;
+ rx_sosi : IN t_dp_sosi
);
END tb_tech_mac_10_verify_rx_at_eop;
@@ -54,10 +54,10 @@ ARCHITECTURE tb OF tb_tech_mac_10_verify_rx_at_eop IS
BEGIN
- p_ff_store_tx_at_eop : PROCESS(tx_clk_156)
+ p_ff_store_tx_at_eop : PROCESS(tx_clk)
VARIABLE vI : NATURAL := 0;
BEGIN
- IF rising_edge(tx_clk_156) THEN
+ IF rising_edge(tx_clk) THEN
IF tx_sosi.eop='1' THEN
expected_sosi_arr(vI) <= tx_sosi;
vI := vI +1;
@@ -65,11 +65,11 @@ BEGIN
END IF;
END PROCESS;
- p_ff_verify_rx_at_eop : PROCESS(rx_clk_156)
+ p_ff_verify_rx_at_eop : PROCESS(rx_clk)
VARIABLE vI : NATURAL := 0;
VARIABLE vLow : NATURAL := 0;
BEGIN
- IF rising_edge(rx_clk_156) THEN
+ IF rising_edge(rx_clk) THEN
rx_sosi_reg <= rx_sosi; -- use rx_sosi_reg for verification at eop to account for once cycle latency in expected_sosi_arr()
IF rx_sosi_reg.eop='1' THEN
IF g_no_padding=FALSE AND g_pkt_length_arr(vI) < 64 - 14 - 20 - 8 - 4 THEN -- = minimum frame 64 - ETH 14 - IP 20 - UDP 8 - CRC 4
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
index 7bdfe3715468a7a69c3fa2d89233e40c35008f46..80c282f88b14e95c9160c8f06ab037c834a8dfc0 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
@@ -34,13 +34,13 @@ ENTITY tb_tech_mac_10g_verify_rx_pkt_cnt IS
g_nof_pkt : NATURAL
);
PORT (
- tx_clk_156 : IN STD_LOGIC;
- tx_sosi : IN t_dp_sosi;
- rx_clk_156 : IN STD_LOGIC;
- rx_sosi : IN t_dp_sosi;
- tx_pkt_cnt : OUT NATURAL;
- rx_pkt_cnt : OUT NATURAL;
- rx_end : IN STD_LOGIC
+ tx_clk : IN STD_LOGIC;
+ tx_sosi : IN t_dp_sosi;
+ rx_clk : IN STD_LOGIC;
+ rx_sosi : IN t_dp_sosi;
+ tx_pkt_cnt : OUT NATURAL;
+ rx_pkt_cnt : OUT NATURAL;
+ rx_end : IN STD_LOGIC
);
END tb_tech_mac_10g_verify_rx_pkt_cnt;
@@ -56,8 +56,8 @@ BEGIN
rx_pkt_cnt <= i_rx_pkt_cnt;
-- Verification
- i_tx_pkt_cnt <= i_tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(tx_clk_156);
- i_rx_pkt_cnt <= i_rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(rx_clk_156);
+ i_tx_pkt_cnt <= i_tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(tx_clk);
+ i_rx_pkt_cnt <= i_rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(rx_clk);
p_verify_pkt_cnt : PROCESS
BEGIN