diff --git a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
index 26f0149aebbb30e122f8f6f2acd38a08d039312e..6887bc5945003241b077a77c59bcd60b1909dba9 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram_reg.vhd
@@ -72,7 +72,6 @@ ARCHITECTURE rtl OF st_histogram_reg IS
                                   nof_dat  => c_nof_addresses,
                                   init_sl  => '0');                                              
 
-  SIGNAL mm_ram_clear    : STD_LOGIC; 
   SIGNAL mm_ram_clearing : STD_LOGIC; 
 
   SIGNAL mm_ram_fill_inst : STD_LOGIC_VECTOR(ceil_log2(g_nof_instances)-1 DOWNTO 0);
@@ -95,7 +94,6 @@ BEGIN
       reg_miso <= c_mem_miso_rst;
       
       -- Access event, register values
-      mm_ram_clear <= '0';
       mm_ram_fill <= '0';
       mm_ram_fill_inst <= (OTHERS=>'0');
  
@@ -104,14 +102,11 @@ BEGIN
       reg_miso.rdval <= '0';
       
       -- Access event defaults
-      mm_ram_clear <= '0';
       mm_ram_fill  <= '0';
       
       -- Write access: set register value
       IF reg_mosi.wr = '1' THEN
         CASE TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
-          WHEN 0 =>
-            mm_ram_clear <= '1';
           WHEN 1 =>
             mm_ram_fill_inst <= reg_mosi.wrdata(ceil_log2(g_nof_instances)-1 DOWNTO 0);
           WHEN 2 =>
@@ -181,21 +176,6 @@ BEGIN
     dout => mm_ram_filling
   );
 
-  -- MM --> ST
-  u_common_spulse_clear : ENTITY common_lib.common_spulse
-  PORT MAP (
-    in_clk    => mm_clk,
-    in_rst    => mm_rst,
-
-    in_pulse  => mm_ram_clear,
-    in_busy   => OPEN,
-
-    out_clk   => dp_clk,
-    out_rst   => dp_rst,
-
-    out_pulse => ram_clear
-  );
-
   u_common_spulse_fill : ENTITY common_lib.common_spulse
   PORT MAP (
     in_clk    => mm_clk,