From 37b92e7f2bb44e1f6490ede0a19aac3fcff83d1d Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 8 Jan 2015 13:01:10 +0000
Subject: [PATCH] Pass on local_init_done from IP via ctlr_miso.done instead of
via separate signal ctlr_init_done.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 6 ------
libraries/io/ddr/src/vhdl/io_ddr_driver.vhd | 12 ++++++------
libraries/technology/ddr/tech_ddr.vhd | 8 --------
libraries/technology/ddr/tech_ddr_stratixiv.vhd | 16 ++++++++++++----
4 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 2298d1363c..80fbd7a884 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -85,7 +85,6 @@
-- rd_fifo_usedw <---|widths | . |_______| . |______|---\
-- |________| . . |
-- ctlr_rd_src ctlr_miso |
--- ctlr_init_done |
-- |
-- ctlr_clk /------ctlr_clk_in -------> |
-- \------ctlr_clk_out-----------------------------------------------/
@@ -185,8 +184,6 @@ ARCHITECTURE str OF io_ddr IS
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
- SIGNAL ctlr_init_done : STD_LOGIC;
-
SIGNAL ctlr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
SIGNAL ctlr_miso : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
@@ -369,7 +366,6 @@ BEGIN
rd_src_out => ctlr_rd_src_out,
rd_src_in => ctlr_rd_src_in,
- ctlr_init_done => ctlr_init_done,
ctlr_miso => ctlr_miso,
ctlr_mosi => ctlr_mosi
);
@@ -390,8 +386,6 @@ BEGIN
ctlr_gen_clk_2x => OPEN,
ctlr_gen_rst_2x => OPEN,
- ctlr_init_done => ctlr_init_done,
-
ctlr_mosi => ctlr_mosi,
ctlr_miso => ctlr_miso,
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
index 926ae5e64f..80cdc38fcd 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
@@ -62,7 +62,6 @@ ENTITY io_ddr_driver IS
rd_src_out : OUT t_dp_sosi;
rd_src_in : IN t_dp_siso;
- ctlr_init_done : IN STD_LOGIC;
ctlr_miso : IN t_mem_ctlr_miso;
ctlr_mosi : OUT t_mem_ctlr_mosi
);
@@ -141,9 +140,10 @@ BEGIN
rd_src_out.valid <= ctlr_miso.rdval;
rd_src_out.data <= RESIZE_DP_DATA(ctlr_miso.rddata);
- p_state : PROCESS(prev_state, state, ctlr_init_done,
- dvr_en, dvr_wr_not_rd, ctlr_miso, wr_snk_in, rd_src_in,
- burst_size, burst_wr_cnt, dvr_start_address, cur_address, address_cnt)
+ p_state : PROCESS(prev_state, state,
+ dvr_en, dvr_wr_not_rd, dvr_start_address, dvr_nof_data,
+ ctlr_miso, wr_snk_in, rd_src_in,
+ burst_size, burst_wr_cnt, cur_address, address_cnt)
BEGIN
nxt_state <= state;
@@ -238,8 +238,8 @@ BEGIN
WHEN OTHERS => -- s_init
nxt_dvr_done <= '0';
- IF ctlr_init_done = '1' THEN
- nxt_state <= s_idle; -- and assert dvr_done when in s_idle to indicate ctlr_init_done
+ IF ctlr_miso.done = '1' THEN
+ nxt_state <= s_idle; -- and assert dvr_done when in s_idle to indicate ctlr_miso.done
END IF;
END CASE;
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index c13dcec25f..e6c138b97f 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -23,11 +23,6 @@
-- Purpose: Technology independent component for DDR memory access.
-- Description:
-- The component also supports different types of DDR, so DDR3 and DDR4.
--- Remarks:
--- . The ctlr_init_done goes high after power up. It could have been AND-ed
--- with ctlr_miso.waitrequest_n to avoid having it as a port. However the
--- timing closure for ctlr_miso.waitrequest_n can be critical, so therefore
--- it is better not to combinatorially load it with the AND ctlr_init_done.
LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -52,8 +47,6 @@ ENTITY tech_ddr IS
ctlr_gen_clk_2x : OUT STD_LOGIC;
ctlr_gen_rst_2x : OUT STD_LOGIC;
- ctlr_init_done : OUT STD_LOGIC;
-
ctlr_mosi : IN t_mem_ctlr_mosi;
ctlr_miso : OUT t_mem_ctlr_miso;
@@ -74,7 +67,6 @@ BEGIN
GENERIC MAP (g_tech_ddr)
PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
- ctlr_init_done,
ctlr_mosi, ctlr_miso,
phy_in, phy_io, phy_ou);
END GENERATE;
diff --git a/libraries/technology/ddr/tech_ddr_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
index cb627df48f..f95ae40138 100644
--- a/libraries/technology/ddr/tech_ddr_stratixiv.vhd
+++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
@@ -20,6 +20,16 @@
--
--------------------------------------------------------------------------------
+
+-- Purpose: DDR3 memory access component for Stratix IV.
+-- Description:
+-- Remarks:
+-- . The local_init_done goes high some time after power up. It could have been
+-- AND-ed with ctlr_miso.waitrequest_n. However the timing closure for
+-- ctlr_miso.waitrequest_n can be critical, so therefore it is better not
+-- to combinatorially load it with the AND local_init_done. Instead a
+-- ctlr_miso.done field was added and used to pass on local_init_done.
+
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib;
LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
@@ -46,8 +56,6 @@ ENTITY tech_ddr_stratixiv IS
ctlr_gen_clk_2x : OUT STD_LOGIC;
ctlr_gen_rst_2x : OUT STD_LOGIC;
- ctlr_init_done : OUT STD_LOGIC;
-
ctlr_mosi : IN t_mem_ctlr_mosi;
ctlr_miso : OUT t_mem_ctlr_miso;
@@ -111,7 +119,7 @@ BEGIN
avl_read_req => ctlr_mosi.rd, -- .read
avl_write_req => ctlr_mosi.wr, -- .write
avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
- local_init_done => ctlr_init_done, -- status.local_init_done
+ local_init_done => ctlr_miso.done, -- status.local_init_done
local_cal_success => OPEN, -- .local_cal_success
local_cal_fail => OPEN, -- .local_cal_fail
oct_rdn => phy_in.oct_rdn, -- oct.rdn
@@ -163,7 +171,7 @@ BEGIN
avl_read_req => ctlr_mosi.rd, -- .read
avl_write_req => ctlr_mosi.wr, -- .write
avl_size => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
- local_init_done => ctlr_init_done, -- status.local_init_done
+ local_init_done => ctlr_miso.done, -- status.local_init_done
local_cal_success => OPEN, -- .local_cal_success
local_cal_fail => OPEN, -- .local_cal_fail
seriesterminationcontrol => phy_in.seriesterminationcontrol(g_tech_ddr.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
--
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