diff --git a/applications/lofar2/libraries/ddrctrl/hdllib.cfg b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
index 8f92d2ddd3f4d347fdfc32811cdbcefd07fe0288..ba8457f096cdfc6b3e1bbefff4d1fedc16d69766 100644
--- a/applications/lofar2/libraries/ddrctrl/hdllib.cfg
+++ b/applications/lofar2/libraries/ddrctrl/hdllib.cfg
@@ -1,19 +1,21 @@
hdl_lib_name = lofar2_ddrctrl
hdl_library_clause_name = lofar2_ddrctrl_lib
-hdl_lib_uses_synth = technology common tech_ddr dp
+hdl_lib_uses_synth = technology common tech_ddr dp io_ddr
hdl_lib_uses_sim =
hdl_lib_technology =
synth_files =
- src/vhdl/ddrctrl_address_counter.vhd
- src/vhdl/ddrctrl_pack.vhd
- src/vhdl/ddrctrl_repack.vhd
+ src/vhdl/ddrctrl_input_address_counter.vhd
+ src/vhdl/ddrctrl_input_pack.vhd
+ src/vhdl/ddrctrl_input_repack.vhd
+ src/vhdl/ddrctrl_input.vhd
src/vhdl/ddrctrl.vhd
test_bench_files =
- tb/vhdl/tb_ddrctrl_address_counter.vhd
- tb/vhdl/tb_ddrctrl_pack.vhd
- tb/vhdl/tb_ddrctrl_repack.vhd
+ tb/vhdl/tb_ddrctrl_input_address_counter.vhd
+ tb/vhdl/tb_ddrctrl_input_pack.vhd
+ tb/vhdl/tb_ddrctrl_input_repack.vhd
+ tb/vhdl/tb_ddrctrl_input.vhd
tb/vhdl/tb_ddrctrl.vhd
regression_test_vhdl =
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 838e8f5c89576d1b3a336d91e8d2ab180e863269..8b0b96df15aafa155ad6bdc7dde31ca491df09d1 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -32,29 +32,49 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
-- The maximum value of the address is determend by g_tech_ddr.
-LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE io_ddr_lib.ALL;
ENTITY ddrctrl IS
GENERIC (
- g_tech_ddr : t_c_tech_ddr; -- type of memory
- g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
- g_nof_streams : NATURAL := 12; -- number of input streams
- g_data_w : NATURAL := 14 -- data with of input data vectors
- );
+ g_tech_ddr : t_c_tech_ddr; -- type of memory
+ g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
+ g_technology : NATURAL := c_tech_select_default;
+ g_nof_streams : NATURAL := 12; -- number of input streams
+ g_data_w : NATURAL := 14 -- data with of input data vectors
+ );
PORT (
- clk : IN STD_LOGIC := '0';
+ clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
- in_sosi_arr : IN t_dp_sosi_arr; -- input data
- out_of : OUT NATURAL; -- amount of internal overflow this output
- out_mosi : OUT t_mem_ctlr_mosi -- output data
+ mm_clk : IN STD_LOGIC := '0';
+ mm_rst : IN STD_LOGIC := '0';
+ in_sosi_arr : IN t_dp_sosi_arr; -- input data
+ wr_not_rd : IN STD_LOGIC := '0';
+ out_of : OUT NATURAL; -- amount of internal overflow this output
+ out_adr : OUT NATURAL;
+
+
+ term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
+ term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
+
+ -- DDR3 PHY external interface
+ phy3_in : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
+ phy3_io : INOUT t_tech_ddr3_phy_io;
+ phy3_ou : OUT t_tech_ddr3_phy_ou;
+
+ -- DDR4 PHY external interface
+ phy4_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
+ phy4_io : INOUT t_tech_ddr4_phy_io;
+ phy4_ou : OUT t_tech_ddr4_phy_ou
);
END ddrctrl;
@@ -62,58 +82,133 @@ END ddrctrl;
ARCHITECTURE str OF ddrctrl IS
-- constant for readability
- CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data with for ddrctrl_repack
-
+ CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr );
+ CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+ CONSTANT c_burstsize : NATURAL := 64; -- max burstsize for max troughput
+ CONSTANT c_bitshift_adr : NATURAL := ceil_log2(c_burstsize);
+ CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
+ CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_adr-1 DOWNTO 0) := (OTHERS => '0');
-- signals for connecting the components
- SIGNAL data : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
- SIGNAL sosi : t_dp_sosi := c_dp_sosi_init;
- SIGNAL a_of : NATURAL := 0;
-
-BEGIN
-
- -- makes one data vector out of all the data from the t_dp_sosi_arr
- u_pack : ENTITY work.ddrctrl_pack
- GENERIC MAP(
-
- g_nof_streams => g_nof_streams, -- number of input streams
- g_data_w => g_data_w -- data with of input data vectors
+ SIGNAL adr : NATURAL := 0;
+ SIGNAL ctrl_clk : STD_LOGIC;
+ SIGNAL ctrl_rst : STD_LOGIC;
+ SIGNAL wr_sosi : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
+ SIGNAL dvr_mosi : t_mem_ctlr_mosi;
- )
- PORT MAP(
- in_sosi_arr => in_sosi_arr, -- input data
- out_data => data -- output data
-
- );
+BEGIN
- -- resizes the input data vector so that the output data vector can be stored into the ddr memory
- u_repack : ENTITY work.ddrctrl_repack
+ p_burst : PROCESS(adr)
+ BEGIN
+ IF TO_UVEC(adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN
+ dvr_mosi.burstbegin <= '1';
+ IF adr = 0 THEN
+ dvr_mosi.address <= TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
+ ELSE
+ dvr_mosi.address <= TO_UVEC(adr-c_burstsize, dvr_mosi.address'length);
+ END IF;
+ ELSE
+ dvr_mosi.burstbegin <= '0';
+ END IF;
+ END PROCESS;
+
+ dvr_mosi.burstsize <= TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
+ dvr_mosi.wr <= wr_not_rd;
+ dvr_mosi.rd <= NOT wr_not_rd;
+
+ -- input to io_ddr
+ u_ddrctrl_input : ENTITY work.ddrctrl_input
GENERIC MAP(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_in_data_w => c_out_data_w -- the input data with
+ g_tech_ddr => g_tech_ddr,
+ g_sim_model => g_sim_model,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
)
PORT MAP(
- clk => clk,
- rst => rst,
- in_data => data, -- input data
- out_of => a_of, -- amount of internal overflow
- out_sosi => sosi -- output data
+ clk => clk,
+ rst => rst,
+ in_sosi_arr => in_sosi_arr,
+ out_of => out_of,
+ out_sosi => wr_sosi,
+ out_adr => adr
);
- -- creates address by counting input valids
- u_address_counter : ENTITY work.ddrctrl_address_counter
+ -- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
+ u_io_ddr : ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_sim_model => g_sim_model -- determens if this is a simulation
- )
- PORT MAP(
- clk => clk,
- rst => rst,
- in_sosi => sosi, -- input data
- in_of => a_of,
- out_mosi => out_mosi, -- output data
- out_of => out_of
+ g_sim_model => g_sim_model,
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => FALSE,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_wr_flush_mode => "VAL",
+ g_wr_flush_use_channel => FALSE,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
+ )
+ PORT MAP(
+
+ -- DDR reference clock
+ ctlr_ref_clk => clk,
+ ctlr_ref_rst => rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ctrl_clk,
+ ctlr_rst_out => ctrl_rst,
+
+ ctlr_clk_in => ctrl_clk,
+ ctlr_rst_in => ctrl_rst,
+
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM interface
+ reg_io_ddr_mosi => open,
+ reg_io_ddr_miso => open,
+
+ -- Driver clock domain
+ dvr_clk => clk,
+ dvr_rst => rst,
+
+ dvr_miso => open,
+ dvr_mosi => dvr_mosi,
+
+ -- Write FIFO clock domain
+ wr_clk => clk,
+ wr_rst => rst,
+
+ wr_fifo_usedw => open,
+ wr_sosi => wr_sosi,
+ wr_siso => open,
+
+ -- Read FIFO clock domain
+ rd_clk => clk,
+ rd_rst => rst,
+
+ rd_fifo_usedw => open,
+ rd_sosi => open,
+ rd_siso => rd_siso,
+
+ term_ctrl_out => term_ctrl_out,
+ term_ctrl_in => term_ctrl_in,
+
+ -- DDR3 PHY external interface
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+
+ -- DDR4 PHY external interface
+ phy4_in => phy4_in,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
);
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0125aa60e02ab526c1befe95d110db62f2e224da
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -0,0 +1,121 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Folding a stream of data into a mm data configuration so it can be
+-- stored in a DDR RAM-stick.
+--
+-- Description:
+-- First the data from the sosi array gets collected into one data vector.
+-- After that this data vector gets resized to the right size data vector in
+-- order to make it storable in a DDR RAM-stick.
+-- After that a address gets assigned to the data so the data can be found back.
+--
+-- Remark:
+-- Use VHDL coding template from:
+-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+-- The maximum value of the address is determend by g_tech_ddr.
+
+LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+
+ENTITY ddrctrl_input IS
+ GENERIC (
+ g_tech_ddr : t_c_tech_ddr; -- type of memory
+ g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
+ g_nof_streams : NATURAL := 12; -- number of input streams
+ g_data_w : NATURAL := 14 -- data with of input data vectors
+ );
+ PORT (
+ clk : IN STD_LOGIC := '0';
+ rst : IN STD_LOGIC;
+ in_sosi_arr : IN t_dp_sosi_arr; -- input data
+ out_of : OUT NATURAL; -- amount of internal overflow this output
+ out_sosi : OUT t_dp_sosi; -- output data
+ out_adr : OUT NATURAL
+ );
+END ddrctrl_input;
+
+
+ARCHITECTURE str OF ddrctrl_input IS
+
+ -- constant for readability
+ CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data with for ddrctrl_repack
+
+
+ -- signals for connecting the components
+ SIGNAL data : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
+ SIGNAL sosi : t_dp_sosi := c_dp_sosi_init;
+ SIGNAL a_of : NATURAL := 0;
+
+BEGIN
+
+ -- makes one data vector out of all the data from the t_dp_sosi_arr
+ u_pack : ENTITY work.ddrctrl_input_pack
+ GENERIC MAP(
+
+ g_nof_streams => g_nof_streams, -- number of input streams
+ g_data_w => g_data_w -- data with of input data vectors
+
+ )
+ PORT MAP(
+
+ in_sosi_arr => in_sosi_arr, -- input data
+ out_data => data -- output data
+
+ );
+
+ -- resizes the input data vector so that the output data vector can be stored into the ddr memory
+ u_repack : ENTITY work.ddrctrl_input_repack
+ GENERIC MAP(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_in_data_w => c_out_data_w -- the input data with
+ )
+ PORT MAP(
+ clk => clk,
+ rst => rst,
+ in_data => data, -- input data
+ out_of => a_of, -- amount of internal overflow
+ out_sosi => sosi -- output data
+ );
+
+ -- creates address by counting input valids
+ u_address_counter : ENTITY work.ddrctrl_input_address_counter
+ GENERIC MAP(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_sim_model => g_sim_model -- determens if this is a simulation
+ )
+ PORT MAP(
+ clk => clk,
+ rst => rst,
+ in_sosi => sosi, -- input data
+ in_of => a_of,
+ out_sosi => out_sosi, -- output data
+ out_of => out_of,
+ out_adr => out_adr
+ );
+
+END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
similarity index 73%
rename from applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
rename to applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index 25d43e825ad5bd8bd5babdb72071004b391f9945..1d95748b0f99bcaf94ff7d14b022724efca7e494 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -39,7 +39,7 @@ USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-ENTITY ddrctrl_address_counter IS
+ENTITY ddrctrl_input_address_counter IS
GENERIC (
g_tech_ddr : t_c_tech_ddr; -- type of memory
g_sim_model : BOOLEAN := TRUE -- determens if this is a simulation
@@ -49,18 +49,19 @@ ENTITY ddrctrl_address_counter IS
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi; -- input data
in_of : IN NATURAL;
- out_mosi : OUT t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst; -- output data
- out_of : OUT NATURAL
+ out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
+ out_of : OUT NATURAL;
+ out_adr : OUT NATURAL
);
-END ddrctrl_address_counter;
+END ddrctrl_input_address_counter;
-ARCHITECTURE rtl OF ddrctrl_address_counter IS
+ARCHITECTURE rtl OF ddrctrl_input_address_counter IS
-- constants for readability
CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576
- CONSTANT c_adr_w : NATURAL := sel_a_b(g_sim_model, 4, func_tech_ddr_ctlr_address_w( g_tech_ddr )); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- CONSTANT c_max_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UVEC(2**(c_adr_w)-1, c_adr_w)); -- the maximal address that is possible within the vector length of the address
+ CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
+ CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
-- type for statemachine
TYPE t_state IS (RESET, COUNTING, MAX, IDLE);
@@ -68,13 +69,14 @@ ARCHITECTURE rtl OF ddrctrl_address_counter IS
-- record for readability
TYPE t_reg IS RECORD
state : t_state;
- out_mosi : t_mem_ctlr_mosi;
+ out_sosi : t_dp_sosi;
out_of : NATURAL;
s_in_sosi : t_dp_sosi;
s_in_of : NATURAL;
+ s_adr : NATURAL;
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, c_mem_ctlr_mosi_rst, 0, c_dp_sosi_init, 0);
+ CONSTANT c_t_reg_init : t_reg := (RESET, c_dp_sosi_init, 0, c_dp_sosi_init, 0, 0);
-- signals for readability
@@ -92,8 +94,8 @@ BEGIN
BEGIN
v := q_reg;
- v.out_mosi.wrdata(c_data_w-1 DOWNTO 0) := q_reg.s_in_sosi.data(c_data_w - 1 DOWNTO 0);
- v.out_mosi.wr := q_reg.s_in_sosi.valid;
+ v.out_sosi.data(c_data_w-1 DOWNTO 0) := q_reg.s_in_sosi.data(c_data_w - 1 DOWNTO 0);
+ v.out_sosi.valid := q_reg.s_in_sosi.valid;
v.out_of := q_reg.s_in_of;
v.s_in_sosi := in_sosi;
v.s_in_of := in_of;
@@ -101,13 +103,13 @@ BEGIN
CASE q_reg.state IS
WHEN RESET =>
- v.out_mosi.address(c_adr_w-1 DOWNTO 0) := (OTHERS => '0');
+ v.s_adr := c_max_adr-1; -- when there is a reset the fifo in io_ddr always needs the first out_sosi.valid to stop flushing the data so the first data word always gets lost. if s_adr is set to 0 after a restart the word from s_adr 1 will be put at address 0 in memory.
WHEN COUNTING =>
- v.out_mosi.address(c_adr_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UVEC(TO_UINT(q_reg.out_mosi.address)+1, c_adr_w));
+ v.s_adr := q_reg.s_adr+1;
WHEN MAX =>
- v.out_mosi.address(c_adr_w-1 DOWNTO 0) := (OTHERS => '0');
+ v.s_adr := 0;
WHEN IDLE =>
@@ -115,7 +117,7 @@ BEGIN
IF rst = '1' THEN
v.state := RESET;
- ELSIF q_reg.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN
+ ELSIF q_reg.s_adr = c_max_adr AND in_sosi.valid = '1' THEN
v.state := MAX;
ELSIF in_sosi.valid = '1' THEN
v.state := COUNTING;
@@ -127,7 +129,8 @@ BEGIN
END PROCESS;
-- fill outputs
- out_mosi <= q_reg.out_mosi;
+ out_sosi <= q_reg.out_sosi;
out_of <= q_reg.out_of;
+ out_adr <= q_reg.s_adr;
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
similarity index 92%
rename from applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
rename to applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
index 5d7630a29b8c8e4b870f74ca713a0ad3622cd1a1..a7f32826e5a101ad17282b27b292e6c15e2b98c3 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
@@ -31,7 +31,7 @@ LIBRARY IEEE, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-ENTITY ddrctrl_pack IS
+ENTITY ddrctrl_input_pack IS
GENERIC (
g_nof_streams : POSITIVE := 12; -- number of input streams
@@ -44,9 +44,9 @@ ENTITY ddrctrl_pack IS
out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data
);
-END ddrctrl_pack;
+END ddrctrl_input_pack;
-ARCHITECTURE rtl OF ddrctrl_pack IS
+ARCHITECTURE rtl OF ddrctrl_input_pack IS
BEGIN
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
similarity index 97%
rename from applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
rename to applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index e650494588ca35744b3d979d72ea214368350fe3..9416182dd0d6309b135c9ac1e7dcf06e1e5402dc 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -34,7 +34,7 @@ USE IEEE.std_logic_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
-ENTITY ddrctrl_repack IS
+ENTITY ddrctrl_input_repack IS
GENERIC (
g_tech_ddr : t_c_tech_ddr; -- type of memory
g_in_data_w : NATURAL := 168 -- the input data with
@@ -46,10 +46,10 @@ ENTITY ddrctrl_repack IS
out_of : OUT NATURAL := 0; -- amount of internal overflow this output
out_sosi : OUT t_dp_sosi := c_dp_sosi_init -- output data
);
-END ddrctrl_repack;
+END ddrctrl_input_repack;
-ARCHITECTURE rtl OF ddrctrl_repack IS
+ARCHITECTURE rtl OF ddrctrl_input_repack IS
-- constant for readability
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 8b56c9ddcf22d7455e0099fbc19f4179ba6e526c..ebbc092b4dccc17c8ced070d319115f8adc73ad8 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -31,73 +31,83 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY tb_ddrctrl IS
GENERIC (
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
- g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
g_nof_streams : POSITIVE := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
- g_sim_length : NATURAL := 52
-
+ g_sim_length : NATURAL := 16500; -- close to the amount of word that gets put into the memory
+ g_technology : NATURAL := c_tech_select_default;
+ g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+ g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m
);
END tb_ddrctrl;
ARCHITECTURE tb OF tb_ddrctrl IS
-- constants for testbench
+ CONSTANT c_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
+ CONSTANT c_mm_clk_freq : NATURAL := 100; -- mm clock frequency in MHz
+ CONSTANT c_mm_clk_period : TIME := (10**6 / c_mm_clk_freq) * 1 ps; -- mm clock period, 10 ns
+ CONSTANT c_sim_length : NATURAL := (g_sim_length*576)/168; -- amount of input words that get put into the DUT
+
+ -- Select DDR3 or DDR4 dependent on the technology and sim model
+ CONSTANT c_mem_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);
+ CONSTANT c_sim_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, c_tech_ddr3_sim_16k, c_tech_ddr4_sim_16k);
+ CONSTANT c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(c_sim_model, c_sim_ddr, c_mem_ddr);
+
-- constants for readability
CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
- CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
- CONSTANT c_adr_w : NATURAL := 4; -- address with in simulation
- CONSTANT c_adr_size : NATURAL := 2**c_adr_w; -- address size in simulation
-- function for making total data vector
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
- VARIABLE temp : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0);
+ VARIABLE temp : STD_LOGIC_VECTOR(c_in_data_w*c_sim_length-1 DOWNTO 0);
+ VARIABLE conv : STD_LOGIC_VECTOR(32-1 DOWNTO 0); -- removes a warning
BEGIN
- FOR I IN 0 TO g_sim_length*g_nof_streams-1 LOOP
- temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
+ FOR I IN 0 TO c_sim_length*g_nof_streams-1 LOOP
+ conv := TO_UVEC(I, 32);
+ temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := conv(g_data_w-1 DOWNTO 0);
END LOOP;
RETURN temp;
END FUNCTION c_total_vector_init;
-- constant for running the test
- CONSTANT c_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
+ CONSTANT c_total_vector : STD_LOGIC_VECTOR(c_in_data_w*c_sim_length-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
-- input signals for ddrctrl.vhd
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '0';
- SIGNAL q_rst : STD_LOGIC := '0';
- SIGNAL q_q_rst : STD_LOGIC := '0';
+ SIGNAL mm_clk : STD_LOGIC := '0';
+ SIGNAL mm_rst : STD_LOGIC := '0';
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
+ SIGNAL wr_not_rd : STD_LOGIC;
- -- output singals from ddrctrl.vhd
- SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is
- SIGNAL out_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst; -- output signal from ddrctrl_pack.vhd
-- testbench signal
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
-- signals for running test
SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
- SIGNAL q_in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd with a delay of 1 clockcycle
- SIGNAL q_q_in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd with a delay of 2 clockcycles
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
- SIGNAL q_test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started with a delay of 1 clockcycle
- SIGNAL q_q_test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started with a delay of 2 clockcycles
- SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest
- SIGNAL q_lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest with a delay of 1 clockcycle
+
+ -- PHY
+ SIGNAL phy3_io : t_tech_ddr3_phy_io;
+ SIGNAL phy3_ou : t_tech_ddr3_phy_ou;
+ SIGNAL phy4_io : t_tech_ddr4_phy_io;
+ SIGNAL phy4_ou : t_tech_ddr4_phy_ou;
BEGIN
-- generating clock
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+ mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
-- excecuting test
p_test : PROCESS
@@ -108,12 +118,17 @@ BEGIN
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*4;
rst <= '1';
+ mm_rst <= '1';
WAIT FOR c_clk_period*1;
rst <= '0';
+ mm_rst <= '0';
test_running <= '1';
+ wr_not_rd <= '1';
+ WAIT FOR c_clk_period*1;
+
-- filling the input data vectors with the corresponding numbers
- make_data : FOR J IN 0 TO g_sim_length-1 LOOP
+ make_data : FOR J IN 0 TO c_sim_length-1 LOOP
in_data_cnt <= in_data_cnt+1;
fill_in_sosi_arr_rest : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
@@ -121,15 +136,7 @@ BEGIN
WAIT FOR c_clk_period*1;
END LOOP;
test_running <= '0';
-
- -- testing reset
- FOR I IN 0 TO g_sim_length-1 LOOP
- rst <= '1';
- WAIT FOR c_clk_period*1;
- rst <= '0';
- WAIT FOR c_clk_period*((((c_out_data_w/c_in_data_w)+1)*c_adr_size)+4);
- END LOOP;
-
+ wr_not_rd <= '0';
-- stopping the testbench
WAIT FOR c_clk_period*4;
@@ -137,73 +144,33 @@ BEGIN
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
- -- generating compare data for out_mosi
- p_out_mosi : PROCESS
- BEGIN
- WAIT UNTIL rising_edge(clk);
- if rising_edge(clk) THEN
- q_q_rst <= q_rst;
- q_lag_due_reset <= lag_due_reset;
- q_rst <= rst;
- END IF;
- IF q_rst = '1' THEN
- IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
- lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
- ELSE
- lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
- END IF;
- END IF;
- END PROCESS;
-
- -- verifying if the address is correct by keeping track of the address
- p_verify_address : PROCESS
- BEGIN
- FOR I IN 0 TO c_adr_size-1 LOOP
- IF I >= q_lag_due_reset THEN
- ASSERT I-q_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
- ELSE
- ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
- END IF;
- WAIT UNTIL out_mosi.wr = '1';
- IF q_q_rst = '1' THEN
- WAIT UNTIL out_mosi.wr = '1';
- END IF;
- END LOOP;
- END PROCESS;
- -- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
- p_verify : PROCESS
-
- VARIABLE ctr_of : NATURAL := 0;
- VARIABLE out_data_cnt : NATURAL := 0;
-
- BEGIN
- WAIT UNTIL rising_edge(clk);
- IF q_q_test_running = '1' AND out_mosi.wr = '1' THEN
- out_data_cnt := out_data_cnt+1;
- IF out_data_cnt mod 2 = 0 THEN
- ctr_of := c_in_data_w*(q_q_in_data_cnt)-c_out_data_w*out_data_cnt;
- ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
- END IF;
- ASSERT out_mosi.wrdata(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
- END IF;
- END PROCESS;
-- DUT
u_ddrctrl : ENTITY work.ddrctrl
GENERIC MAP (
- g_tech_ddr => g_tech_ddr,
- g_sim_model => g_sim_model,
+ g_tech_ddr => c_tech_ddr,
+ g_sim_model => c_sim_model,
+ g_technology => g_technology,
g_nof_streams => g_nof_streams,
g_data_w => g_data_w
)
PORT MAP (
clk => clk,
rst => rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
in_sosi_arr => in_sosi_arr,
- out_of => out_of,
- out_mosi => out_mosi
+ wr_not_rd => wr_not_rd,
+ out_of => open,
+ out_adr => open,
+
+ --PHY
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
);
END tb;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1df9277d93977ed10fdb5f7170add3169a8a3e43
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd
@@ -0,0 +1,222 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Job van Wee
+-- Purpose: Self checking and self-stopping tb for ddrctrl_input.vhd
+-- Usage:
+-- > run -a
+
+LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY tb_ddrctrl_input IS
+ GENERIC (
+
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
+ g_nof_streams : POSITIVE := 12; -- number of input streams
+ g_data_w : NATURAL := 14; -- data with of input data vectors
+ g_sim_length : NATURAL := 52
+
+ );
+END tb_ddrctrl_input;
+
+ARCHITECTURE tb OF tb_ddrctrl_input IS
+
+ -- constants for testbench
+ CONSTANT c_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
+ CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
+ CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
+
+ -- constants for readability
+ CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
+ CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
+ CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ) ; -- address with in simulation
+ CONSTANT c_adr_size : NATURAL := 2**c_adr_w; -- address size in simulation
+
+ -- function for making total data vector
+ FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
+ VARIABLE v_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0);
+ BEGIN
+ FOR I IN 0 TO g_sim_length*g_nof_streams-1 LOOP
+ v_total_vector(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
+ END LOOP;
+ RETURN v_total_vector;
+ END FUNCTION c_total_vector_init;
+
+ -- constant for running the test
+ CONSTANT c_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
+
+
+ -- input signals for ddrctrl_input.vhd
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC := '0';
+ SIGNAL q_rst : STD_LOGIC := '0';
+ SIGNAL q_q_rst : STD_LOGIC := '0';
+ SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
+
+ -- output singals from ddrctrl_input.vhd
+ SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is
+ SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init; -- output signal from ddrctrl_pack.vhd
+ SIGNAL out_adr : NATURAL := 0;
+
+ -- testbench signal
+ SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
+
+ -- signals for running test
+ SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
+ SIGNAL q_in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd with a delay of 1 clockcycle
+ SIGNAL q_q_in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd with a delay of 2 clockcycles
+ SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
+ SIGNAL q_test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started with a delay of 1 clockcycle
+ SIGNAL q_q_test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started with a delay of 2 clockcycles
+ SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest
+ SIGNAL q_lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest with a delay of 1 clockcycle
+
+BEGIN
+
+ -- generating clock
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+
+ -- excecuting test
+ p_test : PROCESS
+ BEGIN
+
+ -- start the test
+ tb_end <= '0';
+ WAIT UNTIL rising_edge(clk); -- align to rising edge
+ WAIT FOR c_clk_period*4;
+ rst <= '1';
+ WAIT FOR c_clk_period*1;
+ rst <= '0';
+ test_running <= '1';
+
+ -- filling the input data vectors with the corresponding numbers
+ make_data : FOR J IN 0 TO g_sim_length-1 LOOP
+ in_data_cnt <= in_data_cnt+1;
+ fill_in_sosi_arr_rest : FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
+ END LOOP;
+ WAIT FOR c_clk_period*1;
+ END LOOP;
+ test_running <= '0';
+
+ -- testing reset
+ --FOR I IN 0 TO g_sim_length-1 LOOP
+ --rst <= '1';
+ --WAIT FOR c_clk_period*1;
+ --rst <= '0';
+ --WAIT FOR c_clk_period*((((c_out_data_w/c_in_data_w)+1)*c_adr_size)+4);
+ --END LOOP;
+
+
+ -- stopping the testbench
+ WAIT FOR c_clk_period*4;
+ tb_end <= '1';
+ ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
+ END PROCESS;
+
+ -- generating compare data for out_sosi
+ p_out_sosi : PROCESS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ if rising_edge(clk) THEN
+ q_q_rst <= q_rst;
+ q_lag_due_reset <= lag_due_reset;
+ q_rst <= rst;
+ END IF;
+ IF q_rst = '1' THEN
+ IF lag_due_reset+out_adr+2 >= c_adr_size THEN
+ lag_due_reset <= lag_due_reset+out_adr+2-c_adr_size;
+ ELSE
+ lag_due_reset <= lag_due_reset+out_adr+2;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- verifying if the address is correct by keeping track of the address
+ p_verify_address : PROCESS
+
+ VARIABLE v_adr : NATURAL range 0 to c_adr_size-1 := c_adr_size-2;
+
+ BEGIN
+ WAIT UNTIL rst = '1';
+ WAIT UNTIL rst = '0';
+ FOR I IN 0 TO g_sim_length-1 LOOP
+ IF v_adr >= q_lag_due_reset THEN
+ ASSERT v_adr-q_lag_due_reset = out_adr REPORT "Wrong address, 1, v_adr = " & NATURAL'image(v_adr-q_lag_due_reset) & ", address = " & NATURAL'image(out_adr) SEVERITY ERROR;
+ ELSE
+ ASSERT (v_adr-q_lag_due_reset)+c_adr_size = out_adr REPORT "Wrong address, 2, v_adr = " & NATURAL'image((v_adr-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(out_adr) SEVERITY ERROR;
+ END IF;
+ WAIT UNTIL out_sosi.valid = '1';
+ IF q_q_rst = '1' THEN
+ WAIT UNTIL out_sosi.valid = '1';
+ END IF;
+ IF v_adr = c_adr_size-1 THEN
+ v_adr := 0;
+ ELSE
+ v_adr := v_adr+1;
+ END IF;
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+ -- verification by checking if the input vectors are correctly put into the output vector and the amount of overflow is as expected
+ p_verify : PROCESS
+
+ VARIABLE ctr_of : NATURAL := 0;
+ VARIABLE out_data_cnt : NATURAL := 0;
+
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ IF q_q_test_running = '1' AND out_sosi.valid = '1' THEN
+ out_data_cnt := out_data_cnt+1;
+ IF out_data_cnt mod 2 = 0 THEN
+ ctr_of := c_in_data_w*(q_q_in_data_cnt)-c_out_data_w*out_data_cnt;
+ ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
+ END IF;
+ ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
+ END IF;
+ END PROCESS;
+
+
+ -- DUT
+ u_ddrctrl_input : ENTITY work.ddrctrl_input
+ GENERIC MAP (
+ g_tech_ddr => g_tech_ddr,
+ g_sim_model => c_sim_model,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
+ )
+ PORT MAP (
+ clk => clk,
+ rst => rst,
+ in_sosi_arr => in_sosi_arr,
+ out_of => out_of,
+ out_sosi => out_sosi,
+ out_adr => out_adr
+ );
+
+END tb;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd
similarity index 76%
rename from applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
rename to applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd
index a17f098b594c673887acdc59f982a8dd87d515f2..843e6b0e8e0061eb6b84efa52efca0bd7ec37068 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for ddrctrl_address_counter.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl_input_address_counter.vhd
-- Usage:
-- > run -a
@@ -30,7 +30,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_ddrctrl_address_counter IS
+ENTITY tb_ddrctrl_input_address_counter IS
GENERIC (
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
@@ -38,9 +38,9 @@ ENTITY tb_ddrctrl_address_counter IS
g_sim_length : NATURAL := 52 -- determens the length of the duration of the test
);
-END tb_ddrctrl_address_counter;
+END tb_ddrctrl_input_address_counter;
-ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
+ARCHITECTURE tb OF tb_ddrctrl_input_address_counter IS
-- constants for running the testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
@@ -48,10 +48,9 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
-- constants for running the test
CONSTANT c_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- in and output data vector with, 576
- CONSTANT c_adr_w : NATURAL := 4; -- address with in simulation
+ CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- address with in simulation
CONSTANT c_adr_size : NATURAL := 2**c_adr_w; -- address size in simulation
-
-- input signals for ddrctrl_address_counter.vhd
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '0';
@@ -61,7 +60,8 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
SIGNAL in_of : NATURAL := 0; -- signal which contains the amount of overflow
-- output signal from ddrctrl_address_counter.vhd
- SIGNAL out_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst; -- signal which is the output from ddrctrl_address_counter.vhd
+ SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init; -- signal which is the output from ddrctrl_address_counter.vhd
+ SIGNAL out_adr : NATURAL := 0;
SIGNAL out_of : NATURAL := 0; -- signal which is the output from ddrctrl_address_counter.vhd
-- testbench signals
@@ -95,6 +95,10 @@ BEGIN
in_data <= (OTHERS => '0');
in_data_enable <= '0';
WAIT UNTIL rising_edge(clk);
+ WAIT FOR c_clk_period*4;
+ rst <= '1';
+ WAIT FOR c_clk_period*1;
+ rst <= '0';
-- changing inputs to start the address counting
FOR I IN 0 TO g_sim_length-1 LOOP
@@ -112,8 +116,8 @@ BEGIN
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
- -- generating compare data for out_mosi
- p_out_mosi : PROCESS
+ -- generating compare data for out_sosi
+ p_out_sosi : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
if rising_edge(clk) THEN
@@ -128,10 +132,10 @@ BEGIN
q_rst <= rst;
END IF;
IF q_rst = '1' THEN
- IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
- lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
+ IF lag_due_reset + out_adr >= c_adr_size THEN
+ lag_due_reset <= lag_due_reset+out_adr-c_adr_size;
ELSE
- lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
+ lag_due_reset <= lag_due_reset+out_adr;
END IF;
END IF;
END PROCESS;
@@ -142,8 +146,8 @@ BEGIN
BEGIN
WAIT UNTIL rising_edge(clk);
IF rising_edge(clk) THEN
- ASSERT q_q_in_data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR;
- ASSERT q_q_in_data_enable = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
+ ASSERT q_q_in_data(c_data_w-1 DOWNTO 0) = out_sosi.data(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_sosi.data" SEVERITY ERROR;
+ ASSERT q_q_in_data_enable = out_sosi.valid REPORT "in_sosi.valid does not match out_sosi.valid" SEVERITY ERROR;
ASSERT q_q_in_of = out_of REPORT "in_of does not match out_of" SEVERITY ERROR;
END IF;
END PROCESS;
@@ -159,23 +163,33 @@ BEGIN
-- verifying if the address is correct by keeping track of the address
p_verify_address : PROCESS
+
+ VARIABLE v_adr : NATURAL range 0 to c_adr_size-1 := c_adr_size-1;
+
BEGIN
- FOR I IN 0 TO c_adr_size-1 LOOP
- IF I >= q_lag_due_reset THEN
- ASSERT I-q_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
+ WAIT UNTIL rst = '1';
+ WAIT UNTIL rst = '0';
+ FOR I IN 0 TO g_sim_length-1 LOOP
+ IF v_adr >= q_lag_due_reset THEN
+ ASSERT v_adr-q_lag_due_reset = out_adr REPORT "Wrong address, 1, v_adr = " & NATURAL'image(v_adr-q_lag_due_reset) & ", address = " & NATURAL'image(out_adr) SEVERITY ERROR;
ELSE
- ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
+ ASSERT (v_adr-q_lag_due_reset)+c_adr_size = out_adr REPORT "Wrong address, 2, v_adr = " & NATURAL'image((v_adr-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(out_adr) SEVERITY ERROR;
END IF;
- WAIT UNTIL out_mosi.wr = '1';
+ WAIT UNTIL out_sosi.valid = '1';
IF q_q_rst = '1' THEN
- WAIT UNTIL out_mosi.wr = '1';
+ WAIT UNTIL out_sosi.valid = '1';
+ END IF;
+ IF v_adr = c_adr_size-1 THEN
+ v_adr := 0;
+ ELSE
+ v_adr := v_adr+1;
END IF;
END LOOP;
END PROCESS;
-- DUT
- u_ddrctrl_address_counter : ENTITY work.ddrctrl_address_counter
+ u_ddrctrl_input_address_counter : ENTITY work.ddrctrl_input_address_counter
GENERIC MAP (
g_tech_ddr => g_tech_ddr,
g_sim_model => g_sim_model
@@ -186,8 +200,9 @@ BEGIN
in_sosi => in_sosi,
in_of => in_of,
- out_mosi => out_mosi,
- out_of => out_of
+ out_sosi => out_sosi,
+ out_of => out_of,
+ out_adr => out_adr
);
END tb;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_pack.vhd
similarity index 95%
rename from applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
rename to applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_pack.vhd
index 6f81b6cb22c88159a2153680f467c39799fa06fe..7570ed4ee919b73037a8f163ad8a447a39c6a052 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_pack.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for ddrctrl_pack.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl_input_pack.vhd
-- Usage:
-- > run -a
@@ -32,7 +32,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_ddrctrl_pack IS
+ENTITY tb_ddrctrl_input_pack IS
GENERIC (
g_nof_streams : POSITIVE := 12; -- number of input streams
@@ -40,9 +40,9 @@ ENTITY tb_ddrctrl_pack IS
g_sim_length : NATURAL := 52 -- determens the lengt of the duration of the test
);
-END tb_ddrctrl_pack;
+END tb_ddrctrl_input_pack;
-ARCHITECTURE tb OF tb_ddrctrl_pack IS
+ARCHITECTURE tb OF tb_ddrctrl_input_pack IS
-- constants for running the testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
@@ -123,7 +123,7 @@ BEGIN
END PROCESS;
-- DUT
- u_ddrctrl_pack : ENTITY work.ddrctrl_pack
+ u_ddrctrl_input_pack : ENTITY work.ddrctrl_input_pack
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_data_w => g_data_w
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_repack.vhd
similarity index 96%
rename from applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
rename to applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_repack.vhd
index 395cb8896128ab33aa01da54733982f8a855e143..2458c6bcf29245d074a584ae6ad5da8e9fe49731 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_repack.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
--- Purpose: Self checking and self-stopping tb for ddrctrl_repack.vhd
+-- Purpose: Self checking and self-stopping tb for ddrctrl_input_repack.vhd
-- Usage:
-- > run -a
@@ -32,7 +32,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_ddrctrl_repack IS
+ENTITY tb_ddrctrl_input_repack IS
GENERIC (
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
@@ -40,9 +40,9 @@ ENTITY tb_ddrctrl_repack IS
g_sim_lengt : NATURAL := 52 -- amount of times there wil be input data for ddrctrl_repack in this testbench
);
-END tb_ddrctrl_repack;
+END tb_ddrctrl_input_repack;
-ARCHITECTURE tb OF tb_ddrctrl_repack IS
+ARCHITECTURE tb OF tb_ddrctrl_input_repack IS
-- constants for running testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock freqency in MHz
@@ -134,7 +134,7 @@ BEGIN
-- DUT
- u_ddrctrl_repack : ENTITY work.ddrctrl_repack
+ u_ddrctrl_input_repack : ENTITY work.ddrctrl_input_repack
GENERIC MAP (
g_tech_ddr => g_tech_ddr,
g_in_data_w => g_in_data_w