diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index 997d282cf2143bd8fd6854e590abf5f2431cc194..957b4d685492e88068d03b202a7de53c0b3cf143 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -1,4 +1,4 @@
-Quick steps to compile and use design [unb2_minimal] in RadionHDL
+Quick steps to compile and use design [unb2_test] in RadionHDL
 -----------------------------------------------------------------
 
 
@@ -8,7 +8,7 @@ Start with the Oneclick Commands:
     python $RADIOHDL/tools/oneclick/base/quartus_config.py -t ip_arria10
 
 Generate MMM for QSYS:
-    run_qsys unb2 unb2_minimal
+    run_qsys unb2 unb2_test
 
 -> From here either continue to Modelsim (simulation) or Quartus (synthesis)
 
@@ -20,15 +20,15 @@ Modelsim instructions:
     run_modelsim unb2
 
     # in Modelsim do:
-    lp unb2_minimal
+    lp unb2_test
     mk all
     # now double click on testbench file
     as 10
     run 500us
 
     # while the simulation runs... in another bash session do:
-    cd unb2_minimal/tb/python
-    python tc_unb2_minimal.py --sim --unb 0 --bn 3 --seq INFO,PPSH,SENSORS 
+    cd unb2_test/tb/python
+    python tc_unb2_test.py --sim --unb 0 --bn 3 --seq INFO,PPSH,SENSORS 
 
     # (sensor results only show up after 1000us of simulation runtime)
 
@@ -39,26 +39,25 @@ Modelsim instructions:
 Synthesis
 ---------
 Quartus instructions (for QSYS):
-    run_app unb2 unb2_minimal use=gen2
-    run_qcomp unb2 unb2_minimal
+    run_app unb2 unb2_test use=gen2
+    run_qcomp unb2 unb2_test
 
-In case of needing the Quartus GUI:
+In case of needing the Quartus GUI for inspection:
     run_quartus unb2
 
 
 Convert .sof to .rbf:
     # assuming in /tmp/temp_options_file: Bitstream_compression=on
-    run_rbf unb2 unb2_minimal  # QSYS
+    run_rbf unb2 unb2_test
 
 
 Send to LCU capture5:
-    scp $RADIOHDL/build/quartus/unb2_minimal/unb2_minimal.rbf capture5:~/rbf/  # QSYS
+    scp $RADIOHDL/build/quartus/unb2_test/unb2_test.rbf capture5:~/rbf/
 
     # Now login on capture5 and use pythonscript to program flash:
-    cd unb2_minimal/tb/python
+    cd unb2_test/tb/python
 
     # for example use frontnode 0 on uniboard 0:
-    python tc_unb2_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb2_minimal.rbf   # QSYS
-
-    python tc_unb2_minimal.py --gn 0 --seq REMU,REGMAP,INFO,PPSH,SENSORS  # start design, read info-ppsh-sensors
+    python tc_unb2_test.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb2_test.rbf
+    python tc_unb2_test.py --gn 0 --seq REMU,REGMAP,INFO,PPSH,SENSORS  # start design, read info-ppsh-sensors
 
diff --git a/boards/uniboard2/designs/unb2_test/hdllib.cfg b/boards/uniboard2/designs/unb2_test/hdllib.cfg
index 8e7cf84190602df567423e0fa6cd94e50027a9fe..6344711e592e77184d4aab9ba56863eda47c2800 100644
--- a/boards/uniboard2/designs/unb2_test/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = unb2_minimal
-hdl_library_clause_name = unb2_minimal_lib
+hdl_lib_name = unb2_test
+hdl_library_clause_name = unb2_test_lib
 hdl_lib_uses = common mm unb2_board 
 hdl_lib_technology = ip_arria10
 
@@ -7,28 +7,28 @@ build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
-    src/vhdl/qsys_unb2_minimal_pkg.vhd
-    src/vhdl/mmm_unb2_minimal.vhd
-    src/vhdl/unb2_minimal.vhd
+    src/vhdl/qsys_unb2_test_pkg.vhd
+    src/vhdl/mmm_unb2_test.vhd
+    src/vhdl/unb2_test.vhd
     
 test_bench_files = 
-    tb/vhdl/tb_unb2_minimal.vhd
+    tb/vhdl/tb_unb2_test.vhd
 
 synth_top_level_entity =
 
 quartus_copy_files =
-    quartus/qsys_unb2_minimal.qsys .
+    quartus/qsys_unb2_test.qsys .
 
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
 
 quartus_tcl_files =
-    quartus/unb2_minimal_pins.tcl
+    quartus/unb2_test_pins.tcl
 
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+    $HDL_BUILD_DIR/quartus/unb2_test/qsys_unb2_test/synthesis/qsys_unb2_test.qip
 
 
 # vsim -L ... -L ... ...
diff --git a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
index 730162e0dfcc145b5720a0be42907d109ee9fb4e..b8bb280eccbfecc12a06e6959133cef0c99a29e7 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
@@ -21,3 +21,4 @@
 
 #source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_all_pins.tcl
 source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl