diff --git a/boards/uniboard2/designs/unb2_singlemac/build/quartus/unb2_singlemac.qpf b/boards/uniboard2/designs/unb2_singlemac/build/quartus/unb2_singlemac.qpf
new file mode 100644
index 0000000000000000000000000000000000000000..11488b07036de2f7d14ce05fa381b16a14647a27
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_singlemac/build/quartus/unb2_singlemac.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0a10.1 Build 374 09/02/2014 SJ Full Version
+# Date created = 13:59:19 November 14, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "13:59:19 November 14, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "unb2_singlemac"
diff --git a/boards/uniboard2/designs/unb2_singlemac/build/quartus/unb2_singlemac.qsf b/boards/uniboard2/designs/unb2_singlemac/build/quartus/unb2_singlemac.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..9a122c4f78c301ababc8a3c00cbc63be13c3ad8f
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_singlemac/build/quartus/unb2_singlemac.qsf
@@ -0,0 +1,75 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0a10.1 Build 374 09/02/2014 SJ Full Version
+# Date created = 13:59:19 November 14, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# unb2_singlemac_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115R2F40I2LG
+set_global_assignment -name TOP_LEVEL_ENTITY unb2_singlemac
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:59:19 NOVEMBER 14, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name QSYS_FILE ../../../unb2_test/src/ip/system_pll.qsys
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_evt.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_wdi_extend.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_counter.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pulser.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_pulser.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_async.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_areset.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_clk_rst.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_node_ctrl.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_common_pkg.vhd
+set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g.qsys
+set_global_assignment -name VHDL_FILE ../../../../../../libraries/technology/transceiver/tech_transceiver_arria10_1.vhd
+set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys
+set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys
+set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys
+set_global_assignment -name VHDL_FILE ../../src/vhdl/unb2_singlemac.vhd
+set_global_assignment -name SDC_FILE ../../src/sdc/unb2_singlemac.sdc
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/sdc/unb2_singlemac.sdc b/boards/uniboard2/designs/unb2_singlemac/src/sdc/unb2_singlemac.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..66a5daa09055c4a43f4c8d826551f6d170b367ae
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_singlemac/src/sdc/unb2_singlemac.sdc
@@ -0,0 +1,11 @@
+create_clock -period 5.000 -name {CLK} { CLK }
+create_clock -period 1.552 -name {SA_CLK} { SA_CLK }
+create_clock -period 1.552 -name {SB_CLK} { SB_CLK }
+#create_clock -period 40.000 -name {ETH_clk} { ETH_clk }
+
+derive_pll_clocks
+
+set_clock_groups -asynchronous -group [get_clocks {u_system_pll|system_pll_inst|altera_pll_i|outclk_wire[0]}]
+set_clock_groups -asynchronous -group [get_clocks {u_system_pll|system_pll_inst|altera_pll_i|outclk_wire[1]}]
+set_false_path -from [get_clocks {*cpulse_out_bus[0]}] -to [get_clocks {*wys|clk_divtx_user}]
+set_false_path -from [get_clocks {*wys|clk_divtx_user}] -to [get_clocks {*cpulse_out_bus[0]}]
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1b2d33fe4f2bdc0121ee5d0fd3b8ffbbc8545e88
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
@@ -0,0 +1,385 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, unb_common_lib;
+use unb_common_lib.unb_common_pkg.all;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+ENTITY unb2_singlemac IS
+ port (
+
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- External system clock
+ PPS : IN STD_LOGIC; -- External system sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- 1GbE Control Interfaces
+ ETH_CLK : in std_logic;
+ ETH_SGIN : in std_logic_vector (1 downto 0);
+ ETH_SGOUT : out std_logic_vector (1 downto 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC; -- SerDes reference clock front
+ SB_CLK : IN STD_LOGIC; -- SerDes reference clock back
+ BCK_REF_CLK : IN STD_LOGIC; -- SerDes reference clock back
+
+ -- SO-DIMM DDR4 Memory Bank i2c (common)
+ MB_SCL : inout std_logic;
+ MB_SDA : inout std_logic;
+ -- SO-DIMM DDR4 Memory Bank I
+ MB_I_RZQ : in STD_LOGIC;
+ MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
+ MB_I_A : out std_logic_vector (13 downto 0);
+ MB_I_ACT_N : out std_logic_vector(0 downto 0);
+ MB_I_BA : out std_logic_vector (1 downto 0);
+ MB_I_BG : out std_logic_vector (1 downto 0);
+ MB_I_CAS_A15 : out std_logic;
+ MB_I_CB : inout std_logic_vector (7 downto 0);
+ MB_I_CK : out std_logic_vector (1 downto 0);
+ MB_I_CK_n : out std_logic_vector (1 downto 0);
+ MB_I_CKE : out std_logic_vector (1 downto 0);
+ MB_I_CS : out std_logic_vector (1 downto 0);
+ MB_I_DM : inout std_logic_vector (8 downto 0);
+ MB_I_DQ : inout std_logic_vector (63 downto 0);
+ MB_I_DQS : inout std_logic_vector (8 downto 0);
+ MB_I_DQS_n : inout std_logic_vector (8 downto 0);
+ MB_I_ODT : out std_logic_vector (1 downto 0);
+ MB_I_PARITY : out std_logic_vector(0 downto 0);
+ MB_I_RAS_A16 : out std_logic;
+ MB_I_WE_A14 : out std_logic;
+ MB_I_RESET_N : out std_logic_vector(0 downto 0);
+ MB_I_ALERT_N : in std_logic_vector(0 downto 0);
+ -- SO-DIMM DDR4 Memory Bank II
+ MB_II_RZQ : in STD_LOGIC;
+ MB_II_REF_CLK : in STD_LOGIC; -- External reference clock
+ MB_II_A : out std_logic_vector (13 downto 0);
+ MB_II_ACT_N : out std_logic_vector(0 downto 0);
+ MB_II_BA : out std_logic_vector (1 downto 0);
+ MB_II_BG : out std_logic_vector (1 downto 0);
+ MB_II_CAS_A15 : out std_logic;
+ MB_II_CB : inout std_logic_vector (7 downto 0);
+ MB_II_CK : out std_logic_vector (1 downto 0);
+ MB_II_CK_n : out std_logic_vector (1 downto 0);
+ MB_II_CKE : out std_logic_vector (1 downto 0);
+ MB_II_CS : out std_logic_vector (1 downto 0);
+ MB_II_DM : inout std_logic_vector (8 downto 0);
+ MB_II_DQ : inout std_logic_vector (63 downto 0);
+ MB_II_DQS : inout std_logic_vector (8 downto 0);
+ MB_II_DQS_n : inout std_logic_vector (8 downto 0);
+ MB_II_ODT : out std_logic_vector (1 downto 0);
+ MB_II_PARITY : out std_logic_vector(0 downto 0);
+ MB_II_RAS_A16 : out std_logic;
+ MB_II_WE_A14 : out std_logic;
+ MB_II_RESET_N : out std_logic_vector(0 downto 0);
+ MB_II_ALERT_N : in std_logic_vector(0 downto 0);
+
+ -- back transceivers
+ BCK_SDA : inout std_logic_vector (2 downto 0);
+ BCK_SCL : inout std_logic_vector (2 downto 0);
+ BCK_ERR : inout std_logic_vector (2 downto 0);
+ -- pmbus
+ PMBUS_SC : inout std_logic;
+ PMBUS_SD : inout std_logic;
+ PMBUS_ALERT : in std_logic;
+ -- front transceivers
+ QSFP_0_RX : in std_logic_vector (0 downto 0);
+ QSFP_0_TX : out std_logic_vector (0 downto 0);
+ QSFP_SDA : inout std_logic_vector (5 downto 0);
+ QSFP_SCL : inout std_logic_vector (5 downto 0);
+ QSFP_RST : inout std_logic;
+ -- I2C Interface to Sensors
+ SENS_SC : inOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+ -- Others
+-- CFG_DATA : inout std_logic_vector (3 downto 0);
+ VERSION : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+
+end unb2_singlemac;
+
+
+architecture str of unb2_singlemac is
+
+
+
+ component system_pll is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X';
+ locked : out std_logic;
+ outclk_0 : out std_logic; -- outclk0
+ outclk_1 : out std_logic; -- outclk1
+ outclk_2 : out std_logic -- outclk2
+ );
+ end component system_pll;
+
+ component tech_transceiver_arria10_1 is
+ generic (
+ g_nof_channels : natural := 1
+ );
+ port (
+ clk : in std_logic;
+ reset_p : in std_logic;
+ refclk : in std_logic;
+ clk_156_arr : out std_logic_vector(0 DOWNTO 0);
+ clk_312_arr : out std_logic_vector(0 DOWNTO 0);
+ tx_serial_data : out std_logic_vector(0 downto 0);
+ rx_serial_data : in std_logic_vector(0 downto 0);
+ tx_parallel_data : in std_logic_vector(63 downto 0);
+ rx_parallel_data : out std_logic_vector(63 downto 0);
+ tx_control : in std_logic_vector(7 downto 0);
+ rx_control : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+
+ component ip_arria10_mac_10g is
+ port (
+ csr_read : in std_logic := 'X'; -- read
+ csr_write : in std_logic := 'X'; -- write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- readdata
+ csr_waitrequest : out std_logic; -- waitrequest
+ csr_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
+ tx_312_5_clk : in std_logic := 'X'; -- clk
+ tx_156_25_clk : in std_logic := 'X'; -- clk
+ rx_312_5_clk : in std_logic := 'X'; -- clk
+ rx_156_25_clk : in std_logic := 'X'; -- clk
+ csr_clk : in std_logic := 'X'; -- clk
+ csr_rst_n : in std_logic := 'X'; -- reset_n
+ tx_rst_n : in std_logic := 'X'; -- reset_n
+ rx_rst_n : in std_logic := 'X'; -- reset_n
+ avalon_st_tx_startofpacket : in std_logic := 'X'; -- startofpacket
+ avalon_st_tx_endofpacket : in std_logic := 'X'; -- endofpacket
+ avalon_st_tx_valid : in std_logic := 'X'; -- valid
+ avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
+ avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
+ avalon_st_tx_error : in std_logic := 'X'; -- error
+ avalon_st_tx_ready : out std_logic; -- ready
+ avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
+ xgmii_tx : out std_logic_vector(71 downto 0); -- data
+ avalon_st_txstatus_valid : out std_logic; -- valid
+ avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- data
+ avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- error
+ xgmii_rx : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0); -- data
+ avalon_st_rx_data : out std_logic_vector(63 downto 0); -- data
+ avalon_st_rx_startofpacket : out std_logic; -- startofpacket
+ avalon_st_rx_valid : out std_logic; -- valid
+ avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- empty
+ avalon_st_rx_error : out std_logic_vector(5 downto 0); -- error
+ avalon_st_rx_ready : in std_logic := 'X'; -- ready
+ avalon_st_rx_endofpacket : out std_logic; -- endofpacket
+ avalon_st_rxstatus_valid : out std_logic; -- valid
+ avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- data
+ avalon_st_rxstatus_error : out std_logic_vector(6 downto 0) -- error
+ );
+ end component ip_arria10_mac_10g;
+
+ -- constants
+ constant cs_sim : std_logic := '0';
+ constant cs_sync : std_logic := '1';
+ --CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
+ CONSTANT c_block_len : NATURAL := 1118;-- = 8944 user bytes. Including packetizing: 9012 bytes.
+
+ -- general reset and clock signals
+ signal reset_n : std_logic := '0';
+ signal reset_p : std_logic := '0';
+ signal pout_wdi : std_logic := '0';
+ signal sys_clk : std_logic := '0';
+ signal sys_locked : std_logic := '0';
+ signal mm_clk : std_logic := '0';
+ signal clk_125 : std_logic := '0';
+
+
+ -- signals for the transceivers
+ signal tx_serial_data_front : std_logic_vector(0 downto 0);
+ signal rx_serial_data_front : std_logic_vector(0 downto 0);
+ signal xgmii_tx : std_logic_vector(71 downto 0);
+ signal xgmii_rx : std_logic_vector(71 downto 0);
+ signal clk_156 : std_logic_vector(0 downto 0);
+ signal clk_312 : std_logic_vector(0 downto 0);
+
+ -- signals for the MAC
+ signal mac_10g_loopback_sop : std_logic;
+ signal mac_10g_loopback_eop : std_logic;
+ signal mac_10g_loopback_valid : std_logic;
+ signal mac_10g_loopback_ready : std_logic;
+ signal mac_10g_loopback_data : std_logic_vector(63 downto 0);
+ signal mac_10g_loopback_empty : std_logic_vector(2 downto 0);
+ signal mac_10g_loopback_err : std_logic_vector(5 downto 0);
+
+ signal reg_mac_rd : std_logic;
+ signal reg_mac_wr : std_logic;
+ signal reg_mac_waitrequest : std_logic;
+ signal reg_mac_rddata : std_logic_vector(31 downto 0);
+ signal reg_mac_wrdata : std_logic_vector(31 downto 0);
+ signal reg_mac_address : std_logic_vector(12 downto 0);
+
+
+ -- signals for the bidirectional and misc ios
+ signal inta_in : std_logic;
+ signal intb_in : std_logic;
+ signal testio_in : std_logic_vector(7 downto 0);
+ signal bck_err_in : std_logic_vector(2 downto 0);
+ signal inta_out : std_logic;
+ signal intb_out : std_logic;
+ signal testio_out : std_logic_vector(7 downto 0);
+ signal bck_err_out : std_logic_vector(2 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
+
+begin
+
+ WDI <= 'Z';
+
+-- -- ****** Front side transceivers and MAC ******
+--
+ QSFP_0_TX <= tx_serial_data_front;
+ rx_serial_data_front <= QSFP_0_RX;
+
+ u_transceiver: tech_transceiver_arria10_1
+ generic map (
+ g_nof_channels => 1
+ )
+ port map(
+ clk => mm_clk,
+ reset_p => reset_p,
+ refclk => SA_CLK,
+ clk_156_arr => clk_156,
+ clk_312_arr => clk_312,
+ tx_serial_data => tx_serial_data_front,
+ rx_serial_data => rx_serial_data_front,
+ tx_parallel_data => xgmii_tx(63 downto 0),
+ rx_parallel_data => xgmii_rx(63 downto 0),
+ tx_control => xgmii_tx(71 downto 64),
+ rx_control => xgmii_rx(71 downto 64)
+ );
+
+ u0 : ip_arria10_mac_10g
+ port map (
+ csr_read => reg_mac_rd,
+ csr_write => reg_mac_wr,
+ csr_writedata => reg_mac_wrdata(31 downto 0),
+ csr_readdata => reg_mac_rddata(31 downto 0),
+ csr_waitrequest => reg_mac_waitrequest,
+ csr_address => reg_mac_address(12 downto 0),
+ tx_312_5_clk => clk_312(0),
+ tx_156_25_clk => clk_156(0),
+ rx_312_5_clk => clk_312(0),
+ rx_156_25_clk => clk_156(0),
+ csr_clk => mm_clk,
+ csr_rst_n => reset_n,
+ tx_rst_n => reset_n,
+ rx_rst_n => reset_n,
+ avalon_st_tx_startofpacket => mac_10g_loopback_sop,
+ avalon_st_tx_endofpacket => mac_10g_loopback_eop,
+ avalon_st_tx_valid => mac_10g_loopback_valid,
+ avalon_st_tx_data => mac_10g_loopback_data,
+ avalon_st_tx_empty => mac_10g_loopback_empty,
+ avalon_st_tx_error => mac_10g_loopback_err(0),
+ avalon_st_tx_ready => mac_10g_loopback_ready,
+ avalon_st_pause_data => (others => '0'),
+ xgmii_tx => xgmii_tx,
+ avalon_st_txstatus_valid => open,
+ avalon_st_txstatus_data => open,
+ avalon_st_txstatus_error => open,
+ xgmii_rx => xgmii_rx,
+ link_fault_status_xgmii_rx_data => open,
+ avalon_st_rx_data => mac_10g_loopback_data,
+ avalon_st_rx_startofpacket => mac_10g_loopback_sop,
+ avalon_st_rx_valid => mac_10g_loopback_valid,
+ avalon_st_rx_empty => mac_10g_loopback_empty(2 downto 0),
+ avalon_st_rx_error => mac_10g_loopback_err(5 downto 0),
+ avalon_st_rx_ready => mac_10g_loopback_ready,
+ avalon_st_rx_endofpacket => mac_10g_loopback_eop,
+ avalon_st_rxstatus_valid => open,
+ avalon_st_rxstatus_data => open,
+ avalon_st_rxstatus_error => open
+ );
+
+
+ -- ****** node control for resets and wdi
+
+ u_node_ctrl : entity unb_common_lib.unb_node_ctrl
+ generic map (
+ g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => ETH_clk,
+ xo_rst_n => reset_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => open,
+ st_clk => clk,
+ st_rst => open,
+ wdi_in => pout_wdi,
+ wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ pulse_us => open,
+ pulse_ms => open,
+ pulse_s => open -- could be used to toggle a LED
+ );
+
+ reset_p <= not reset_n;
+
+ u_system_pll : system_pll
+ port map(
+ refclk => ETH_CLK,
+ rst => reset_p,
+ locked => sys_locked,
+ outclk_0 => mm_clk, -- 100MHz
+ outclk_1 => sys_clk, -- 300MHz
+ outclk_2 => clk_125 -- 125MHz for 1ge
+ );
+
+
+-- bidirectional and misc
+-- use PPS as output enable
+
+ INTA <= inta_out when PPS = '1' else 'Z';
+ INTB <= intb_out when PPS = '1' else 'Z';
+ TESTIO <= testio_out when PPS = '1' else "ZZZZZZZZ";
+ BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
+
+ inta_in <= INTA;
+ intb_in <= INTB;
+ testio_in <= TESTIO;
+ bck_err_in <= BCK_ERR;
+
+ inta_out <= intb_in;
+ intb_out <= inta_in;
+ testio_out(7 downto 4) <= testio_in(3 downto 0);
+ testio_out(3 downto 0) <= testio_in(7 downto 4);
+ bck_err_out(2) <= bck_err_in(1);
+ bck_err_out(1) <= bck_err_in(0);
+ bck_err_out(0) <= bck_err_in(2);
+
+
+ ver_id_pmbusalert <= version & id & pmbus_alert;
+
+end str;