diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2ce081db9c558bdb160d5c5dcdbf79557fd1a24c
--- /dev/null
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -0,0 +1,46 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author: E. Kooistra
+-- Purpose: Keep parameters of DP components
+-- Description:
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+PACKAGE dp_components_pkg IS
+
+ CONSTANT c_dp_clk_MHz : NATURAL := 200;
+ CONSTANT c_dp_sync_timeout : NATURAL := c_dp_clk_MHz*10**6 + c_dp_clk_MHz*10**5; -- 10% margin for nominal 1 s
+
+ CONSTANT c_dp_bsn_monitor_v2_reg_adr_w : NATURAL := ceil_log2(7); -- = 3
+
+ CONSTANT c_dp_strobe_total_count_reg_adr_w : NATURAL := ceil_log2(15*2 + 1); -- = 5
+ CONSTANT c_dp_strobe_total_count_nof_counts_max : NATURAL := 2**c_dp_strobe_total_count_reg_adr_w / 2 - 1;
+
+END dp_components_pkg;
+
+
+PACKAGE BODY dp_components_pkg IS
+END dp_components_pkg;
+
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 19c033c715a2f338236f57fe02356754f8ac4aa5..cae82db6f7ce41435ef8c336817327f5402936c8 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -23,7 +23,7 @@
-- Purpose:
-- Count strobes
-- Description:
--- * g_nof_counts >= 1, maximum g_nof_counts_max = 15
+-- * g_nof_counts >= 1, maximum c_nof_counts_max = 15
-- There are g_nof_counts in parallel, one clear that clears them all
-- . count any strobe like e.g. sync, sop, valid, error flag, ...
-- . MM read or write of clear registers clears all counter immediately,
@@ -43,7 +43,8 @@
--
-------------------------------------------------------------------------------
-- REGMAP
--- . address span is (g_nof_counts_max + 1)*2 = 32
+-- . address span is (c_nof_counts_max + 1)*2 = 32
+-- . address width is c_dp_strobe_total_count_reg_adr_w - ceil_log2(32) = 5
-------------------------------------------------------------------------------
-- wi Bits R/W Name Default
-- ===========================================================================
@@ -57,23 +58,27 @@
-- (g_nof_counts-1)*2 + 1 [63.32]
-- . . . . .
-- . .
--- (g_nof_counts_max-1)*2 [31..0] RO count[g_nof_counts_max-1] 0x0
--- (g_nof_counts_max-1)*2 + 1 [63.32]
--- g_nof_counts_max*2 [31..0] RW clear 0x0
--- g_nof_counts_max*2 + 1 [31..0] RO rsvd 0x0
+-- (c_nof_counts_max-1)*2 [31..0] RO count[c_nof_counts_max-1] 0x0
+-- (c_nof_counts_max-1)*2 + 1 [63.32]
+-- c_nof_counts_max*2 [31..0] RW clear 0x0
+-- c_nof_counts_max*2 + 1 [31..0] RO rsvd 0x0
-- ===========================================================================
--
+-- Remark:
+-- * This dp_strobe_total_count could have been a common_strobe_total_count
+-- component, because it does not use sosi/siso signals. However it is fine
+-- to keep it in dp_lib, to avoid extra work of moving and renaming.
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE work.dp_components_pkg.ALL;
ENTITY dp_strobe_total_count IS
GENERIC (
g_mm_w : NATURAL := c_word_w;
- g_nof_counts_max : NATURAL := 15; -- fixed by REGMAP
- g_nof_counts : NATURAL := 1; -- actual nof counts, <= g_nof_counts_max
+ g_nof_counts : NATURAL := 1; -- actual nof counts, <= c_nof_counts_max
g_count_w : NATURAL := c_longword_w; -- actual count width, max is c_longword_w due to two mm word width
g_clip : BOOLEAN := TRUE
);
@@ -94,12 +99,13 @@ END dp_strobe_total_count;
ARCHITECTURE rtl OF dp_strobe_total_count IS
- CONSTANT c_nof_words : NATURAL := g_nof_counts_max*2 + 1; -- +1 for clear
- CONSTANT c_clear_adr : NATURAL := g_nof_counts_max*2; -- after counters in REGMAP
+ CONSTANT c_nof_counts_max : NATURAL := c_dp_strobe_total_count_nof_counts_max; -- fixed by REGMAP
+ CONSTANT c_nof_words : NATURAL := c_nof_counts_max*2 + 1; -- +1 for clear
+ CONSTANT c_clear_adr : NATURAL := c_nof_counts_max*2; -- after counters in REGMAP
-- Define the size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_words),
+ adr_w => c_dp_strobe_total_count_reg_adr_w,
dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => c_nof_words,
init_sl => '0');
@@ -119,7 +125,7 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS
BEGIN
- ASSERT g_nof_counts <= g_nof_counts_max REPORT "Too many counters to fit REGMAP." SEVERITY FAILURE;
+ ASSERT g_nof_counts <= c_nof_counts_max REPORT "Too many counters to fit REGMAP." SEVERITY FAILURE;
ASSERT g_count_w <= g_mm_w*2 REPORT "Too wide counter to fit REGMAP." SEVERITY FAILURE;
mm_cnt_clr <= (reg_mosi.rd OR reg_mosi.wr) WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = c_clear_adr ELSE '0' ;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
index 64bf0567a6ecd37bef46fb2db0a67ed9019d7af9..e94f3f21cc44c4a2f35572ae75c37fa6dd1c6512 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
@@ -29,12 +29,13 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.dp_stream_pkg.ALL;
+USE work.dp_components_pkg.ALL;
ENTITY mms_dp_bsn_monitor_v2 IS
GENERIC (
g_nof_streams : POSITIVE := 1;
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
- g_sync_timeout : NATURAL := 200*10**6;
+ g_sync_timeout : NATURAL := c_dp_sync_timeout;
g_bsn_w : NATURAL := c_dp_stream_bsn_w;
g_error_bi : NATURAL := 0;
g_cnt_sop_w : NATURAL := c_word_w;
@@ -61,7 +62,7 @@ END mms_dp_bsn_monitor_v2;
ARCHITECTURE str OF mms_dp_bsn_monitor_v2 IS
- CONSTANT c_reg_adr_w : NATURAL := ceil_log2(7);
+ CONSTANT c_reg_adr_w : NATURAL := c_dp_bsn_monitor_v2_reg_adr_w;
SIGNAL mon_evt_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL mon_sync_timeout_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);