diff --git a/applications/apertif/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd b/applications/apertif/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
index 1336a9c50ec3b5bf6d14ea5e20a3f11d6fc8767f..cf3083653a31754240aec997122efb906bba5c9c 100644
--- a/applications/apertif/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+++ b/applications/apertif/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
@@ -20,20 +20,22 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, correlator_lib, diag_lib, dp_lib, rTwoSDF_lib, wpfb_lib, st_lib, filter_lib, fft_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, correlator_lib, diag_lib, dp_lib, eth_lib, tech_tse_lib, tr_10GbE_lib, apertif_unb1_fn_beamformer_lib, wpfb_lib ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE rTwoSDF_lib.rTwoSDFPkg.ALL;
-USE st_lib.ALL;
-USE filter_lib.ALL;
-USE filter_lib.fil_pkg.ALL;
-USE fft_lib.ALL;
-USE fft_lib.fft_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE apertif_unb1_fn_beamformer_lib.apertif_unb1_fn_beamformer_udp_offload_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
ENTITY apertif_unb1_correlator IS
@@ -48,25 +50,45 @@ ENTITY apertif_unb1_correlator IS
);
PORT (
-- GENERAL
- CLK : IN STD_LOGIC; -- System Clock
- PPS : IN STD_LOGIC; -- System Sync
- WDI : OUT STD_LOGIC; -- Watchdog Clear
- INTA : INOUT STD_LOGIC; -- FPGA interconnect line
- INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-
- -- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
- sens_sc : INOUT STD_LOGIC;
- sens_sd : INOUT STD_LOGIC;
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
-- 1GbE Control Interface
- ETH_clk : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC;
- ETH_SGOUT : OUT STD_LOGIC
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+
+ -- Serial I/O
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- So we need to assign a '1' to it.
);
END apertif_unb1_correlator;
@@ -77,50 +99,94 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 1);
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 0, 0, 0, 1);
-
- -- System
- SIGNAL cs_sim : STD_LOGIC;
- SIGNAL xo_clk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_locked : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
- SIGNAL dp_rst : STD_LOGIC;
- SIGNAL dp_clk : STD_LOGIC;
-
- -- PIOs
- SIGNAL pout_wdi : STD_LOGIC;
+ CONSTANT c_nof_10GbE_streams : NATURAL := 3; -- The number of 10G input streams
- -- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL sa_rst : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
-- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi;
- SIGNAL reg_ppsh_miso : t_mem_miso;
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- Interface: 10GbE
+ SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+ SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+
+ -- DP offload
+ SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
- -- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
-
- -- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
-
- -- eth1g
- SIGNAL eth1g_tse_clk : STD_LOGIC;
- SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+
+ -- BSN Alignern + FIFO's
+ CONSTANT c_block_period : NATURAL := 256;
+ CONSTANT c_block_size : NATURAL := 176;
+ CONSTANT c_bsn_align_latency : NATURAL := 3;
+ CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
+ CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
+ CONSTANT c_dp_fifo_size : NATURAL := (c_bsn_align_latency + 5) * c_block_size; -- be able to fit blocks for as long as sop time out;
+ CONSTANT c_dp_fifo_fill : NATURAL := c_block_size;
+
+ SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_bsn_align_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL dp_bsn_align_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-- Correlator
CONSTANT c_nof_inputs : NATURAL := sel_a_b(g_sim, 24, 24);
@@ -211,21 +277,217 @@ BEGIN
-- To replace block generators: 10GbE receivers 0..2
-----------------------------------------------------------------------------
-- Placeholder
+ -----------------------------------------------------------------------------
+ -- Interface : 10GbE
+ -----------------------------------------------------------------------------
+ -- Wire together different types
+ gen_wires: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ unb_xaui_tx_arr(i) <= xaui_tx_arr(i);
+ xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
+ END GENERATE;
+
+ u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
+ GENERIC MAP (
+ g_nof_xaui => c_nof_10GbE_streams
+ )
+ PORT MAP (
+ xaui_tx_arr => unb_xaui_tx_arr,
+ xaui_rx_arr => unb_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
+
+ u_areset_sa_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ PORT MAP(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_streams,
+ g_use_mdio => TRUE
+ )
+
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk, --cal_clk, # required for XAUI
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- RX: dp_offload_rx
+ -----------------------------------------------------------------------------
+ u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx_dev
+ GENERIC MAP (
+ g_nof_streams => c_nof_10GbE_streams,
+ g_data_w => c_xgmii_data_w,
+ g_hdr_field_arr => c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr,
+ g_remove_crc => TRUE,
+ g_crc_nof_words => 1
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
+
+ gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_sync" )));
+ dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
+
+ dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ END GENERATE;
+
-----------------------------------------------------------------------------
-- To replace block generators: BSN aligner
-- . Produces 3 aligned streams
-----------------------------------------------------------------------------
- -- Placeholder
+ -----------------------------------------------------------------------------
+ -- RX: BSN alignment
+ -----------------------------------------------------------------------------
+ gen_dp_fifo_fill: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_use_bsn => TRUE,
+ g_use_channel => TRUE,
+ g_use_error => TRUE,
+ g_use_sync => TRUE,
+ g_fifo_fill => c_dp_fifo_fill,
+ g_fifo_size => c_dp_fifo_size
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_offload_rx_src_in_arr(i),
+ snk_in => dp_offload_rx_restored_src_out_arr(i),
+
+ src_in => dp_fifo_fill_src_in_arr(i),
+ src_out => dp_fifo_fill_src_out_arr(i)
+ );
+ END GENERATE;
+
+ u_dp_bsn_align : ENTITY dp_lib.dp_bsn_align
+ GENERIC MAP (
+ g_block_size => c_block_size,
+ g_block_period => c_block_period,
+ g_nof_input => c_nof_10GbE_streams,
+ g_xoff_timeout => c_bsn_align_xoff_timeout,
+ g_sop_timeout => c_bsn_align_sop_timeout,
+ g_bsn_latency => c_bsn_align_latency,
+ g_bsn_request_pipeline => 2
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_fifo_fill_src_in_arr,
+ snk_in_arr => dp_fifo_fill_src_out_arr,
+
+ src_in_arr => dp_bsn_align_src_in_arr,
+ src_out_arr => dp_bsn_align_src_out_arr
+ );
-----------------------------------------------------------------------------
-- To replace block generators:
-- . Extracts
-----------------------------------------------------------------------------
- -- Placeholder
-
-
-
+ -----------------------------------------------------------------------------
+ -- Rewire: for each input stream, extract the 4 concatenated BF output streams
+ -- and assign to its own _2arr dimension
+ -----------------------------------------------------------------------------
+ p_extract_bf_streams : PROCESS(dp_bsn_align_src_out_arr)
+ BEGIN
+ FOR i IN 0 TO c_nof_10GbE_streams-1 LOOP
+ FOR j IN 0 TO c_nof_bf_modules-1 LOOP
+-- dp_bsn_align_src_out_2arr(i)(j) <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl
+-- dp_bsn_align_src_out_2arr(i)(j).data <= (OTHERS=>'0');
+-- dp_bsn_align_src_out_2arr(i)(j).im <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w));
+-- dp_bsn_align_src_out_2arr(i)(j).re <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w));
+
+ wpfb_snk_in_arr(i*c_nof_bf_modules + j) <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl
+ wpfb_snk_in_arr(i*c_nof_bf_modules + j).data <= (OTHERS=>'0');
+ wpfb_snk_in_arr(i*c_nof_bf_modules + j).im <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w));
+ wpfb_snk_in_arr(i*c_nof_bf_modules + j).re <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w));
+ END LOOP;
+ END LOOP;
+ END PROCESS;
-----------------------------------------------------------------------------
-- WPFB