diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index 0b0118a03eb0d4f5fe886c21928da165141dda9a..3b96557c5324b29b7a32bd0f443437d7d5f1a326 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -65,100 +65,103 @@
type = "String";
}
}
- element reg_diag_bg_10GbE.mem
+ element reg_diag_data_buffer_10GbE.mem
{
datum baseAddress
{
- value = "12960";
+ value = "12416";
type = "long";
}
}
- element reg_bsn_monitor_ddr.mem
+ element reg_mmdp_data.mem
{
datum baseAddress
{
- value = "12736";
+ value = "53288";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element reg_dp_offload_rx_10GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "393216";
+ value = "13312";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element reg_diag_data_buffer_ddr.mem
{
datum baseAddress
{
- value = "262144";
+ value = "12544";
type = "long";
}
}
- element reg_dpmm_ctrl.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "13040";
+ value = "12992";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element reg_diag_bg_10GbE.mem
{
datum baseAddress
{
- value = "13048";
+ value = "13152";
type = "long";
}
}
- element reg_dp_offload_tx_1GbE.mem
+ element reg_remu.mem
{
datum baseAddress
{
- value = "13080";
+ value = "13024";
type = "long";
}
}
- element reg_dp_offload_rx_10GbE_hdr_dat.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "13312";
+ value = "53264";
type = "long";
}
}
- element reg_mmdp_ctrl.mem
+ element reg_diag_rx_seq_ddr.mem
{
datum baseAddress
{
- value = "13056";
+ value = "13248";
type = "long";
}
}
- element ram_diag_data_buffer_ddr.mem
+ element reg_diag_bg_ddr.mem
{
datum baseAddress
{
- value = "524288";
+ value = "13184";
type = "long";
}
}
- element rom_system_info.mem
+ element reg_bsn_monitor_10GbE.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "768";
+ type = "long";
}
+ }
+ element reg_bsn_monitor_1GbE.mem
+ {
datum baseAddress
{
- value = "4096";
+ value = "12800";
type = "long";
}
}
- element reg_dp_offload_tx_10GbE.mem
+ element reg_diag_tx_seq_10gbe.mem
{
datum baseAddress
{
@@ -166,120 +169,123 @@
type = "long";
}
}
- element reg_diag_data_buffer_ddr.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "12544";
+ value = "393216";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_io_ddr.mem
{
- datum _lockedAddress
+ datum baseAddress
{
- value = "1";
- type = "boolean";
+ value = "13280";
+ type = "long";
}
+ }
+ element pio_pps.mem
+ {
datum baseAddress
{
- value = "0";
+ value = "53296";
type = "long";
}
}
- element ram_diag_data_buffer_10GbE.mem
+ element reg_diag_tx_seq_ddr.mem
{
datum baseAddress
{
- value = "458752";
+ value = "53248";
type = "long";
}
}
- element ram_diag_bg_10GbE.mem
+ element reg_diag_bg_1GbE.mem
{
datum baseAddress
{
- value = "16384";
+ value = "13088";
type = "long";
}
}
- element reg_dp_offload_tx_10GbE_hdr_dat.mem
+ element ram_diag_bg_ddr.mem
{
datum baseAddress
{
- value = "1024";
+ value = "49152";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element ram_diag_data_buffer_10GbE.mem
{
datum baseAddress
{
- value = "13064";
+ value = "458752";
type = "long";
}
}
- element ram_diag_data_buffer_1GbE.mem
+ element ram_diag_bg_10GbE.mem
{
datum baseAddress
{
- value = "65536";
+ value = "16384";
type = "long";
}
}
- element reg_bsn_monitor_1GbE.mem
+ element reg_dp_offload_tx_1GbE.mem
{
datum baseAddress
{
- value = "12672";
+ value = "53304";
type = "long";
}
}
- element reg_unb_sens.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "12800";
+ value = "53272";
type = "long";
}
}
- element reg_diag_bg_ddr.mem
+ element reg_diag_rx_seq_1gbe.mem
{
datum baseAddress
{
- value = "12992";
+ value = "13216";
type = "long";
}
}
- element pio_pps.mem
+ element ram_diag_bg_1GbE.mem
{
datum baseAddress
{
- value = "13072";
+ value = "45056";
type = "long";
}
}
- element reg_bsn_monitor_10GbE.mem
+ element reg_dp_offload_rx_1GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "768";
+ value = "256";
type = "long";
}
}
- element reg_remu.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "12832";
+ value = "32768";
type = "long";
}
}
- element ram_diag_bg_ddr.mem
+ element ram_diag_data_buffer_1GbE.mem
{
datum baseAddress
{
- value = "49152";
+ value = "65536";
type = "long";
}
}
@@ -296,11 +302,11 @@
type = "long";
}
}
- element reg_dp_offload_rx_1GbE_hdr_dat.mem
+ element reg_diag_rx_seq_10gbe.mem
{
datum baseAddress
{
- value = "256";
+ value = "12672";
type = "long";
}
}
@@ -308,23 +314,28 @@
{
datum baseAddress
{
- value = "12864";
+ value = "13056";
type = "long";
}
}
- element reg_diag_data_buffer_10GbE.mem
+ element pio_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12416";
+ value = "0";
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "32768";
+ value = "262144";
type = "long";
}
}
@@ -336,11 +347,27 @@
type = "long";
}
}
- element ram_diag_bg_1GbE.mem
+ element reg_mmdp_ctrl.mem
{
datum baseAddress
{
- value = "45056";
+ value = "53280";
+ type = "long";
+ }
+ }
+ element reg_bsn_monitor_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "12864";
+ type = "long";
+ }
+ }
+ element ram_diag_data_buffer_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
type = "long";
}
}
@@ -352,19 +379,40 @@
type = "long";
}
}
- element reg_io_ddr.mem
+ element reg_dp_offload_tx_10GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "13024";
+ value = "1024";
type = "long";
}
}
- element reg_diag_bg_1GbE.mem
+ element reg_diag_tx_seq_1gbe.mem
+ {
+ datum baseAddress
+ {
+ value = "13296";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_tx_10GbE.mem
{
datum baseAddress
{
- value = "12896";
+ value = "13120";
type = "long";
}
}
@@ -486,7 +534,7 @@
{
datum _sortIndex
{
- value = "41";
+ value = "47";
type = "int";
}
}
@@ -562,6 +610,54 @@
type = "int";
}
}
+ element reg_diag_rx_seq_10gbe
+ {
+ datum _sortIndex
+ {
+ value = "42";
+ type = "int";
+ }
+ }
+ element reg_diag_rx_seq_1gbe
+ {
+ datum _sortIndex
+ {
+ value = "44";
+ type = "int";
+ }
+ }
+ element reg_diag_rx_seq_ddr
+ {
+ datum _sortIndex
+ {
+ value = "46";
+ type = "int";
+ }
+ }
+ element reg_diag_tx_seq_10gbe
+ {
+ datum _sortIndex
+ {
+ value = "41";
+ type = "int";
+ }
+ }
+ element reg_diag_tx_seq_1gbe
+ {
+ datum _sortIndex
+ {
+ value = "43";
+ type = "int";
+ }
+ }
+ element reg_diag_tx_seq_ddr
+ {
+ datum _sortIndex
+ {
+ value = "45";
+ type = "int";
+ }
+ }
element reg_dp_offload_rx_10GbE_hdr_dat
{
datum _sortIndex
@@ -638,7 +734,7 @@
{
datum _sortIndex
{
- value = "42";
+ value = "48";
type = "int";
}
}
@@ -706,11 +802,16 @@
type = "int";
}
}
- element pio_wdi.s1
+ element onchip_memory2_0.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12304";
+ value = "131072";
type = "long";
}
}
@@ -722,16 +823,11 @@
type = "long";
}
}
- element onchip_memory2_0.s1
+ element pio_wdi.s1
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "131072";
+ value = "12304";
type = "long";
}
}
@@ -758,7 +854,7 @@
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1429783651439" />
+ <parameter name="timeStamp" value="1430735732056" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
@@ -2521,6 +2617,216 @@
internal="ram_diag_data_buffer_ddr.reset"
type="conduit"
dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_readdata"
+ internal="reg_diag_rx_seq_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_read"
+ internal="reg_diag_rx_seq_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_writedata"
+ internal="reg_diag_rx_seq_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_write"
+ internal="reg_diag_rx_seq_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_address"
+ internal="reg_diag_rx_seq_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_clk"
+ internal="reg_diag_rx_seq_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_ddr_reset"
+ internal="reg_diag_rx_seq_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_readdata"
+ internal="reg_diag_tx_seq_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_read"
+ internal="reg_diag_tx_seq_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_writedata"
+ internal="reg_diag_tx_seq_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_write"
+ internal="reg_diag_tx_seq_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_address"
+ internal="reg_diag_tx_seq_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_clk"
+ internal="reg_diag_tx_seq_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_ddr_reset"
+ internal="reg_diag_tx_seq_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_readdata"
+ internal="reg_diag_rx_seq_1gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_read"
+ internal="reg_diag_rx_seq_1gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_writedata"
+ internal="reg_diag_rx_seq_1gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_write"
+ internal="reg_diag_rx_seq_1gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_address"
+ internal="reg_diag_rx_seq_1gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_clk"
+ internal="reg_diag_rx_seq_1gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_1gbe_reset"
+ internal="reg_diag_rx_seq_1gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_readdata"
+ internal="reg_diag_tx_seq_1gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_read"
+ internal="reg_diag_tx_seq_1gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_writedata"
+ internal="reg_diag_tx_seq_1gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_write"
+ internal="reg_diag_tx_seq_1gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_address"
+ internal="reg_diag_tx_seq_1gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_clk"
+ internal="reg_diag_tx_seq_1gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_1gbe_reset"
+ internal="reg_diag_tx_seq_1gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_readdata"
+ internal="reg_diag_rx_seq_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_read"
+ internal="reg_diag_rx_seq_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_writedata"
+ internal="reg_diag_rx_seq_10gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_write"
+ internal="reg_diag_rx_seq_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_address"
+ internal="reg_diag_rx_seq_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_clk"
+ internal="reg_diag_rx_seq_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_rx_seq_10gbe_reset"
+ internal="reg_diag_rx_seq_10gbe.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_readdata"
+ internal="reg_diag_tx_seq_10gbe.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_read"
+ internal="reg_diag_tx_seq_10gbe.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_writedata"
+ internal="reg_diag_tx_seq_10gbe.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_write"
+ internal="reg_diag_tx_seq_10gbe.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_address"
+ internal="reg_diag_tx_seq_10gbe.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_clk"
+ internal="reg_diag_tx_seq_10gbe.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_tx_seq_10gbe_reset"
+ internal="reg_diag_tx_seq_10gbe.reset"
+ type="conduit"
+ dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="125000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -2761,7 +3067,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x3080' end='0x3100' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x3100' end='0x3180' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3180' end='0x31C0' /><slave name='reg_bsn_monitor_ddr.mem' start='0x31C0' end='0x3200' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3220' /><slave name='reg_remu.mem' start='0x3220' end='0x3240' /><slave name='reg_epcs.mem' start='0x3240' end='0x3260' /><slave name='reg_diag_bg_1GbE.mem' start='0x3260' end='0x3280' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x3280' end='0x32A0' /><slave name='reg_diag_bg_10GbE.mem' start='0x32A0' end='0x32C0' /><slave name='reg_diag_bg_ddr.mem' start='0x32C0' end='0x32E0' /><slave name='reg_io_ddr.mem' start='0x32E0' end='0x32F0' /><slave name='reg_dpmm_ctrl.mem' start='0x32F0' end='0x32F8' /><slave name='reg_dpmm_data.mem' start='0x32F8' end='0x3300' /><slave name='reg_mmdp_ctrl.mem' start='0x3300' end='0x3308' /><slave name='reg_mmdp_data.mem' start='0x3308' end='0x3310' /><slave name='pio_pps.mem' start='0x3310' end='0x3318' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0x3318' end='0x3320' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10GbE.mem' start='0x4000' end='0x8000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_1GbE.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_bg_ddr.mem' start='0xC000' end='0xD000' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x80000' end='0x90000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x3080' end='0x3100' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x3100' end='0x3180' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x3180' end='0x3200' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3200' end='0x3240' /><slave name='reg_bsn_monitor_ddr.mem' start='0x3240' end='0x3280' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x3280' end='0x32C0' /><slave name='reg_unb_sens.mem' start='0x32C0' end='0x32E0' /><slave name='reg_remu.mem' start='0x32E0' end='0x3300' /><slave name='reg_epcs.mem' start='0x3300' end='0x3320' /><slave name='reg_diag_bg_1GbE.mem' start='0x3320' end='0x3340' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x3340' end='0x3360' /><slave name='reg_diag_bg_10GbE.mem' start='0x3360' end='0x3380' /><slave name='reg_diag_bg_ddr.mem' start='0x3380' end='0x33A0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x33A0' end='0x33C0' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x33C0' end='0x33E0' /><slave name='reg_io_ddr.mem' start='0x33E0' end='0x33F0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x33F0' end='0x3400' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10GbE.mem' start='0x4000' end='0x8000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_1GbE.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_bg_ddr.mem' start='0xC000' end='0xD000' /><slave name='reg_diag_tx_seq_ddr.mem' start='0xD000' end='0xD010' /><slave name='reg_dpmm_ctrl.mem' start='0xD010' end='0xD018' /><slave name='reg_dpmm_data.mem' start='0xD018' end='0xD020' /><slave name='reg_mmdp_ctrl.mem' start='0xD020' end='0xD028' /><slave name='reg_mmdp_data.mem' start='0xD028' end='0xD030' /><slave name='pio_pps.mem' start='0xD030' end='0xD038' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0xD038' end='0xD040' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x80000' end='0x90000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="125000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -2967,6 +3273,60 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_tx_seq_10gbe">
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_rx_seq_10gbe">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_tx_seq_1gbe">
+ <parameter name="g_adr_w" value="2" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_rx_seq_1gbe">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_tx_seq_ddr">
+ <parameter name="g_adr_w" value="2" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_rx_seq_ddr">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -3039,7 +3399,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x32c0" />
</connection>
<connection
kind="avalon"
@@ -3071,7 +3431,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3220" />
+ <parameter name="baseAddress" value="0x32e0" />
</connection>
<connection
kind="avalon"
@@ -3079,7 +3439,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x32f0" />
+ <parameter name="baseAddress" value="0xd010" />
</connection>
<connection
kind="avalon"
@@ -3087,7 +3447,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x32f8" />
+ <parameter name="baseAddress" value="0xd018" />
</connection>
<connection
kind="avalon"
@@ -3095,7 +3455,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3300" />
+ <parameter name="baseAddress" value="0xd020" />
</connection>
<connection
kind="avalon"
@@ -3103,7 +3463,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3308" />
+ <parameter name="baseAddress" value="0xd028" />
</connection>
<connection
kind="avalon"
@@ -3111,7 +3471,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3240" />
+ <parameter name="baseAddress" value="0x3300" />
</connection>
<connection
kind="avalon"
@@ -3119,7 +3479,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3310" />
+ <parameter name="baseAddress" value="0xd030" />
</connection>
<connection
kind="avalon"
@@ -3369,7 +3729,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_bsn_monitor_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3180" />
+ <parameter name="baseAddress" value="0x3200" />
</connection>
<connection
kind="reset"
@@ -3420,7 +3780,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3318" />
+ <parameter name="baseAddress" value="0xd038" />
</connection>
<connection
kind="avalon"
@@ -3472,7 +3832,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_bg_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3260" />
+ <parameter name="baseAddress" value="0x3320" />
</connection>
<connection
kind="avalon"
@@ -3641,7 +4001,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_io_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x32e0" />
+ <parameter name="baseAddress" value="0x33e0" />
</connection>
<connection
kind="reset"
@@ -3747,7 +4107,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3280" />
+ <parameter name="baseAddress" value="0x3340" />
</connection>
<connection
kind="clock"
@@ -3786,7 +4146,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_bg_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x32a0" />
+ <parameter name="baseAddress" value="0x3360" />
</connection>
<connection
kind="clock"
@@ -3888,7 +4248,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_bsn_monitor_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31c0" />
+ <parameter name="baseAddress" value="0x3240" />
</connection>
<connection
kind="clock"
@@ -3901,7 +4261,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_bg_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x32c0" />
+ <parameter name="baseAddress" value="0x3380" />
</connection>
<connection
kind="clock"
@@ -3942,4 +4302,142 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00080000" />
</connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_tx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_tx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_rx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_rx_seq_10gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_tx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_tx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_rx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_rx_seq_1gbe.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_tx_seq_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_tx_seq_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_rx_seq_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_rx_seq_ddr.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_tx_seq_10gbe.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_tx_seq_10gbe.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3280" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_rx_seq_10gbe.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_rx_seq_10gbe.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3180" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_tx_seq_1gbe.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_tx_seq_1gbe.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x33f0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_rx_seq_1gbe.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_rx_seq_1gbe.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x33a0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_tx_seq_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_tx_seq_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xd000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_rx_seq_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_rx_seq_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x33c0" />
+ </connection>
</system>
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 40d9aa6e1c6e677a2d3b50b863c525c7cff97a43..47e798d226406fd89120ba30523675c0b7c14bb9 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -757,6 +757,65 @@ BEGIN
reg_diag_data_buffer_ddr_write_export => reg_diag_data_buf_ddr_mosi.wr,
reg_diag_data_buffer_ddr_writedata_export => reg_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- reg_diag_tx_seq_10GbE
+ reg_diag_tx_seq_10GbE_address_export => reg_diag_tx_seq_10GbE_mosi.address(4-1 DOWNTO 0),
+ reg_diag_tx_seq_10GbE_clk_export => OPEN,
+ reg_diag_tx_seq_10GbE_read_export => reg_diag_tx_seq_10GbE_mosi.rd,
+ reg_diag_tx_seq_10GbE_readdata_export => reg_diag_tx_seq_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_10GbE_reset_export => OPEN,
+ reg_diag_tx_seq_10GbE_write_export => reg_diag_tx_seq_10GbE_mosi.wr,
+ reg_diag_tx_seq_10GbE_writedata_export => reg_diag_tx_seq_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- reg_diag_rx_seq_10GbE
+ reg_diag_rx_seq_10GbE_address_export => reg_diag_rx_seq_10GbE_mosi.address(5-1 DOWNTO 0),
+ reg_diag_rx_seq_10GbE_clk_export => OPEN,
+ reg_diag_rx_seq_10GbE_read_export => reg_diag_rx_seq_10GbE_mosi.rd,
+ reg_diag_rx_seq_10GbE_readdata_export => reg_diag_rx_seq_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_rx_seq_10GbE_reset_export => OPEN,
+ reg_diag_rx_seq_10GbE_write_export => reg_diag_rx_seq_10GbE_mosi.wr,
+ reg_diag_rx_seq_10GbE_writedata_export => reg_diag_rx_seq_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- reg_diag_tx_seq_1GbE
+ reg_diag_tx_seq_1GbE_address_export => reg_diag_tx_seq_1GbE_mosi.address(2-1 DOWNTO 0),
+ reg_diag_tx_seq_1GbE_clk_export => OPEN,
+ reg_diag_tx_seq_1GbE_read_export => reg_diag_tx_seq_1GbE_mosi.rd,
+ reg_diag_tx_seq_1GbE_readdata_export => reg_diag_tx_seq_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_1GbE_reset_export => OPEN,
+ reg_diag_tx_seq_1GbE_write_export => reg_diag_tx_seq_1GbE_mosi.wr,
+ reg_diag_tx_seq_1GbE_writedata_export => reg_diag_tx_seq_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- reg_diag_rx_seq_1GbE
+ reg_diag_rx_seq_1GbE_address_export => reg_diag_rx_seq_1GbE_mosi.address(3-1 DOWNTO 0),
+ reg_diag_rx_seq_1GbE_clk_export => OPEN,
+ reg_diag_rx_seq_1GbE_read_export => reg_diag_rx_seq_1GbE_mosi.rd,
+ reg_diag_rx_seq_1GbE_readdata_export => reg_diag_rx_seq_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_rx_seq_1GbE_reset_export => OPEN,
+ reg_diag_rx_seq_1GbE_write_export => reg_diag_rx_seq_1GbE_mosi.wr,
+ reg_diag_rx_seq_1GbE_writedata_export => reg_diag_rx_seq_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+ -- reg_diag_tx_seq_ddr
+ reg_diag_tx_seq_ddr_address_export => reg_diag_tx_seq_ddr_mosi.address(2-1 DOWNTO 0),
+ reg_diag_tx_seq_ddr_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_read_export => reg_diag_tx_seq_ddr_mosi.rd,
+ reg_diag_tx_seq_ddr_readdata_export => reg_diag_tx_seq_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_tx_seq_ddr_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_write_export => reg_diag_tx_seq_ddr_mosi.wr,
+ reg_diag_tx_seq_ddr_writedata_export => reg_diag_tx_seq_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- reg_diag_rx_seq_ddr
+ reg_diag_rx_seq_ddr_address_export => reg_diag_rx_seq_ddr_mosi.address(3-1 DOWNTO 0),
+ reg_diag_rx_seq_ddr_clk_export => OPEN,
+ reg_diag_rx_seq_ddr_read_export => reg_diag_rx_seq_ddr_mosi.rd,
+ reg_diag_rx_seq_ddr_readdata_export => reg_diag_rx_seq_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_rx_seq_ddr_reset_export => OPEN,
+ reg_diag_rx_seq_ddr_write_export => reg_diag_rx_seq_ddr_mosi.wr,
+ reg_diag_rx_seq_ddr_writedata_export => reg_diag_rx_seq_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+
+
-- ram_ss_ss_wide
ram_ss_ss_wide_address_export => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w-1 DOWNTO 0),
ram_ss_ss_wide_clk_export => OPEN,
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index f78c1f804acb2116daa9ecc22d5357da1200c105..eb56afedc7ad2e8ea46dc33979fbe788c4d04ecc 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -305,7 +305,49 @@ PACKAGE qsys_unb1_test_pkg IS
ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_reset_export : out std_logic -- export
+ ram_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic -- export
);
end component qsys_unb1_test;