diff --git a/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd b/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
index 0998a2ba456daf1c1886354474ce7297db0544ae..7b84e5acf313f073458390f5ce53bab87d86f58b 100644
--- a/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
+++ b/applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd
@@ -163,9 +163,9 @@ BEGIN
  
   u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
   GENERIC MAP( 
-    g_sim                    => g_sim,
     g_technology             => g_tech_select_default,
-    g_tech_ddr               => c_tech_ddr,      
+    g_tech_ddr               => c_tech_ddr,
+    g_use_ddr_memory_model   => FALSE, 
     g_cross_domain_dvr_ctlr  => FALSE, 
     g_wr_data_w              => c_wr_data_w,     
     g_wr_fifo_depth          => c_wr_fifo_depth, 
diff --git a/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd b/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd
index a10576812c597007601b4f5f96c76579b6ef2a8c..8ca33028b5f4c710594ac86a43b0f7710ce97bc8 100644
--- a/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd
+++ b/applications/unb1_reorder/tb/vhdl/tb_unb1_reorder.vhd
@@ -140,7 +140,8 @@ BEGIN
     GENERIC MAP (
       g_sim         => c_sim,
       g_sim_unb_nr  => c_unb_nr,
-      g_sim_node_nr => c_node_nr
+      g_sim_node_nr => c_node_nr,
+      g_tech_ddr    => c_ddr
     )
     PORT MAP (
       -- GENERAL
@@ -169,6 +170,19 @@ BEGIN
       
     );
 
+  ------------------------------------------------------------------------------
+  -- DDR3 memory model
+  ------------------------------------------------------------------------------
+  u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+  GENERIC MAP (
+    g_sim      => TRUE,
+    g_tech_ddr => c_ddr
+  )
+  PORT MAP (
+    mem_in => phy_ou(0),
+    mem_io => phy_io(0)
+  );
+  
   ------------------------------------------------------------------------------
   -- UniBoard sensors
   ------------------------------------------------------------------------------