diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index 7485a037c978ee492fdb78a871ebd50836c5ef33..4910d02f8418de17f47ddc563947d18345997109 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -53,7 +53,7 @@ ENTITY ddr3 IS
     g_flush_sop_start_channel : NATURAL := 0;
     g_flush_nof_channels      : NATURAL := 0
   );                      
-  PORT (   
+  PORT (
     -- MM clock + reset                                                             
     mm_rst             : IN    STD_LOGIC := '0';                                           
     mm_clk             : IN    STD_LOGIC := '0';                                                          
@@ -325,34 +325,24 @@ BEGIN
   mm_reg_io_ddr <= RESIZE_UVEC(local_cal_fail & local_cal_success & i_ctlr_gen_rst & flush_ena & i_ctlr_rdy & i_ctlr_init_done, 32);   
 
 
-
-
-
-
   ser_term_ctrl_out <= term_ctrl_out.seriesterminationcontrol;
   par_term_ctrl_out <= term_ctrl_out.parallelterminationcontrol;
   term_ctrl_in.seriesterminationcontrol   <= ser_term_ctrl_in;
   term_ctrl_in.parallelterminationcontrol <= par_term_ctrl_in;
 
-
-
   ctlr_tech_mosi.burstbegin <= ctlr_burst;
-  ctlr_tech_mosi.address    <= RESIZE_UVEC(dvr_cur_addr.chip & dvr_cur_addr.bank & dvr_cur_addr.row(g_ddr.a_w-1 DOWNTO 0) & dvr_cur_addr.column(g_ddr.a_col_w -1 DOWNTO c_ddr3_ctlr_rsl_w),32);
-  ctlr_tech_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0) <= ctlr_wr_sosi.data(c_ctlr_data_w-1 DOWNTO 0);
+  ctlr_tech_mosi.address    <= RESIZE_MEM_CTLR_ADDRESS(dvr_cur_addr.chip & dvr_cur_addr.bank & dvr_cur_addr.row(g_ddr.a_w-1 DOWNTO 0) & dvr_cur_addr.column(g_ddr.a_col_w -1 DOWNTO c_ddr3_ctlr_rsl_w));
+  ctlr_tech_mosi.wrdata     <= RESIZE_MEM_CTLR_DATA(ctlr_wr_sosi.data);
   ctlr_tech_mosi.rd         <= ctlr_rd_req;
   ctlr_tech_mosi.wr         <= ctlr_wr_req;
-  ctlr_tech_mosi.burstsize  <= RESIZE_UVEC(ctlr_burst_size,32);
-
-  i_ctlr_rdy                                  <= ctlr_tech_miso.waitrequest_n;
-  ctlr_rd_sosi.valid                          <= ctlr_tech_miso.rdval;
-  ctlr_rd_sosi.data(c_ctlr_data_w-1 DOWNTO 0) <= ctlr_tech_miso.rddata(c_ctlr_data_w-1 DOWNTO 0);
-  i_ctlr_init_done                            <= ctlr_tech_miso.done;
-  local_cal_success                           <= ctlr_tech_miso.cal_ok;
-  local_cal_fail                              <= ctlr_tech_miso.cal_fail;
-
-
-
-
+  ctlr_tech_mosi.burstsize  <= RESIZE_MEM_CTLR_BURSTSIZE(ctlr_burst_size);
+
+  i_ctlr_rdy          <= ctlr_tech_miso.waitrequest_n;
+  ctlr_rd_sosi.valid  <= ctlr_tech_miso.rdval;
+  ctlr_rd_sosi.data   <= RESIZE_DP_DATA(ctlr_tech_miso.rddata);
+  i_ctlr_init_done    <= ctlr_tech_miso.done;
+  local_cal_success   <= ctlr_tech_miso.cal_ok;
+  local_cal_fail      <= ctlr_tech_miso.cal_fail;
 
 
   u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr