diff --git a/libraries/technology/ip_arria10/ddio/README.txt b/libraries/technology/ip_arria10/ddio/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..a491b7893b3a74cdf8258b26e29bceb58e6ebba4
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/README.txt
@@ -0,0 +1,73 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+
+Contents:
+
+1) DDIO components
+2) Arria10 IP
+3) Synthesis trials
+4) Issues
+
+
+1) DDIO components:
+ ip_arria10_ddio_in.vhd = Double Date Rate input
+ ip_arria10_ddio_out.vhd = Double Date Rate output
+
+
+2) Arria10 IP
+
+ The StratixIV IP uses altddio_in and altddio_out. First a Megawizard file for this StratixIV IP was made using the settings that
+ were used in common_ddio_in.vhd and common_ddio_out.vhd. This Megawizard IP file was then opened in Quartus to be able to let
+ Quartus 14 convert them using the altera_gpio component for Arria10.
+
+ The altera_gpio component is not part of the default Quartus 14.0a10 tool libraries, but instead it is created by Qsys together
+ with the IP. This makes that the altera_gpio can not easily be used in simulation and synthesis like was possible with altera_mf
+ in for Stratix IV (Quartus 11.1).
+
+ The ddio_in component is used by the PPSH and the ddio_out component is used by the ADUH. In both cases the g_width=1.
+ The Arria10 IP can be generated using a fixed width of 1. Therefore the width was set to 1 in the conversion from MegaWizard
+ to Qsys and the qsys files are stored as:
+
+ ip_arria10_ddio_in_1.qsys
+ ip_arria10_ddio_out_1.qsys
+
+ If the application would need a wider port then it can achieve this by instantiating the IP multiple times. This approach
+ avoids having to generate DDIO IP for every possible width. An alternative would be:
+ - to generate IP for e.g. width=16 and assuming that that is sufficient for all applications. Any application that uses less
+ width then leaves these IO unconnected so that the unused IO will get optimized away by synthesis.
+ - create the IP when it is needed, this scheme is more difficult to manage but is something to consider for the future.
+
+ The IP needs to be generated with:
+
+ ./generate_ip.sh
+
+ to create the simulation and synthesis files, because these are initially not kept in SVN.
+
+
+3) Synthesis trials
+
+ The Quartus project:
+
+ quartus/ddio.qpf
+
+ was used to verify that the DDIO IP actually synthesise to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
+
+
+4) Issues
+
+a) Simulation model does not work
+
+ The simulation model for the DDIO does not compile ok because a din port is missing in the ddio_out en a dout port is
+ missing in the ddio_in. Adding this ports manualy does work for compile, but when the component is loaded as a simulation
+ then Modelsim reports some internal error on the IP. The compile also does not work when using 'do msim_setup.tcl', so
+ there is something wrong with the DDIO simulation model. The synthesis of the DDIO IP using ddio.qpf does work.
+
+ The work around is not not use the simulation model, but instead use a behavioral simulation model for the IP:
+ sim/ip_arria10_ddio_in_1.vhd
+ sim/ip_arria10_ddio_out_1.vhd
+ sim/tb_ip_arria10_ddio_1.vhd = self checking tb for ip_arria10_ddio_in_1 -> ip_arria10_ddio_out_1
+
+ The selection between the IP model or the behavioral model is made in the compile_ip.tcl script.
+
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8823e755b41e3679413954f64d315470dabfc14c
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -0,0 +1,58 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+set IPMODEL "SIM";
+#set IPMODEL "PHY";
+
+if {$IPMODEL=="PHY"} {
+
+ # This file is based on Qsys-generated file msim_setup.tcl.
+ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/generated/"
+
+ vlib ./work/
+ vmap ip_arria10_ddio_in_1_altera_gpio_core_140 ./work/
+ vmap ip_arria10_ddio_out_1_altera_gpio_core_140 ./work/
+ vmap ip_arria10_ddio_in_1_altera_gpio_140 ./work/
+ vmap ip_arria10_ddio_out_1_altera_gpio_140 ./work/
+
+ # Quartus QIP uses the libraries, so map these here to work/ to be able to use these libraries also in simulation.
+ # However by instantiating the compenents as components instead of as entities it is not necessary to know the
+ # library in simiulation. Therefor these lines can be commented:
+ #vmap ip_arria10_ddio_in_1 ./work/
+ #vmap ip_arria10_ddio_out_1 ./work/
+
+ vlog -sv "$IP_DIR/altera_gpio_core_140/sim/mentor/altera_gpio.sv" -work work
+ vcom "$IP_DIR/altera_gpio_140/sim/ip_arria10_ddio_in_1_altera_gpio_140_dtqjxiy.vhd" -work work
+ vcom "$IP_DIR/altera_gpio_140/sim/ip_arria10_ddio_out_1_altera_gpio_140_awilcdy.vhd" -work work
+ vcom "$IP_DIR/sim/ip_arria10_ddio_in_1.vhd"
+ vcom "$IP_DIR/sim/ip_arria10_ddio_out_1.vhd"
+
+} else {
+
+ # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
+ set SIM_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/ddio/sim/"
+
+ vcom "$SIM_DIR/ip_arria10_ddio_in_1.vhd"
+ vcom "$SIM_DIR/ip_arria10_ddio_out_1.vhd"
+ vcom "$SIM_DIR/tb_ip_arria10_ddio_1.vhd"
+
+}
diff --git a/libraries/technology/ip_arria10/ddio/generate_ip.sh b/libraries/technology/ip_arria10/ddio/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..0f136b9599ba9a82d8a5fd69e63c7ccae36569d8
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/generate_ip.sh
@@ -0,0 +1,43 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Remark:
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+qsys-generate ip_arria10_ddio_in_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_ddio_out_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..43ba3ad6d30ac7fa8f4bb1b09dce6c23ae84695c
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_ddio
+hdl_library_clause_name = ip_arria10_ddio_lib
+hdl_lib_uses = technology
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+
+synth_files =
+ ip_arria10_ddio_in.vhd
+ ip_arria10_ddio_out.vhd
+
+test_bench_files =
+
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
+
+quartus_qip_files =
+ ddio/generated/ip_arria10_ddio_in_1.qip
+ ddio/generated/ip_arria10_ddio_out_1.qip
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
index 6ac22e3fd1e49894f038cb478768175d394a2d8c..ab3fb6fe9c88735747ecf790b43097a180bb5ece 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
@@ -1,112 +1,69 @@
--- megafunction wizard: %ALTDDIO_IN%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: ALTDDIO_IN
-
--- ============================================================
--- File Name: ip_arria10_ddio_in.vhd
--- Megafunction Name(s):
--- ALTDDIO_IN
+-------------------------------------------------------------------------------
--
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2011 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Wrapper for ip_arria10_ddio_in_1 to support g_width >= 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
ENTITY ip_arria10_ddio_in IS
- PORT
- (
- aclr : IN STD_LOGIC ;
- datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- inclock : IN STD_LOGIC ;
- dataout_h : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- dataout_l : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
- );
+ GENERIC (
+ g_width : NATURAL := 1
+ );
+ PORT (
+ in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ rst : IN STD_LOGIC := '0';
+ out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
END ip_arria10_ddio_in;
-ARCHITECTURE SYN OF ip_arria10_ddio_in IS
-
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
- SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
+ARCHITECTURE str OF ip_arria10_ddio_in IS
+ component ip_arria10_ddio_in_1 is
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
+ inclock : in std_logic := '0'; -- ck.export
+ aclr : in std_logic := '0'; -- aclr.export
+ dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
+ dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
+ );
+ end component;
+
BEGIN
- dataout_h <= sub_wire0(7 DOWNTO 0);
- dataout_l <= sub_wire1(7 DOWNTO 0);
-
- ALTDDIO_IN_component : ALTDDIO_IN
- GENERIC MAP (
- intended_device_family => "Stratix IV",
- invert_input_clocks => "OFF",
- lpm_hint => "UNUSED",
- lpm_type => "altddio_in",
- power_up_high => "OFF",
- width => 8
- )
- PORT MAP (
- aclr => aclr,
- datain => datain,
- inclock => inclock,
- dataout_h => sub_wire0,
- dataout_l => sub_wire1
- );
-
-
-
-END SYN;
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
--- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
--- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
--- Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
--- Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL "dataout_h[7..0]"
--- Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0
--- Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL "dataout_l[7..0]"
--- Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0
--- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
--- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_in.vhd TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_in.qip TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_in.bsf TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_in_inst.vhd TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_in.inc TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_in.cmp TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_in.ppf TRUE FALSE
--- Retrieval info: LIB_FILE: altera_mf
+ gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
+
+ u_ip_arria10_ddio_in_1 : ip_arria10_ddio_in_1
+ PORT MAP (
+ datain => in_dat(I DOWNTO I),
+ inclock => in_clk,
+ aclr => rst,
+ dataout_h => out_dat_hi(I DOWNTO I),
+ dataout_l => out_dat_lo(I DOWNTO I)
+ );
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..58e7e3a5de8e40caf7f5bc730b9a2b8879b36bfa
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in_1.qsys
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element ip_arria10_ddio_in_1
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="din" internal="ip_arria10_ddio_in_1.din" />
+ <interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
+ <interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
+ <interface
+ name="pad_in"
+ internal="ip_arria10_ddio_in_1.pad_in"
+ type="conduit"
+ dir="end">
+ <port name="datain" internal="datain" />
+ </interface>
+ <interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
+ <port name="inclock" internal="inclock" />
+ </interface>
+ <interface
+ name="aclr"
+ internal="ip_arria10_ddio_in_1.aclr"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="dataout_h"
+ internal="ip_arria10_ddio_in_1.dataout_h"
+ type="conduit"
+ dir="end">
+ <port name="dataout_h" internal="dataout_h" />
+ </interface>
+ <interface
+ name="dataout_l"
+ internal="ip_arria10_ddio_in_1.dataout_l"
+ type="conduit"
+ dir="end">
+ <port name="dataout_l" internal="dataout_l" />
+ </interface>
+ <module
+ kind="altera_gpio"
+ version="14.0"
+ enabled="1"
+ name="ip_arria10_ddio_in_1"
+ autoexport="1">
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="PIN_TYPE_GUI" value="Input" />
+ <parameter name="SIZE" value="1" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_diff_buff" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_use_oe" value="false" />
+ <parameter name="gui_enable_termination_ports" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_separate_io_clks" value="false" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
+ <parameter name="AUTO_DEVICE" value="Unknown" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
index 833742e20883584d441763bbf787ee3928190cfc..f91ec989cbc9a092a8d22dca52c6577b838bbe11 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
@@ -1,114 +1,67 @@
--- megafunction wizard: %ALTDDIO_OUT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: ALTDDIO_OUT
-
--- ============================================================
--- File Name: ip_arria10_ddio_out.vhd
--- Megafunction Name(s):
--- ALTDDIO_OUT
+-------------------------------------------------------------------------------
--
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2011 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Wrapper for ip_arria10_ddio_out_1 to support g_width >= 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
ENTITY ip_arria10_ddio_out IS
- PORT
- (
- aclr : IN STD_LOGIC ;
- datain_h : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- datain_l : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- outclock : IN STD_LOGIC ;
- dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
- );
+ GENERIC(
+ g_width : NATURAL := 1
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
END ip_arria10_ddio_out;
-ARCHITECTURE SYN OF ip_arria10_ddio_out IS
-
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
-
+ARCHITECTURE str OF ip_arria10_ddio_out IS
+
+ component ip_arria10_ddio_out_1 is
+ port (
+ dataout : out std_logic_vector(0 downto 0); -- pad_out.export
+ outclock : in std_logic := '0'; -- ck.export
+ aclr : in std_logic := '0'; -- aclr.export
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0'); -- datain_h.fragment
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
+ );
+ end component;
+
BEGIN
- dataout <= sub_wire0(7 DOWNTO 0);
-
- ALTDDIO_OUT_component : ALTDDIO_OUT
- GENERIC MAP (
- extend_oe_disable => "OFF",
- intended_device_family => "Stratix IV",
- invert_output => "OFF",
- lpm_hint => "UNUSED",
- lpm_type => "altddio_out",
- oe_reg => "UNREGISTERED",
- power_up_high => "OFF",
- width => 8
- )
- PORT MAP (
- aclr => aclr,
- datain_h => datain_h,
- datain_l => datain_l,
- outclock => outclock,
- dataout => sub_wire0
- );
-
-
-
-END SYN;
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
--- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
--- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
--- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
--- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL "datain_h[7..0]"
--- Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0
--- Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL "datain_l[7..0]"
--- Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0
--- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
--- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
--- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_out.vhd TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_out.qip TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_out.bsf TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_out_inst.vhd TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_out.inc TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_out.cmp TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ddio_out.ppf TRUE FALSE
--- Retrieval info: LIB_FILE: altera_mf
+ gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
+ u_ip_arria10_ddio_out_1 : ip_arria10_ddio_out_1
+ PORT MAP (
+ dataout => out_dat(I DOWNTO I),
+ outclock => in_clk,
+ aclr => rst,
+ datain_h => in_dat_hi(I DOWNTO I),
+ datain_l => in_dat_lo(I DOWNTO I)
+ );
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..f06b7fff7875ee9ff5584500535d64f58f25c0c8
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out_1.qsys
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element ip_arria10_ddio_out_1
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="Unknown" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="Unknown" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="din" internal="ip_arria10_ddio_out_1.din" />
+ <interface
+ name="pad_out"
+ internal="ip_arria10_ddio_out_1.pad_out"
+ type="conduit"
+ dir="end">
+ <port name="dataout" internal="dataout" />
+ </interface>
+ <interface name="ck" internal="ip_arria10_ddio_out_1.ck" type="conduit" dir="end">
+ <port name="outclock" internal="outclock" />
+ </interface>
+ <interface
+ name="aclr"
+ internal="ip_arria10_ddio_out_1.aclr"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="datain_h"
+ internal="ip_arria10_ddio_out_1.datain_h"
+ type="conduit"
+ dir="end">
+ <port name="datain_h" internal="datain_h" />
+ </interface>
+ <interface
+ name="datain_l"
+ internal="ip_arria10_ddio_out_1.datain_l"
+ type="conduit"
+ dir="end">
+ <port name="datain_l" internal="datain_l" />
+ </interface>
+ <module
+ kind="altera_gpio"
+ version="14.0"
+ enabled="1"
+ name="ip_arria10_ddio_out_1"
+ autoexport="1">
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="PIN_TYPE_GUI" value="Output" />
+ <parameter name="SIZE" value="1" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_diff_buff" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_use_oe" value="false" />
+ <parameter name="gui_enable_termination_ports" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_separate_io_clks" value="false" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
+ <parameter name="AUTO_DEVICE" value="Unknown" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>
diff --git a/libraries/technology/ip_arria10/ddio/quartus/ddio.qpf b/libraries/technology/ip_arria10/ddio/quartus/ddio.qpf
new file mode 100644
index 0000000000000000000000000000000000000000..6dd723a28a67be8432bb37f216cb923a90bfd9e2
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/quartus/ddio.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0a10.1 Build 374 09/02/2014 SJ Full Version
+# Date created = 18:00:35 October 24, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "18:00:35 October 24, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "ddio"
diff --git a/libraries/technology/ip_arria10/ddio/quartus/ddio.qsf b/libraries/technology/ip_arria10/ddio/quartus/ddio.qsf
new file mode 100644
index 0000000000000000000000000000000000000000..10a63e2560ca9cc66b94a05b3cac83ff2a81edc9
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/quartus/ddio.qsf
@@ -0,0 +1,59 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0a10.1 Build 374 09/02/2014 SJ Full Version
+# Date created = 18:00:35 October 24, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ddio_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Arria 10"
+set_global_assignment -name DEVICE 10AX115R2F40I2LG
+set_global_assignment -name TOP_LEVEL_ENTITY ip_arria10_ddio_out
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:00:35 OCTOBER 24, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name VHDL_FILE ../ip_arria10_ddio_in.vhd
+set_global_assignment -name VHDL_FILE ../ip_arria10_ddio_out.vhd
+set_global_assignment -name QIP_FILE ../generated/ip_arria10_ddio_out_1.qip
+set_global_assignment -name QIP_FILE ../generated/ip_arria10_ddio_in_1.qip
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..193d1fba05139d627ab5148ec477be56c757b8d1
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
@@ -0,0 +1,65 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Simulation model for DDIO in
+-- Description:
+-- The double data rate datain samples that arrive at time series t0, t1, t2,
+-- ... get output with samples t0, t2, ... in dataout_l and samples t1, t3,
+-- ... in dataout_h. Hence dataout = dataout_h & dataout_l contains the
+-- time series samples in little endian format with the first sample in the
+-- LSpart as shown in the timing diagram:
+-- _ _ _ _
+-- inclock | |_| |_| |_| |_
+-- datain 0 1 2 3 4 5 6 7
+-- in_dat_r 1 3 5
+-- in_dat_f 0 2 4
+-- dataout_h 1 3 5
+-- dataout_l 0 2 4
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY ip_arria10_ddio_in_1 IS
+ PORT (
+ datain : IN STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
+ inclock : IN STD_LOGIC := '0';
+ aclr : IN STD_LOGIC := '0';
+ dataout_h : OUT STD_LOGIC_VECTOR(0 downto 0);
+ dataout_l : OUT STD_LOGIC_VECTOR(0 downto 0)
+ );
+END ip_arria10_ddio_in_1;
+
+
+ARCHITECTURE beh OF ip_arria10_ddio_in_1 IS
+
+ SIGNAL in_dat_r : STD_LOGIC;
+ SIGNAL in_dat_f : STD_LOGIC;
+
+BEGIN
+
+ in_dat_r <= datain(0) WHEN rising_edge(inclock);
+ in_dat_f <= datain(0) WHEN falling_edge(inclock);
+
+ dataout_h <= (OTHERS=>in_dat_r);
+ dataout_l <= (OTHERS=>in_dat_f) WHEN rising_edge(inclock);
+
+END beh;
diff --git a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d9eaea024387d6070ae78bc791fc1ff481a5849f
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
@@ -0,0 +1,59 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Simulation model for DDIO out
+-- Description:
+-- This function is the inverse of DDIO in as described in ip_arria10_ddio_in_1.
+-- The timing diagram:
+-- _ _ _ _ _
+-- outclock | |_| |_| |_| |_| |_
+-- datain_h 1 3 5
+-- datain_l 0 2 4
+-- dataout @ r 1 3 5
+-- dataout @ f 0 2 4
+-- dataout 0 1 2 3 4 5 6 7
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY ip_arria10_ddio_out_1 IS
+ PORT (
+ dataout : OUT STD_LOGIC_VECTOR(0 downto 0);
+ outclock : IN STD_LOGIC := '0';
+ aclr : IN STD_LOGIC := '0';
+ datain_h : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0');
+ datain_l : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0')
+ );
+END ip_arria10_ddio_out_1;
+
+
+ARCHITECTURE beh OF ip_arria10_ddio_out_1 IS
+
+ SIGNAL out_dat_r : STD_LOGIC;
+ SIGNAL out_dat_f : STD_LOGIC;
+
+BEGIN
+
+ dataout <= datain_l WHEN falling_edge(outclock) ELSE
+ datain_h WHEN rising_edge(outclock);
+
+END beh;
diff --git a/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..70dfc0c63a7b6a61994b74bca72f792ce3fa61e7
--- /dev/null
+++ b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for the DDIO in and out simulation models
+-- Description:
+-- _ _ _ _
+-- inclock | |_| |_| |_| |_
+-- datain 0 1 2 3 4 5 6 7
+-- data_h 1 3 5
+-- data_l 0 2 4
+-- dataout 0 1 2 3 4 5 6 7
+--
+-- Usage:
+-- The tb is self checking (p_verify) and self stopping (tb_end)
+--
+-- . Load the simulation by right mouse selecting the entity in library work
+-- > as 3
+-- > run -a
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY tb_ip_arria10_ddio_1 IS
+END tb_ip_arria10_ddio_1;
+
+
+ARCHITECTURE tb OF tb_ip_arria10_ddio_1 IS
+
+ CONSTANT c_clk_period : TIME := 10 ns;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL in_dat : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL data_h : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL data_l : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL out_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL out_dat : STD_LOGIC;
+ SIGNAL out_dat_exp : STD_LOGIC;
+
+BEGIN
+
+ tb_end <= '0', '1' AFTER 100*c_clk_period;
+
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+
+ p_in : PROCESS
+ BEGIN
+ -- 0
+ in_dat <= '0';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ -- 1
+ in_dat <= '0';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '1';
+ WAIT UNTIL rising_edge(clk);
+ -- 2
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ -- 3
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '1';
+ WAIT UNTIL rising_edge(clk);
+ -- 2
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ END PROCESS;
+
+ in_data(0) <= in_dat;
+
+ u_ddio_in : ENTITY work.ip_arria10_ddio_in_1
+ PORT MAP (
+ datain => in_data,
+ inclock => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
+
+ u_ddio_out : ENTITY work.ip_arria10_ddio_out_1
+ PORT MAP (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
+
+ out_dat <= out_data(0);
+
+ out_dat_exp <= TRANSPORT in_dat AFTER c_clk_period*1.5 + 1 ps;
+
+ p_verify : PROCESS(clk)
+ BEGIN
+ IF falling_edge(clk) THEN
+ ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_ddio_1: Error, unexpeced data at falling edge";
+ END IF;
+ IF rising_edge(clk) THEN
+ ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_ddio_1: Error, unexpeced data at rising edge";
+ END IF;
+ END PROCESS;
+
+END tb;