diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
index a66650e5b4234bb30714ecce9841d9be484905e4..68048b09ca51ee3bdd1be86fb24a382f38b0475d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
@@ -1,6 +1,6 @@
 hdl_lib_name = lofar2_unb2b_adc
 hdl_library_clause_name = lofar2_unb2b_adc_lib
-hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag tech_jesd 
+hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag tech_jesd204b
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e1sg
 
@@ -11,7 +11,7 @@ synth_files =
     src/vhdl/lofar2_unb2b_adc.vhd
     
 test_bench_files = 
-#    tb/vhdl/tb_lofar2_unb2b_adc.vhd
+    tb/vhdl/tb_lofar2_unb2b_adc.vhd
 
 
 [modelsim_project_file]
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..e0a8d1b58168ab6b944a51e297c8478e8c28fac5
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
@@ -0,0 +1 @@
+#Placeholder
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..da85c19f6523141cbbe5eb02ad1bd1dc0e4f2fdb
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
index ce325a8640b28889f50e934fefcf74aa69123c93..d38ba1fec4ab3b26e4cef80387cfd2f936d7c20e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -5,9 +5,14 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_arria10_e1sg
                      
  synth_files =
+    ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+    ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
+    ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
+    ../../src/vhdl/lofar2_unb2b_adc.vhd
     lofar2_unb2b_adc_full.vhd
 
 test_bench_files = 
+    tb_lofar2_unb2b_adc_full.vhd
 
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index bc8c1b2659eb059828ddea1ef213dbdac28a72fc..90ae0d564ae296168051d9cf0337b3b476122fbf 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -85,7 +85,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc_full IS
 
 BEGIN
 
-  u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
+  u_revision : ENTITY work.lofar2_unb2b_adc
   GENERIC MAP (
     g_design_name => g_design_name,
     g_design_note => g_design_note,
@@ -123,10 +123,10 @@ BEGIN
     ETH_SGOUT    => ETH_SGOUT,
 
     -- LEDs
-    QSFP_LED     => QSFP_LED
+    QSFP_LED     => QSFP_LED,
 
     -- back transceivers
-    BCK_RX       => BCK_RX_INTERNAL,
+    BCK_RX       => BCK_RX,
     BCK_REF_CLK  => BCK_REF_CLK,
   
     -- jesd204b syncronization signals
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_adc_unb2b_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_adc_unb2b_full.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0d7d95d1718b5b3b6ddd4ff389fbef3bce83dc85
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_adc_unb2b_full.vhd
@@ -0,0 +1,167 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2018
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Jonathan Hargreaves
+-- Purpose: Tb to show that lofar2_unb2b_adc_full can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_adc_full IS
+END tb_lofar2_unb2b_adc_full;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_adc_full IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL bck_rx              : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL bck_ref_clk         : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc_full : ENTITY work.lofar2_unb2b_adc_full
+  GENERIC MAP (
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    BCK_RX       => bck_rx,
+    BCK_REF_CLK  => bck_ref_clk,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC   => jesd204b_sync
+  );
+
+
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0d7d95d1718b5b3b6ddd4ff389fbef3bce83dc85
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -0,0 +1,167 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2018
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Jonathan Hargreaves
+-- Purpose: Tb to show that lofar2_unb2b_adc_full can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_adc_full IS
+END tb_lofar2_unb2b_adc_full;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_adc_full IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL bck_rx              : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL bck_ref_clk         : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc_full : ENTITY work.lofar2_unb2b_adc_full
+  GENERIC MAP (
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    BCK_RX       => bck_rx,
+    BCK_REF_CLK  => bck_ref_clk,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC   => jesd204b_sync
+  );
+
+
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
index dcd8780a7d0c17e763c318730cb1a481f4dddf0b..707fde2968d25fbf115fcb1f1a34d7245b2590f2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
@@ -5,10 +5,14 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_arria10_e1sg
                      
  synth_files =
+    ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+    ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
+    ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
+    ../../src/vhdl/lofar2_unb2b_adc.vhd
     lofar2_unb2b_adc_one_node.vhd
 
 test_bench_files = 
-
+    tb_lofar2_unb2b_adc_one_node.vhd
 
 
 [modelsim_project_file]
@@ -34,7 +38,7 @@ quartus_sdc_files =
 quartus_tcl_files =
     ../../quartus/lofar_unb2b_adc_pins.tcl
 
-quartus_vhdl_files = 
+quartus_vhdl_files =
 
 quartus_qip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar_unb2b_adc_one_node/qsys_lofar_unb2b_adc/qsys_lofar_unb2b_adc.qip
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index cab09b0a1b6ea73fe7d35ae4f9e326581b304004..f3f27d30c296711961cde2d042e8008148baa664 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -85,7 +85,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc_one_node IS
 
 BEGIN
 
-  u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
+  u_revision : ENTITY work.lofar2_unb2b_adc
   GENERIC MAP (
     g_design_name => g_design_name,
     g_design_note => g_design_note,
@@ -123,10 +123,10 @@ BEGIN
     ETH_SGOUT    => ETH_SGOUT,
 
     -- LEDs
-    QSFP_LED     => QSFP_LED
+    QSFP_LED     => QSFP_LED,
 
     -- back transceivers
-    BCK_RX       => BCK_RX_INTERNAL,
+    BCK_RX       => BCK_RX,
     BCK_REF_CLK  => BCK_REF_CLK,
   
     -- jesd204b syncronization signals
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..03102523a4f927f9a723dc282bd60d425e59c157
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -0,0 +1,167 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2018
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Jonathan Hargreaves
+-- Purpose: Tb to show that lofar2_unb2b_adc_one_node can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_adc_one_node IS
+END tb_lofar2_unb2b_adc_one_node;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_adc_one_node IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL bck_rx              : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL bck_ref_clk         : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc_one_node : ENTITY work.lofar2_unb2b_adc_one_node
+  GENERIC MAP (
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    BCK_RX       => bck_rx,
+    BCK_REF_CLK  => bck_ref_clk,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC   => jesd204b_sync
+  );
+
+
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index d7abb42f889e48e217abf26f9e563291771cf8b4..c76f0c9a933305a65da4d5efc905b888f923ca46 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -27,8 +27,10 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE work.lofar2_unb2b_adc_pkg.ALL;
 
 ENTITY lofar2_unb2b_adc IS
   GENERIC (
@@ -41,8 +43,8 @@ ENTITY lofar2_unb2b_adc IS
     g_sim_model_ddr    : BOOLEAN := FALSE;
     g_stamp_date       : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
-    g_revision_id      : STRING  := ""   -- revision ID     -- set by QSF
-    g_factory_image    : BOOLEAN := FALSE
+    g_revision_id      : STRING  := "";  -- revision ID     -- set by QSF
+    g_factory_image    : BOOLEAN := FALSE;
     g_protect_addr_range: BOOLEAN := FALSE
   );
   PORT (
@@ -89,9 +91,9 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
 
   -- Revision parameters
   CONSTANT c_revision_select        : t_lofar2_unb2b_adc_config := func_sel_revision_rec(g_design_name);
-  CONSTANT c_nof_streams_jesd204b   : NATURAL := c_revision_select.nof_streams_jesd204b;
-  CONSTANT c_nof_streams_db         : NATURAL := c_revision_select.nof_streams_db;
-  CONSTANT c_nof_streams_input      : NATURAL := c_revision_select.nof_streams_input;
+  CONSTANT c_nof_streams_jesd204b   : NATURAL := c_revision_select.nof_streams_jesd204b; -- IP is set up for 12 streams
+  CONSTANT c_nof_streams_db         : NATURAL := c_revision_select.nof_streams_db;       -- Streams of raw samples to record in db
+  CONSTANT c_nof_streams_input      : NATURAL := c_revision_select.nof_streams_input;    -- Streams actually passed through for processing
 
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
@@ -102,10 +104,16 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   CONSTANT c_wg_buf_directory       : STRING := "data/";
   CONSTANT c_wg_buf_dat_w           : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
   CONSTANT c_wg_buf_addr_w          : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
-  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(0 TO c_nof_streams_input-1);    
-  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(0 TO c_nof_streams_input-1);         
-  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(0 TO c_nof_streams_input-1);
+  SIGNAL wg_out_ovr                 : STD_LOGIC_VECTOR(c_nof_streams_input-1 DOWNTO 0);    
+  SIGNAL wg_out_val                 : STD_LOGIC_VECTOR(c_nof_streams_input-1 DOWNTO 0);    
+  SIGNAL wg_out_data                : STD_LOGIC_VECTOR(c_nof_streams_input*c_wg_buf_dat_w-1 DOWNTO 0);    
+  SIGNAL wg_out_sync                : STD_LOGIC_VECTOR(c_nof_streams_input-1 DOWNTO 0);    
+  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(c_nof_streams_input-1 DOWNTO 0);    
+  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(c_nof_streams_input-1 DOWNTO 0);         
+  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(c_nof_streams_input-1 DOWNTO 0);
 
+  -- bsn monitor
+  SIGNAL bsn_sosi_arr               : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0) := (others => c_dp_sosi_rst);
 
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;
@@ -119,6 +127,9 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   SIGNAL st_clk                     : STD_LOGIC;
   SIGNAL st_pps                     : STD_LOGIC;
 
+  SIGNAL dp_rst                     : STD_LOGIC;
+  SIGNAL dp_clk                     : STD_LOGIC;
+
   -- PIOs
   SIGNAL pout_wdi                   : STD_LOGIC;
 
@@ -184,6 +195,16 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   SIGNAL jesd204b_mosi              : t_mem_mosi;
   SIGNAL jesd204b_miso              : t_mem_miso;
 
+  -- WG
+  SIGNAL reg_wg_mosi_arr            : t_mem_mosi_arr(c_nof_streams_input-1 DOWNTO 0);
+  SIGNAL reg_wg_miso_arr            : t_mem_miso_arr(c_nof_streams_input-1 DOWNTO 0);
+  SIGNAL ram_wg_mosi_arr            : t_mem_mosi_arr(c_nof_streams_input-1 DOWNTO 0);
+  SIGNAL ram_wg_miso_arr            : t_mem_miso_arr(c_nof_streams_input-1 DOWNTO 0);
+
+  -- BSN MONITOR
+  SIGNAL reg_bsn_monitor_mosi       : t_mem_mosi;
+  SIGNAL reg_bsn_monitor_miso       : t_mem_miso;
+
   -- QSFP leds
   SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
   SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -197,6 +218,15 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   SIGNAL jesd204b_rx_src_out_arr        : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
   SIGNAL jesd204b_frame_clk             : STD_LOGIC;
 
+  -------------------------------------------------------------------------------
+  -- DP sync checker / insert
+  -------------------------------------------------------------------------------
+  CONSTANT c_nof_clk_per_blk         : NATURAL := 1024;
+  CONSTANT c_nof_blk_per_sync        : NATURAL := 800000;
+  CONSTANT c_nof_clk_per_sync        : NATURAL := c_nof_blk_per_sync * 256;  -- = 800000 * 256
+  CONSTANT c_bsn_sync_timeout        : NATURAL := (c_nof_clk_per_sync * 10)/8; -- *10/8 as margin
+
+
 
 BEGIN
 
@@ -325,7 +355,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- MM master
   -----------------------------------------------------------------------------
-  u_mmm : ENTITY work.mmm_unb2b_jesd_simple
+  u_mmm : ENTITY work.mmm_lofar2_unb2b_adc
   GENERIC MAP (
     g_sim         => g_sim,
     g_sim_unb_nr  => g_sim_unb_nr,
@@ -510,12 +540,17 @@ BEGIN
       st_clk              => jesd204b_frame_clk,
       st_restart          => st_pps,
 
-      out_ovr             => wg_sosi_arr(I).err,
-      out_val             => wg_sosi_arr(I).valid,
-      out_dat             => wg_sosi_arr(I).data(c_wg_buf_dat_w-1 downto 0),
-      out_sync            => wg_sosi_arr(I).sync
+      out_ovr             => wg_out_ovr(I downto I),
+      out_val             => wg_out_val(I downto I),
+      out_dat             => wg_out_data((I+1)*c_wg_buf_dat_w-1 downto I*c_wg_buf_dat_w),
+      out_sync            => wg_out_sync(I downto I)
     );
 
+    wg_sosi_arr(I).err(0) <= wg_out_ovr(I);
+    wg_sosi_arr(I).valid <= wg_out_val(I);
+    wg_sosi_arr(I).data(c_wg_buf_dat_w-1 downto 0) <= wg_out_data((I+1)*c_wg_buf_dat_w-1 downto I*c_wg_buf_dat_w);
+    wg_sosi_arr(I).sync <= wg_out_sync(I);
+
   END GENERATE;
 
 
@@ -548,5 +583,35 @@ BEGIN
     END IF;
   END PROCESS;
 
-END str;
 
+  ---------------------------------------------------------------------------------------
+  -- BSN monitor (Block Checker)
+  ---------------------------------------------------------------------------------------
+  u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+  GENERIC MAP (
+    g_nof_streams        => c_nof_streams_jesd204b,
+    g_sync_timeout       => c_bsn_sync_timeout,
+    g_bsn_w              => 51, --c_apertif_bsn_w,
+    g_log_first_bsn      => FALSE
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+    reg_mosi    => reg_bsn_monitor_mosi,
+    reg_miso    => reg_bsn_monitor_miso,
+
+    -- Streaming clock domain
+    dp_rst      => dp_rst,
+    dp_clk      => dp_clk,
+    in_siso_arr => (OTHERS=>c_dp_siso_rdy),
+    in_sosi_arr => bsn_sosi_arr
+  );
+
+  -- only connect the channels actually used
+
+  gen_bsn_monitor_inputs : FOR I IN 0 TO c_nof_streams_input-1 GENERATE
+    bsn_sosi_arr(I) <= mux_sosi_arr(I);
+  END GENERATE;
+
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
index c85fc15e4e5398ebce75981102da6390c6d30ec0..fc8463eea473048d1e0e849e4cf13cc592863185 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE BODY lofar2_unb2b_adc_pkg IS
   FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_adc_config IS
   BEGIN
     IF    g_design_name = "lofar2_unb2b_adc_one_node"    THEN RETURN c_one_node;
-    IF    g_design_name = "lofar2_unb2b_adc_full"        THEN RETURN c_full;
+    ELSIF g_design_name = "lofar2_unb2b_adc_full"        THEN RETURN c_full;
     ELSE  RETURN c_one_node;
     END IF;
   END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index 19c2ae37d4818345b1106b08728024eee2201f1c..03e1e6bd65e9e5e3d2eba1e2c43ee68957a1797d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -19,49 +19,30 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, mm_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
-USE common_lib.tb_common_mem_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
-USE common_lib.common_network_total_header_pkg.ALL;
-USE common_lib.common_network_layers_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE mm_lib.mm_file_pkg.ALL;
 USE mm_lib.mm_file_unb_pkg.ALL;
-USE eth_lib.eth_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE tech_tse_lib.tech_tse_pkg.ALL;
-USE tech_tse_lib.tb_tech_tse_pkg.ALL;
-USE work.qsys_unb2b_test_pkg.ALL;
-USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
-USE work.unb2b_test_pkg.ALL;
-
+USE work.qsys_lofar2_unb2b_adc_pkg.ALL;
 
 
 ENTITY mmm_lofar2_unb2b_adc IS
   GENERIC (
-    g_sim               : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
-    g_sim_unb_nr        : NATURAL := 0;
-    g_sim_node_nr       : NATURAL := 0;
-    g_technology        : NATURAL := c_tech_arria10_e1sg;
-    g_bg_block_size     : NATURAL;
-    g_hdr_field_arr     : t_common_field_arr;
-    g_nof_streams_1GbE  : NATURAL;
-    g_nof_streams_qsfp  : NATURAL;
-    g_nof_streams_ring  : NATURAL;
-    g_nof_streams_back0 : NATURAL;
-    g_nof_streams_back1 : NATURAL
+    g_sim         : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
+    g_sim_unb_nr  : NATURAL := 0;
+    g_sim_node_nr : NATURAL := 0
   );
   PORT (
     mm_rst                   : IN  STD_LOGIC;
     mm_clk                   : IN  STD_LOGIC;
 
     pout_wdi                 : OUT STD_LOGIC;
-
+                             
     -- Manual WDI override
     reg_wdi_mosi             : OUT t_mem_mosi;
     reg_wdi_miso             : IN  t_mem_miso;
@@ -75,7 +56,7 @@ ENTITY mmm_lofar2_unb2b_adc IS
     -- UniBoard I2C sensors
     reg_unb_sens_mosi        : OUT t_mem_mosi; 
     reg_unb_sens_miso        : IN  t_mem_miso; 
-
+                             
     reg_fpga_temp_sens_mosi   : OUT t_mem_mosi;
     reg_fpga_temp_sens_miso   : IN  t_mem_miso;
     reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
@@ -88,25 +69,15 @@ ENTITY mmm_lofar2_unb2b_adc IS
     reg_ppsh_mosi            : OUT t_mem_mosi; 
     reg_ppsh_miso            : IN  t_mem_miso; 
                              
-    -- eth1g ch0
-    eth1g_eth0_mm_rst        : OUT STD_LOGIC;
-    eth1g_eth0_tse_mosi      : OUT t_mem_mosi;  
-    eth1g_eth0_tse_miso      : IN  t_mem_miso;  
-    eth1g_eth0_reg_mosi      : OUT t_mem_mosi;  
-    eth1g_eth0_reg_miso      : IN  t_mem_miso;  
-    eth1g_eth0_reg_interrupt : IN  STD_LOGIC; 
-    eth1g_eth0_ram_mosi      : OUT t_mem_mosi;  
-    eth1g_eth0_ram_miso      : IN  t_mem_miso;
-
-    -- eth1g ch1
-    eth1g_eth1_mm_rst        : OUT STD_LOGIC;
-    eth1g_eth1_tse_mosi      : OUT t_mem_mosi;  
-    eth1g_eth1_tse_miso      : IN  t_mem_miso;  
-    eth1g_eth1_reg_mosi      : OUT t_mem_mosi;  
-    eth1g_eth1_reg_miso      : IN  t_mem_miso;  
-    eth1g_eth1_reg_interrupt : IN  STD_LOGIC; 
-    eth1g_eth1_ram_mosi      : OUT t_mem_mosi;  
-    eth1g_eth1_ram_miso      : IN  t_mem_miso;
+    -- eth1g
+    eth1g_mm_rst             : OUT STD_LOGIC;
+    eth1g_tse_mosi           : OUT t_mem_mosi;  
+    eth1g_tse_miso           : IN  t_mem_miso;  
+    eth1g_reg_mosi           : OUT t_mem_mosi;  
+    eth1g_reg_miso           : IN  t_mem_miso;  
+    eth1g_reg_interrupt      : IN  STD_LOGIC; 
+    eth1g_ram_mosi           : OUT t_mem_mosi;  
+    eth1g_ram_miso           : IN  t_mem_miso;
 
     -- EPCS read
     reg_dpmm_data_mosi       : OUT t_mem_mosi;
@@ -128,186 +99,46 @@ ENTITY mmm_lofar2_unb2b_adc IS
     reg_remu_mosi            : OUT t_mem_mosi;
     reg_remu_miso            : IN  t_mem_miso;
 
-    -- block gen
-    ram_diag_bg_1GbE_mosi          : OUT t_mem_mosi;
-    ram_diag_bg_1GbE_miso          : IN  t_mem_miso;
-    reg_diag_bg_1GbE_mosi          : OUT t_mem_mosi;
-    reg_diag_bg_1GbE_miso          : IN  t_mem_miso;
-    reg_diag_tx_seq_1GbE_mosi      : OUT t_mem_mosi;
-    reg_diag_tx_seq_1GbE_miso      : IN  t_mem_miso;
-
-    ram_diag_bg_10GbE_mosi         : OUT t_mem_mosi;
-    ram_diag_bg_10GbE_miso         : IN  t_mem_miso;
-    reg_diag_bg_10GbE_mosi         : OUT t_mem_mosi;
-    reg_diag_bg_10GbE_miso         : IN  t_mem_miso;
-    reg_diag_tx_seq_10GbE_mosi     : OUT t_mem_mosi;
-    reg_diag_tx_seq_10GbE_miso     : IN  t_mem_miso;
-
-    -- dp_offload_tx
-    --reg_dp_offload_tx_1GbE_mosi          : OUT t_mem_mosi;
-    --reg_dp_offload_tx_1GbE_miso          : IN  t_mem_miso;
-    --reg_dp_offload_tx_1GbE_hdr_dat_mosi  : OUT t_mem_mosi;
-    --reg_dp_offload_tx_1GbE_hdr_dat_miso  : IN  t_mem_miso;
-
-    -- dp_offload_rx
-    --reg_dp_offload_rx_1GbE_hdr_dat_mosi  : OUT t_mem_mosi;
-    --reg_dp_offload_rx_1GbE_hdr_dat_miso  : IN  t_mem_miso;
-
-    -- bsn
-    reg_bsn_monitor_1GbE_mosi      : OUT t_mem_mosi;
-    reg_bsn_monitor_1GbE_miso      : IN  t_mem_miso;
-    reg_bsn_monitor_10GbE_mosi     : OUT t_mem_mosi;
-    reg_bsn_monitor_10GbE_miso     : IN  t_mem_miso;
-
-    -- databuffer
-    ram_diag_data_buf_1GbE_mosi    : OUT t_mem_mosi;
-    ram_diag_data_buf_1GbE_miso    : IN  t_mem_miso;
-    reg_diag_data_buf_1GbE_mosi    : OUT t_mem_mosi;
-    reg_diag_data_buf_1GbE_miso    : IN  t_mem_miso;
-    reg_diag_rx_seq_1GbE_mosi      : OUT t_mem_mosi;
-    reg_diag_rx_seq_1GbE_miso      : IN  t_mem_miso;
-
-    ram_diag_data_buf_10GbE_mosi   : OUT t_mem_mosi;
-    ram_diag_data_buf_10GbE_miso   : IN  t_mem_miso;
-    reg_diag_data_buf_10GbE_mosi   : OUT t_mem_mosi;
-    reg_diag_data_buf_10GbE_miso   : IN  t_mem_miso;
-    reg_diag_rx_seq_10GbE_mosi     : OUT t_mem_mosi;
-    reg_diag_rx_seq_10GbE_miso     : IN  t_mem_miso;
-
-    -- 10GbE
-    reg_10gbase_r_24_mosi : OUT t_mem_mosi;
-    reg_10gbase_r_24_miso : IN  t_mem_miso;
-    reg_tr_10GbE_qsfp_ring_mosi    : OUT t_mem_mosi;
-    reg_tr_10GbE_qsfp_ring_miso    : IN  t_mem_miso;
-    reg_tr_10GbE_back0_mosi        : OUT t_mem_mosi;
-    reg_tr_10GbE_back0_miso        : IN  t_mem_miso;
-    reg_tr_10GbE_back1_mosi        : OUT t_mem_mosi;
-    reg_tr_10GbE_back1_miso        : IN  t_mem_miso;
-
-    reg_eth10g_qsfp_ring_mosi      : OUT t_mem_mosi;
-    reg_eth10g_qsfp_ring_miso      : IN  t_mem_miso;
-    reg_eth10g_back0_mosi          : OUT t_mem_mosi;
-    reg_eth10g_back0_miso          : IN  t_mem_miso;
-    reg_eth10g_back1_mosi          : OUT t_mem_mosi;
-    reg_eth10g_back1_miso          : IN  t_mem_miso;
-
-    -- DDR4 : MB I
-    reg_io_ddr_MB_I_mosi                : OUT t_mem_mosi;
-    reg_io_ddr_MB_I_miso                : IN  t_mem_miso;
-    
-    reg_diag_tx_seq_ddr_MB_I_mosi       : OUT t_mem_mosi;
-    reg_diag_tx_seq_ddr_MB_I_miso       : IN  t_mem_miso;
-
-    reg_diag_rx_seq_ddr_MB_I_mosi       : OUT t_mem_mosi;
-    reg_diag_rx_seq_ddr_MB_I_miso       : IN  t_mem_miso;
-
-    reg_diag_data_buf_ddr_MB_I_mosi     : OUT t_mem_mosi;
-    reg_diag_data_buf_ddr_MB_I_miso     : IN  t_mem_miso;
-    ram_diag_data_buf_ddr_MB_I_mosi     : OUT t_mem_mosi;
-    ram_diag_data_buf_ddr_MB_I_miso     : IN  t_mem_miso;
-    
-    -- DDR4 : MB II
-    reg_io_ddr_MB_II_mosi                : OUT t_mem_mosi;
-    reg_io_ddr_MB_II_miso                : IN  t_mem_miso;
-    
-    reg_diag_tx_seq_ddr_MB_II_mosi       : OUT t_mem_mosi;
-    reg_diag_tx_seq_ddr_MB_II_miso       : IN  t_mem_miso;
-
-    reg_diag_rx_seq_ddr_MB_II_mosi       : OUT t_mem_mosi;
-    reg_diag_rx_seq_ddr_MB_II_miso       : IN  t_mem_miso;
-
-    reg_diag_data_buf_ddr_MB_II_mosi     : OUT t_mem_mosi;
-    reg_diag_data_buf_ddr_MB_II_miso     : IN  t_mem_miso;
-    ram_diag_data_buf_ddr_MB_II_mosi     : OUT t_mem_mosi;
-    ram_diag_data_buf_ddr_MB_II_miso     : IN  t_mem_miso
+    -- Jesd control
+    jesd204b_mosi            : OUT t_mem_mosi;
+    jesd204b_miso            : IN  t_mem_miso;
+
+    -- JESD databuffer
+    ram_diag_data_buf_jesd_mosi   : OUT t_mem_mosi;
+    ram_diag_data_buf_jesd_miso   : IN  t_mem_miso;
+    reg_diag_data_buf_jesd_mosi   : OUT t_mem_mosi;
+    reg_diag_data_buf_jesd_miso   : IN  t_mem_miso
   );
 END mmm_lofar2_unb2b_adc;
 
-
-ARCHITECTURE str OF mmm_unb2b_test IS
+ARCHITECTURE str OF mmm_lofar2_unb2b_adc IS
 
   CONSTANT c_sim_node_nr   : NATURAL := g_sim_node_nr;
   CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
 
-  CONSTANT g_nof_streams_10GbE                     : NATURAL := g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back0 + g_nof_streams_back1;
-
-  -- Block generator
-  -- check with python: from common import *
-  --                    ceil_log2(48 * 2**ceil_log2(900))
-  CONSTANT c_ram_diag_bg_1GbE_addr_w               : NATURAL := ceil_log2(g_nof_streams_1GbE  * pow2(ceil_log2(g_bg_block_size)));
-  CONSTANT c_ram_diag_bg_10GbE_addr_w              : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
-  CONSTANT c_ram_diag_databuffer_10GbE_addr_w      : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
-  CONSTANT c_ram_diag_databuffer_1GbE_addr_w       : NATURAL := ceil_log2(g_nof_streams_1GbE  * pow2(ceil_log2(g_bg_block_size)));
-  CONSTANT c_ram_diag_databuffer_ddr_addr_w        : NATURAL := ceil_log2(2                   * pow2(ceil_log2(g_bg_block_size)));
-
-  -- dp_offload
---  CONSTANT c_reg_dp_offload_tx_adr_w                     : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
---  CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w          : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
---  CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words    : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
---  CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w        : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
---  CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w  : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
---  CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words    : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
---  CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w        : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
---  CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w  : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-
-  -- tr_10GbE
-  CONSTANT c_reg_tr_10GbE_adr_w                    : NATURAL := func_tech_mac_10g_csr_addr_w(g_technology);
-  CONSTANT c_reg_tr_10GbE_qsfp_ring_multi_adr_w    : NATURAL := ceil_log2((g_nof_streams_qsfp+g_nof_streams_ring) * pow2(c_reg_tr_10GbE_adr_w));
-  CONSTANT c_reg_tr_10GbE_back0_multi_adr_w        : NATURAL := ceil_log2(g_nof_streams_back0 * pow2(c_reg_tr_10GbE_adr_w));
-  CONSTANT c_reg_tr_10GbE_back1_multi_adr_w        : NATURAL := ceil_log2(g_nof_streams_back1 * pow2(c_reg_tr_10GbE_adr_w));
-
-  -- reg_eth10g
-  CONSTANT c_reg_eth10g_adr_w                      : NATURAL := 1;
-  CONSTANT c_reg_eth10g_qsfp_ring_multi_adr_w      : NATURAL := ceil_log2((g_nof_streams_qsfp+g_nof_streams_ring) * pow2(c_reg_eth10g_adr_w));
-  CONSTANT c_reg_eth10g_back0_multi_adr_w          : NATURAL := ceil_log2(g_nof_streams_back0 * pow2(c_reg_eth10g_adr_w));
-  CONSTANT c_reg_eth10g_back1_multi_adr_w          : NATURAL := ceil_log2(g_nof_streams_back1 * pow2(c_reg_eth10g_adr_w));
-
-  -- BSN monitors
-  CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w        : NATURAL := ceil_log2(g_nof_streams_1GbE  * pow2(c_unb2b_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-  CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w       : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb2b_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
-
-  -- Simulation
-  CONSTANT c_sim_eth_src_mac                       : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
-  CONSTANT c_sim_eth_control_rx_en                 : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
-
-  SIGNAL sim_eth_mm_bus_switch                     : STD_LOGIC;
-  SIGNAL sim_eth_psc_access                        : STD_LOGIC;
-
-  SIGNAL i_eth1g_eth0_reg_mosi                     : t_mem_mosi;
-  SIGNAL i_eth1g_eth0_reg_miso                     : t_mem_miso;
-  SIGNAL i_eth1g_eth1_reg_mosi                     : t_mem_mosi;
-  SIGNAL i_eth1g_eth1_reg_miso                     : t_mem_miso;
-
-  SIGNAL sim_eth1g_eth0_reg_mosi                   : t_mem_mosi;
-  SIGNAL sim_eth1g_eth1_reg_mosi                   : t_mem_mosi;
-  SIGNAL i_reset_n                                 : STD_LOGIC;
+  SIGNAL i_reset_n         : STD_LOGIC;
 
 BEGIN
 
   ----------------------------------------------------------------------------
-  -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
+  -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
   ----------------------------------------------------------------------------
   gen_mm_file_io : IF g_sim = TRUE GENERATE
 
-    eth1g_eth0_mm_rst <= mm_rst;
-    eth1g_eth1_mm_rst <= mm_rst;
-
-    u_mm_file_reg_unb_system_info   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
-                                                 PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+    u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+                                               PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
 
-    u_mm_file_rom_unb_system_info   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
-                                                 PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+    u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+                                               PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
 
-    u_mm_file_reg_wdi               : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
-                                                 PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+    u_mm_file_reg_wdi             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+                                               PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
 
-    u_mm_file_reg_unb_sens          : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
-                                                 PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+    u_mm_file_reg_unb_sens        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+                                               PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
 
-    u_mm_file_reg_unb_pmbus         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
-                                                 PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+    u_mm_file_reg_unb_pmbus       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+                                               PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
 
     u_mm_file_reg_fpga_temp_sens  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
                                                PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
@@ -315,136 +146,22 @@ BEGIN
     u_mm_file_reg_fpga_voltage_sens :  mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
                                                PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
 
-    u_mm_file_reg_ppsh              : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
-                                                 PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-
-    u_mm_file_reg_diag_bg_1GbE      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
-                                                 PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
-    u_mm_file_ram_diag_bg_1GbE      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
-                                                 PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
-    u_mm_file_reg_diag_tx_seq_1GbE  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
-                                                 PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
-
-    u_mm_file_reg_diag_bg_10GbE     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
-                                                 PORT MAP(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
-    u_mm_file_ram_diag_bg_10GbE     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
-                                                 PORT MAP(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
-    u_mm_file_reg_diag_tx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
-                                                 PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
---    u_mm_file_reg_dp_offload_tx_1GbE  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
---                                                   PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
---    u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
---                                                           PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
---    u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
---                                                           PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
-    u_mm_file_reg_bsn_monitor_1GbE       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
-                                                      PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
-    u_mm_file_reg_bsn_monitor_10GbE      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
-                                                      PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
-    u_mm_file_reg_diag_data_buffer_1GbE  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
-                                                      PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
-    u_mm_file_ram_diag_data_buffer_1GbE  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
-                                                      PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
-    u_mm_file_reg_diag_rx_seq_1GbE       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
-                                                      PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
-    u_mm_file_reg_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
-                                                      PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
-    u_mm_file_ram_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
-                                                      PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
-    u_mm_file_reg_diag_rx_seq_10GbE      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
-                                                      PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
-    u_mm_file_reg_io_ddr_MB_I                 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
-                                                           PORT MAP(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
-    u_mm_file_reg_diag_tx_seq_ddr_MB_I        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
-                                                           PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
-    u_mm_file_reg_diag_rx_seq_ddr_MB_I        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
-                                                           PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
-    u_mm_file_reg_diag_data_buffer_ddr_MB_I   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
-                                                           PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
-    u_mm_file_ram_diag_data_buffer_ddr_MB_I   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
-                                                           PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
-    u_mm_file_reg_io_ddr_MB_II                : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
-                                                           PORT MAP(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
-    u_mm_file_reg_diag_tx_seq_ddr_MB_II       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
-                                                           PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
-    u_mm_file_reg_diag_rx_seq_ddr_MB_II       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
-                                                           PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
-    u_mm_file_reg_diag_data_buffer_ddr_MB_II  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
-                                                           PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
-    u_mm_file_ram_diag_data_buffer_ddr_MB_II  : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
-                                                           PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-                                                           
-    -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
-    u_mm_file_reg_eth0            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
-                                               PORT MAP(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
-    u_mm_file_reg_eth1            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
-                                               PORT MAP(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-    
-    u_mm_file_reg_10gbase_r_24 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
-                                                                  PORT MAP(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
-
-    u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
-                                                  PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
-    u_mm_file_reg_tr_10GbE_back0     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
-                                                  PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
-    u_mm_file_reg_tr_10GbE_back1     : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
-                                                  PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
-
-    u_mm_file_reg_eth10g_qsfp_ring   : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
-                                                  PORT MAP(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
-    u_mm_file_reg_eth10g_back0       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
-                                                  PORT MAP(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
-    u_mm_file_reg_eth10g_back1       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
-                                                  PORT MAP(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
-
-    ----------------------------------------------------------------------------
-    -- 1GbE setup sequence normally performed by unb_os@NIOS
-    ----------------------------------------------------------------------------
-    p_eth_setup : PROCESS
-    BEGIN
-      sim_eth_mm_bus_switch <= '1';
-
-      eth1g_eth0_tse_mosi.wr <= '0';
-      eth1g_eth0_tse_mosi.rd <= '0';
-      WAIT FOR 400 ns;
-      WAIT UNTIL rising_edge(mm_clk);
-      proc_tech_tse_setup(c_tech_arria10_e1sg, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
-
-      -- Enable RX
-      proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi);  -- control rx en
-      sim_eth_mm_bus_switch <= '0';
-
-      WAIT;
-    END PROCESS;
-
-    p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
-    BEGIN
-      IF sim_eth_mm_bus_switch = '1' THEN
-          eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
-        ELSE
-          eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
-        END IF;
-    END PROCESS;
+    u_mm_file_reg_ppsh            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+                                               PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
 
+    -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
+    u_mm_file_reg_eth             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+                                               PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
 
     ----------------------------------------------------------------------------
     -- Procedure that polls a sim control file that can be used to e.g. get
     -- the simulation time in ns
     ----------------------------------------------------------------------------
-    mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+    mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
 
   END GENERATE;
 
   i_reset_n <= NOT mm_rst;
-
   ----------------------------------------------------------------------------
   -- QSYS for synthesis
   ----------------------------------------------------------------------------
@@ -458,45 +175,25 @@ BEGIN
       -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
       pio_wdi_external_connection_export        => pout_wdi,
 
-      avs_eth_0_reset_export                    => eth1g_eth0_mm_rst,
+      avs_eth_0_reset_export                    => eth1g_mm_rst,
       avs_eth_0_clk_export                      => OPEN,
-      avs_eth_0_tse_address_export              => eth1g_eth0_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
-      avs_eth_0_tse_write_export                => eth1g_eth0_tse_mosi.wr,
-      avs_eth_0_tse_read_export                 => eth1g_eth0_tse_mosi.rd,
-      avs_eth_0_tse_writedata_export            => eth1g_eth0_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      avs_eth_0_tse_readdata_export             => eth1g_eth0_tse_miso.rddata(c_word_w-1 DOWNTO 0),
-      avs_eth_0_tse_waitrequest_export          => eth1g_eth0_tse_miso.waitrequest,
-      avs_eth_0_reg_address_export              => eth1g_eth0_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
-      avs_eth_0_reg_write_export                => eth1g_eth0_reg_mosi.wr,
-      avs_eth_0_reg_read_export                 => eth1g_eth0_reg_mosi.rd,
-      avs_eth_0_reg_writedata_export            => eth1g_eth0_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      avs_eth_0_reg_readdata_export             => eth1g_eth0_reg_miso.rddata(c_word_w-1 DOWNTO 0),
-      avs_eth_0_ram_address_export              => eth1g_eth0_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
-      avs_eth_0_ram_write_export                => eth1g_eth0_ram_mosi.wr,
-      avs_eth_0_ram_read_export                 => eth1g_eth0_ram_mosi.rd,
-      avs_eth_0_ram_writedata_export            => eth1g_eth0_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      avs_eth_0_ram_readdata_export             => eth1g_eth0_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-      avs_eth_0_irq_export                      => eth1g_eth0_reg_interrupt,
-
-      avs_eth_1_reset_export                    => eth1g_eth1_mm_rst,
-      avs_eth_1_clk_export                      => OPEN,
-      avs_eth_1_tse_address_export              => eth1g_eth1_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
-      avs_eth_1_tse_write_export                => eth1g_eth1_tse_mosi.wr,
-      avs_eth_1_tse_read_export                 => eth1g_eth1_tse_mosi.rd,
-      avs_eth_1_tse_writedata_export            => eth1g_eth1_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      avs_eth_1_tse_readdata_export             => eth1g_eth1_tse_miso.rddata(c_word_w-1 DOWNTO 0),
-      avs_eth_1_tse_waitrequest_export          => eth1g_eth1_tse_miso.waitrequest,
-      avs_eth_1_reg_address_export              => eth1g_eth1_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
-      avs_eth_1_reg_write_export                => eth1g_eth1_reg_mosi.wr,
-      avs_eth_1_reg_read_export                 => eth1g_eth1_reg_mosi.rd,
-      avs_eth_1_reg_writedata_export            => eth1g_eth1_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      avs_eth_1_reg_readdata_export             => eth1g_eth1_reg_miso.rddata(c_word_w-1 DOWNTO 0),
-      avs_eth_1_ram_address_export              => eth1g_eth1_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
-      avs_eth_1_ram_write_export                => eth1g_eth1_ram_mosi.wr,
-      avs_eth_1_ram_read_export                 => eth1g_eth1_ram_mosi.rd,
-      avs_eth_1_ram_writedata_export            => eth1g_eth1_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      avs_eth_1_ram_readdata_export             => eth1g_eth1_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-      avs_eth_1_irq_export                      => eth1g_eth1_reg_interrupt,
+      avs_eth_0_tse_address_export              => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+      avs_eth_0_tse_write_export                => eth1g_tse_mosi.wr,
+      avs_eth_0_tse_read_export                 => eth1g_tse_mosi.rd,
+      avs_eth_0_tse_writedata_export            => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_tse_readdata_export             => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_tse_waitrequest_export          => eth1g_tse_miso.waitrequest,
+      avs_eth_0_reg_address_export              => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+      avs_eth_0_reg_write_export                => eth1g_reg_mosi.wr,
+      avs_eth_0_reg_read_export                 => eth1g_reg_mosi.rd,
+      avs_eth_0_reg_writedata_export            => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_reg_readdata_export             => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_ram_address_export              => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+      avs_eth_0_ram_write_export                => eth1g_ram_mosi.wr,
+      avs_eth_0_ram_read_export                 => eth1g_ram_mosi.rd,
+      avs_eth_0_ram_writedata_export            => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_ram_readdata_export             => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+      avs_eth_0_irq_export                      => eth1g_reg_interrupt,
 
       reg_unb_sens_reset_export                 => OPEN,
       reg_unb_sens_clk_export                   => OPEN,
@@ -570,6 +267,14 @@ BEGIN
       reg_remu_read_export                      => reg_remu_mosi.rd,
       reg_remu_readdata_export                  => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
 
+      jesd204b_reset_export                     => OPEN,
+      jesd204b_clk_export                       => OPEN,
+      jesd204b_address_export                   => jesd204b_mosi.address(11 DOWNTO 0),
+      jesd204b_write_export                     => jesd204b_mosi.wr,
+      jesd204b_writedata_export                 => jesd204b_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      jesd204b_read_export                      => jesd204b_mosi.rd,
+      jesd204b_readdata_export                  => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+
       reg_epcs_reset_export                     => OPEN,
       reg_epcs_clk_export                       => OPEN,
       reg_epcs_address_export                   => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
@@ -610,254 +315,23 @@ BEGIN
       reg_mmdp_ctrl_write_export                => reg_mmdp_ctrl_mosi.wr,
       reg_mmdp_ctrl_writedata_export            => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
-      reg_10gbase_r_24_reset_export             => OPEN,
-      reg_10gbase_r_24_clk_export               => OPEN,
-      reg_10gbase_r_24_address_export           => reg_10gbase_r_24_mosi.address(14 DOWNTO 0),
-      reg_10gbase_r_24_write_export             => reg_10gbase_r_24_mosi.wr,
-      reg_10gbase_r_24_writedata_export         => reg_10gbase_r_24_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_10gbase_r_24_read_export              => reg_10gbase_r_24_mosi.rd,
-      reg_10gbase_r_24_readdata_export          => reg_10gbase_r_24_miso.rddata(c_word_w-1 DOWNTO 0),
-      reg_10gbase_r_24_waitrequest_export       => reg_10gbase_r_24_miso.waitrequest,
-
-      reg_tr_10gbe_qsfp_ring_reset_export       => OPEN,
-      reg_tr_10gbe_qsfp_ring_clk_export         => OPEN,
-      reg_tr_10gbe_qsfp_ring_address_export     => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w-1 DOWNTO 0),
-      reg_tr_10gbe_qsfp_ring_write_export       => reg_tr_10GbE_qsfp_ring_mosi.wr,
-      reg_tr_10gbe_qsfp_ring_writedata_export   => reg_tr_10GbE_qsfp_ring_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_tr_10gbe_qsfp_ring_read_export        => reg_tr_10GbE_qsfp_ring_mosi.rd,
-      reg_tr_10gbe_qsfp_ring_readdata_export    => reg_tr_10GbE_qsfp_ring_miso.rddata(c_word_w-1 DOWNTO 0),
-      reg_tr_10gbe_qsfp_ring_waitrequest_export => reg_tr_10GbE_qsfp_ring_miso.waitrequest,
-
-      reg_tr_10gbe_back0_reset_export           => OPEN,
-      reg_tr_10gbe_back0_clk_export             => OPEN,
-      reg_tr_10gbe_back0_address_export         => reg_tr_10GbE_back0_mosi.address(c_reg_tr_10GbE_back0_multi_adr_w-1 DOWNTO 0),
-      reg_tr_10gbe_back0_write_export           => reg_tr_10GbE_back0_mosi.wr,
-      reg_tr_10gbe_back0_writedata_export       => reg_tr_10GbE_back0_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_tr_10gbe_back0_read_export            => reg_tr_10GbE_back0_mosi.rd,
-      reg_tr_10gbe_back0_readdata_export        => reg_tr_10GbE_back0_miso.rddata(c_word_w-1 DOWNTO 0),
-      reg_tr_10gbe_back0_waitrequest_export     => reg_tr_10GbE_back0_miso.waitrequest,
-
-      reg_tr_10gbe_back1_reset_export           => OPEN,
-      reg_tr_10gbe_back1_clk_export             => OPEN,
-      reg_tr_10gbe_back1_address_export         => reg_tr_10GbE_back1_mosi.address(c_reg_tr_10GbE_back1_multi_adr_w-1 DOWNTO 0),
-      reg_tr_10gbe_back1_write_export           => reg_tr_10GbE_back1_mosi.wr,
-      reg_tr_10gbe_back1_writedata_export       => reg_tr_10GbE_back1_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_tr_10gbe_back1_read_export            => reg_tr_10GbE_back1_mosi.rd,
-      reg_tr_10gbe_back1_readdata_export        => reg_tr_10GbE_back1_miso.rddata(c_word_w-1 DOWNTO 0),
-      reg_tr_10gbe_back1_waitrequest_export     => reg_tr_10GbE_back1_miso.waitrequest,
-
-      reg_eth10g_qsfp_ring_reset_export         => OPEN,
-      reg_eth10g_qsfp_ring_clk_export           => OPEN,
-      reg_eth10g_qsfp_ring_address_export       => reg_eth10g_qsfp_ring_mosi.address(c_reg_eth10g_qsfp_ring_multi_adr_w-1 DOWNTO 0),
-      reg_eth10g_qsfp_ring_write_export         => reg_eth10g_qsfp_ring_mosi.wr,
-      reg_eth10g_qsfp_ring_writedata_export     => reg_eth10g_qsfp_ring_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_eth10g_qsfp_ring_read_export          => reg_eth10g_qsfp_ring_mosi.rd,
-      reg_eth10g_qsfp_ring_readdata_export      => reg_eth10g_qsfp_ring_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_eth10g_back0_reset_export             => OPEN,
-      reg_eth10g_back0_clk_export               => OPEN,
-      reg_eth10g_back0_address_export           => reg_eth10g_back0_mosi.address(c_reg_eth10g_back0_multi_adr_w-1 DOWNTO 0),
-      reg_eth10g_back0_write_export             => reg_eth10g_back0_mosi.wr,
-      reg_eth10g_back0_writedata_export         => reg_eth10g_back0_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_eth10g_back0_read_export              => reg_eth10g_back0_mosi.rd,
-      reg_eth10g_back0_readdata_export          => reg_eth10g_back0_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_eth10g_back1_reset_export             => OPEN,
-      reg_eth10g_back1_clk_export               => OPEN,
-      reg_eth10g_back1_address_export           => reg_eth10g_back1_mosi.address(c_reg_eth10g_back1_multi_adr_w-1 DOWNTO 0),
-      reg_eth10g_back1_write_export             => reg_eth10g_back1_mosi.wr,
-      reg_eth10g_back1_writedata_export         => reg_eth10g_back1_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_eth10g_back1_read_export              => reg_eth10g_back1_mosi.rd,
-      reg_eth10g_back1_readdata_export          => reg_eth10g_back1_miso.rddata(c_word_w-1 DOWNTO 0),
-
---      -- the_reg_dp_offload_tx_1GbE
---      reg_dp_offload_tx_1GbE_address_export         => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
---      reg_dp_offload_tx_1GbE_clk_export             => OPEN,
---      reg_dp_offload_tx_1GbE_read_export            => reg_dp_offload_tx_1GbE_mosi.rd,
---      reg_dp_offload_tx_1GbE_readdata_export        => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
---      reg_dp_offload_tx_1GbE_reset_export           => OPEN,
---      reg_dp_offload_tx_1GbE_write_export           => reg_dp_offload_tx_1GbE_mosi.wr,
---      reg_dp_offload_tx_1GbE_writedata_export       => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
---      -- the_reg_dp_offload_tx_1GbE_hdr_dat
---      reg_dp_offload_tx_1GbE_hdr_dat_address_export    => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
---      reg_dp_offload_tx_1GbE_hdr_dat_clk_export        => OPEN,
---      reg_dp_offload_tx_1GbE_hdr_dat_read_export       => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
---      reg_dp_offload_tx_1GbE_hdr_dat_readdata_export   => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
---      reg_dp_offload_tx_1GbE_hdr_dat_reset_export      => OPEN,
---      reg_dp_offload_tx_1GbE_hdr_dat_write_export      => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
---      reg_dp_offload_tx_1GbE_hdr_dat_writedata_export  => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
---      -- the_reg_dp_offload_rx_1GbE_hdr_dat
---      reg_dp_offload_rx_1GbE_hdr_dat_address_export    => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
---      reg_dp_offload_rx_1GbE_hdr_dat_clk_export        => OPEN,
---      reg_dp_offload_rx_1GbE_hdr_dat_read_export       => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
---      reg_dp_offload_rx_1GbE_hdr_dat_readdata_export   => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
---      reg_dp_offload_rx_1GbE_hdr_dat_reset_export      => OPEN,
---      reg_dp_offload_rx_1GbE_hdr_dat_write_export      => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
---      reg_dp_offload_rx_1GbE_hdr_dat_writedata_export  => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
-      reg_bsn_monitor_1gbe_reset_export         => OPEN,
-      reg_bsn_monitor_1gbe_clk_export           => OPEN,
-      reg_bsn_monitor_1gbe_address_export       => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w-1 DOWNTO 0),
-      reg_bsn_monitor_1gbe_write_export         => reg_bsn_monitor_1GbE_mosi.wr,
-      reg_bsn_monitor_1gbe_writedata_export     => reg_bsn_monitor_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_bsn_monitor_1gbe_read_export          => reg_bsn_monitor_1GbE_mosi.rd,
-      reg_bsn_monitor_1gbe_readdata_export      => reg_bsn_monitor_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_bsn_monitor_10gbe_reset_export        => OPEN,
-      reg_bsn_monitor_10gbe_clk_export          => OPEN,
-      reg_bsn_monitor_10gbe_address_export      => reg_bsn_monitor_10GbE_mosi.address(c_reg_rsp_bsn_monitor_10GbE_adr_w-1 DOWNTO 0),
-      reg_bsn_monitor_10gbe_write_export        => reg_bsn_monitor_10GbE_mosi.wr,
-      reg_bsn_monitor_10gbe_writedata_export    => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_bsn_monitor_10gbe_read_export         => reg_bsn_monitor_10GbE_mosi.rd,
-      reg_bsn_monitor_10gbe_readdata_export     => reg_bsn_monitor_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_diag_data_buffer_1gbe_reset_export     => OPEN,
-      reg_diag_data_buffer_1gbe_clk_export       => OPEN,
-      reg_diag_data_buffer_1gbe_address_export   => reg_diag_data_buf_1gbe_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
-      reg_diag_data_buffer_1gbe_write_export     => reg_diag_data_buf_1gbe_mosi.wr,
-      reg_diag_data_buffer_1gbe_writedata_export => reg_diag_data_buf_1gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_diag_data_buffer_1gbe_read_export      => reg_diag_data_buf_1gbe_mosi.rd,
-      reg_diag_data_buffer_1gbe_readdata_export  => reg_diag_data_buf_1gbe_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_diag_data_buffer_10gbe_reset_export     => OPEN,
-      reg_diag_data_buffer_10gbe_clk_export       => OPEN,
-      reg_diag_data_buffer_10gbe_address_export   => reg_diag_data_buf_10gbe_mosi.address(5 DOWNTO 0),
-      reg_diag_data_buffer_10gbe_write_export     => reg_diag_data_buf_10gbe_mosi.wr,
-      reg_diag_data_buffer_10gbe_writedata_export => reg_diag_data_buf_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_diag_data_buffer_10gbe_read_export      => reg_diag_data_buf_10gbe_mosi.rd,
-      reg_diag_data_buffer_10gbe_readdata_export  => reg_diag_data_buf_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      ram_diag_data_buffer_1gbe_clk_export       => OPEN,
-      ram_diag_data_buffer_1gbe_reset_export     => OPEN,
-      ram_diag_data_buffer_1gbe_address_export   => ram_diag_data_buf_1gbe_mosi.address(c_ram_diag_databuffer_1GbE_addr_w-1 DOWNTO 0),
-      ram_diag_data_buffer_1gbe_write_export     => ram_diag_data_buf_1gbe_mosi.wr,
-      ram_diag_data_buffer_1gbe_writedata_export => ram_diag_data_buf_1gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      ram_diag_data_buffer_1gbe_read_export      => ram_diag_data_buf_1gbe_mosi.rd,
-      ram_diag_data_buffer_1gbe_readdata_export  => ram_diag_data_buf_1gbe_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      ram_diag_data_buffer_10gbe_clk_export       => OPEN,
-      ram_diag_data_buffer_10gbe_reset_export     => OPEN,
-      ram_diag_data_buffer_10gbe_address_export   => ram_diag_data_buf_10gbe_mosi.address(c_ram_diag_databuffer_10GbE_addr_w-1 DOWNTO 0),
-      ram_diag_data_buffer_10gbe_write_export     => ram_diag_data_buf_10gbe_mosi.wr,
-      ram_diag_data_buffer_10gbe_writedata_export => ram_diag_data_buf_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      ram_diag_data_buffer_10gbe_read_export      => ram_diag_data_buf_10gbe_mosi.rd,
-      ram_diag_data_buffer_10gbe_readdata_export  => ram_diag_data_buf_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_diag_bg_1GbE_reset_export               => OPEN,
-      reg_diag_bg_1GbE_clk_export                 => OPEN,
-      reg_diag_bg_1GbE_address_export             => reg_diag_bg_1GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
-      reg_diag_bg_1GbE_write_export               => reg_diag_bg_1GbE_mosi.wr,
-      reg_diag_bg_1GbE_writedata_export           => reg_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_diag_bg_1GbE_read_export                => reg_diag_bg_1GbE_mosi.rd,
-      reg_diag_bg_1GbE_readdata_export            => reg_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_diag_bg_10GbE_reset_export              => OPEN,
-      reg_diag_bg_10GbE_clk_export                => OPEN,
-      reg_diag_bg_10GbE_address_export            => reg_diag_bg_10GbE_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
-      reg_diag_bg_10GbE_write_export              => reg_diag_bg_10GbE_mosi.wr,
-      reg_diag_bg_10GbE_writedata_export          => reg_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_diag_bg_10GbE_read_export               => reg_diag_bg_10GbE_mosi.rd,
-      reg_diag_bg_10GbE_readdata_export           => reg_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      ram_diag_bg_1GbE_reset_export               => OPEN,
-      ram_diag_bg_1GbE_clk_export                 => OPEN,
-      ram_diag_bg_1GbE_address_export             => ram_diag_bg_1GbE_mosi.address(c_ram_diag_bg_1GbE_addr_w-1 DOWNTO 0),
-      ram_diag_bg_1GbE_write_export               => ram_diag_bg_1GbE_mosi.wr,
-      ram_diag_bg_1GbE_writedata_export           => ram_diag_bg_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      ram_diag_bg_1GbE_read_export                => ram_diag_bg_1GbE_mosi.rd,
-      ram_diag_bg_1GbE_readdata_export            => ram_diag_bg_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      ram_diag_bg_10GbE_reset_export              => OPEN,
-      ram_diag_bg_10GbE_clk_export                => OPEN,
-      ram_diag_bg_10GbE_address_export            => ram_diag_bg_10GbE_mosi.address(c_ram_diag_bg_10GbE_addr_w-1 DOWNTO 0),
-      ram_diag_bg_10GbE_write_export              => ram_diag_bg_10GbE_mosi.wr,
-      ram_diag_bg_10GbE_writedata_export          => ram_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      ram_diag_bg_10GbE_read_export               => ram_diag_bg_10GbE_mosi.rd,
-      ram_diag_bg_10GbE_readdata_export           => ram_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_io_ddr_MB_I_address_export                  => reg_io_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
-      reg_io_ddr_MB_I_clk_export                      => OPEN,
-      reg_io_ddr_MB_I_read_export                     => reg_io_ddr_MB_I_mosi.rd,
-      reg_io_ddr_MB_I_readdata_export                 => reg_io_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
-      reg_io_ddr_MB_I_reset_export                    => OPEN,
-      reg_io_ddr_MB_I_write_export                    => reg_io_ddr_MB_I_mosi.wr,
-      reg_io_ddr_MB_I_writedata_export                => reg_io_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      
-      reg_io_ddr_MB_II_address_export                 => reg_io_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
-      reg_io_ddr_MB_II_clk_export                     => OPEN,
-      reg_io_ddr_MB_II_read_export                    => reg_io_ddr_MB_II_mosi.rd,
-      reg_io_ddr_MB_II_readdata_export                => reg_io_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
-      reg_io_ddr_MB_II_reset_export                   => OPEN,
-      reg_io_ddr_MB_II_write_export                   => reg_io_ddr_MB_II_mosi.wr,
-      reg_io_ddr_MB_II_writedata_export               => reg_io_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      
-   		reg_diag_tx_seq_ddr_MB_I_reset_export           => OPEN,
-   		reg_diag_tx_seq_ddr_MB_I_clk_export             => OPEN,
-   		reg_diag_tx_seq_ddr_MB_I_address_export         => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
-   		reg_diag_tx_seq_ddr_MB_I_write_export           => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
-   		reg_diag_tx_seq_ddr_MB_I_writedata_export       => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
-   		reg_diag_tx_seq_ddr_MB_I_read_export            => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
-   		reg_diag_tx_seq_ddr_MB_I_readdata_export        => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
-
-   		reg_diag_tx_seq_ddr_MB_II_reset_export          => OPEN,
-   		reg_diag_tx_seq_ddr_MB_II_clk_export            => OPEN,
-   		reg_diag_tx_seq_ddr_MB_II_address_export        => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
-   		reg_diag_tx_seq_ddr_MB_II_write_export          => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
-   		reg_diag_tx_seq_ddr_MB_II_writedata_export      => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
-   		reg_diag_tx_seq_ddr_MB_II_read_export           => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
-   		reg_diag_tx_seq_ddr_MB_II_readdata_export       => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      reg_diag_rx_seq_ddr_MB_I_reset_export           => OPEN,
-      reg_diag_rx_seq_ddr_MB_I_clk_export             => OPEN,
-      reg_diag_rx_seq_ddr_MB_I_address_export         => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
-      reg_diag_rx_seq_ddr_MB_I_write_export           => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
-      reg_diag_rx_seq_ddr_MB_I_writedata_export       => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 downto 0),
-      reg_diag_rx_seq_ddr_MB_I_read_export            => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
-      reg_diag_rx_seq_ddr_MB_I_readdata_export        => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w-1 downto 0),
-
-      reg_diag_rx_seq_ddr_MB_II_reset_export          => OPEN,
-      reg_diag_rx_seq_ddr_MB_II_clk_export            => OPEN,
-      reg_diag_rx_seq_ddr_MB_II_address_export        => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
-      reg_diag_rx_seq_ddr_MB_II_write_export          => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
-      reg_diag_rx_seq_ddr_MB_II_writedata_export      => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 downto 0),
-      reg_diag_rx_seq_ddr_MB_II_read_export           => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
-      reg_diag_rx_seq_ddr_MB_II_readdata_export       => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w-1 downto 0),
-
-      reg_diag_data_buffer_ddr_MB_I_reset_export      => OPEN,
-      reg_diag_data_buffer_ddr_MB_I_clk_export        => OPEN,
-      reg_diag_data_buffer_ddr_MB_I_address_export    => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
-      reg_diag_data_buffer_ddr_MB_I_write_export      => reg_diag_data_buf_ddr_MB_I_mosi.wr,
-      reg_diag_data_buffer_ddr_MB_I_writedata_export  => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_diag_data_buffer_ddr_MB_I_read_export       => reg_diag_data_buf_ddr_MB_I_mosi.rd,
-      reg_diag_data_buffer_ddr_MB_I_readdata_export   => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
-      
-      reg_diag_data_buffer_ddr_MB_II_reset_export     => OPEN,
-      reg_diag_data_buffer_ddr_MB_II_clk_export       => OPEN,
-      reg_diag_data_buffer_ddr_MB_II_address_export   => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
-      reg_diag_data_buffer_ddr_MB_II_write_export     => reg_diag_data_buf_ddr_MB_II_mosi.wr,
-      reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      reg_diag_data_buffer_ddr_MB_II_read_export      => reg_diag_data_buf_ddr_MB_II_mosi.rd,
-      reg_diag_data_buffer_ddr_MB_II_readdata_export  => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
-
-      ram_diag_data_buffer_ddr_MB_I_clk_export        => OPEN,
-      ram_diag_data_buffer_ddr_MB_I_reset_export      => OPEN,
-      ram_diag_data_buffer_ddr_MB_I_address_export    => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
-      ram_diag_data_buffer_ddr_MB_I_write_export      => ram_diag_data_buf_ddr_MB_I_mosi.wr,
-      ram_diag_data_buffer_ddr_MB_I_writedata_export  => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      ram_diag_data_buffer_ddr_MB_I_read_export       => ram_diag_data_buf_ddr_MB_I_mosi.rd,
-      ram_diag_data_buffer_ddr_MB_I_readdata_export   => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
-      
-      ram_diag_data_buffer_ddr_MB_II_clk_export       => OPEN,
-      ram_diag_data_buffer_ddr_MB_II_reset_export     => OPEN,
-      ram_diag_data_buffer_ddr_MB_II_address_export   => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
-      ram_diag_data_buffer_ddr_MB_II_write_export     => ram_diag_data_buf_ddr_MB_II_mosi.wr,
-      ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
-      ram_diag_data_buffer_ddr_MB_II_read_export      => ram_diag_data_buf_ddr_MB_II_mosi.rd,
-      ram_diag_data_buffer_ddr_MB_II_readdata_export  => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0)
+
+      ram_diag_data_buf_jesd_clk_export         => OPEN,
+      ram_diag_data_buf_jesd_reset_export       => OPEN,
+      ram_diag_data_buf_jesd_address_export     => ram_diag_data_buf_jesd_mosi.address(17-1 DOWNTO 0),
+      ram_diag_data_buf_jesd_write_export       => ram_diag_data_buf_jesd_mosi.wr,
+      ram_diag_data_buf_jesd_writedata_export   => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      ram_diag_data_buf_jesd_read_export        => ram_diag_data_buf_jesd_mosi.rd,
+      ram_diag_data_buf_jesd_readdata_export    => ram_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_diag_data_buf_jesd_reset_export       => OPEN,
+      reg_diag_data_buf_jesd_clk_export         => OPEN,
+      reg_diag_data_buf_jesd_address_export     => reg_diag_data_buf_jesd_mosi.address(12-1 DOWNTO 0),
+      reg_diag_data_buf_jesd_write_export       => reg_diag_data_buf_jesd_mosi.wr,
+      reg_diag_data_buf_jesd_writedata_export   => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_diag_data_buf_jesd_read_export        => reg_diag_data_buf_jesd_mosi.rd,
+      reg_diag_data_buf_jesd_readdata_export    => reg_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0)
+
     );
   END GENERATE;
-
 END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index 3f65ef343603eacf4ef78ffec631e56fe6a32008..35aec5cc67d11350b30d0534a25038c460e8e217 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -22,7 +22,7 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 
-PACKAGE qsys_unb2b_test_pkg IS
+PACKAGE qsys_lofar2_unb2b_adc_pkg IS
 
   -----------------------------------------------------------------------------
   -- this component declaration is copy-pasted from Quartus QSYS builder generated file:
@@ -30,371 +30,150 @@ PACKAGE qsys_unb2b_test_pkg IS
   -----------------------------------------------------------------------------
   
     component qsys_lofar2_unb2b_adc is
-       	port (
-            avs_eth_0_clk_export                                      : out std_logic;                                        --                                      avs_eth_0_clk.export
-            avs_eth_0_irq_export                                      : in  std_logic                     := '0';             --                                      avs_eth_0_irq.export
-            avs_eth_0_ram_address_export                              : out std_logic_vector(9 downto 0);                     --                              avs_eth_0_ram_address.export
-            avs_eth_0_ram_read_export                                 : out std_logic;                                        --                                 avs_eth_0_ram_read.export
-            avs_eth_0_ram_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             avs_eth_0_ram_readdata.export
-            avs_eth_0_ram_write_export                                : out std_logic;                                        --                                avs_eth_0_ram_write.export
-            avs_eth_0_ram_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            avs_eth_0_ram_writedata.export
-            avs_eth_0_reg_address_export                              : out std_logic_vector(3 downto 0);                     --                              avs_eth_0_reg_address.export
-            avs_eth_0_reg_read_export                                 : out std_logic;                                        --                                 avs_eth_0_reg_read.export
-            avs_eth_0_reg_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             avs_eth_0_reg_readdata.export
-            avs_eth_0_reg_write_export                                : out std_logic;                                        --                                avs_eth_0_reg_write.export
-            avs_eth_0_reg_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            avs_eth_0_reg_writedata.export
-            avs_eth_0_reset_export                                    : out std_logic;                                        --                                    avs_eth_0_reset.export
-            avs_eth_0_tse_address_export                              : out std_logic_vector(9 downto 0);                     --                              avs_eth_0_tse_address.export
-            avs_eth_0_tse_read_export                                 : out std_logic;                                        --                                 avs_eth_0_tse_read.export
-            avs_eth_0_tse_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             avs_eth_0_tse_readdata.export
-            avs_eth_0_tse_waitrequest_export                          : in  std_logic                     := '0';             --                          avs_eth_0_tse_waitrequest.export
-            avs_eth_0_tse_write_export                                : out std_logic;                                        --                                avs_eth_0_tse_write.export
-            avs_eth_0_tse_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            avs_eth_0_tse_writedata.export
-            avs_eth_1_clk_export                                      : out std_logic;                                        --                                      avs_eth_1_clk.export
-            avs_eth_1_irq_export                                      : in  std_logic                     := '0';             --                                      avs_eth_1_irq.export
-            avs_eth_1_ram_address_export                              : out std_logic_vector(9 downto 0);                     --                              avs_eth_1_ram_address.export
-            avs_eth_1_ram_read_export                                 : out std_logic;                                        --                                 avs_eth_1_ram_read.export
-            avs_eth_1_ram_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             avs_eth_1_ram_readdata.export
-            avs_eth_1_ram_write_export                                : out std_logic;                                        --                                avs_eth_1_ram_write.export
-            avs_eth_1_ram_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            avs_eth_1_ram_writedata.export
-            avs_eth_1_reg_address_export                              : out std_logic_vector(3 downto 0);                     --                              avs_eth_1_reg_address.export
-            avs_eth_1_reg_read_export                                 : out std_logic;                                        --                                 avs_eth_1_reg_read.export
-            avs_eth_1_reg_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             avs_eth_1_reg_readdata.export
-            avs_eth_1_reg_write_export                                : out std_logic;                                        --                                avs_eth_1_reg_write.export
-            avs_eth_1_reg_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            avs_eth_1_reg_writedata.export
-            avs_eth_1_reset_export                                    : out std_logic;                                        --                                    avs_eth_1_reset.export
-            avs_eth_1_tse_address_export                              : out std_logic_vector(9 downto 0);                     --                              avs_eth_1_tse_address.export
-            avs_eth_1_tse_read_export                                 : out std_logic;                                        --                                 avs_eth_1_tse_read.export
-            avs_eth_1_tse_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             avs_eth_1_tse_readdata.export
-            avs_eth_1_tse_waitrequest_export                          : in  std_logic                     := '0';             --                          avs_eth_1_tse_waitrequest.export
-            avs_eth_1_tse_write_export                                : out std_logic;                                        --                                avs_eth_1_tse_write.export
-            avs_eth_1_tse_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            avs_eth_1_tse_writedata.export
-            clk_clk                                                   : in  std_logic                     := '0';             --                                                clk.clk
-            pio_pps_address_export                                    : out std_logic_vector(0 downto 0);                     --                                    pio_pps_address.export
-            pio_pps_clk_export                                        : out std_logic;                                        --                                        pio_pps_clk.export
-            pio_pps_read_export                                       : out std_logic;                                        --                                       pio_pps_read.export
-            pio_pps_readdata_export                                   : in  std_logic_vector(31 downto 0) := (others => '0'); --                                   pio_pps_readdata.export
-            pio_pps_reset_export                                      : out std_logic;                                        --                                      pio_pps_reset.export
-            pio_pps_write_export                                      : out std_logic;                                        --                                      pio_pps_write.export
-            pio_pps_writedata_export                                  : out std_logic_vector(31 downto 0);                    --                                  pio_pps_writedata.export
-            pio_system_info_address_export                            : out std_logic_vector(4 downto 0);                     --                            pio_system_info_address.export
-            pio_system_info_clk_export                                : out std_logic;                                        --                                pio_system_info_clk.export
-            pio_system_info_read_export                               : out std_logic;                                        --                               pio_system_info_read.export
-            pio_system_info_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => '0'); --                           pio_system_info_readdata.export
-            pio_system_info_reset_export                              : out std_logic;                                        --                              pio_system_info_reset.export
-            pio_system_info_write_export                              : out std_logic;                                        --                              pio_system_info_write.export
-            pio_system_info_writedata_export                          : out std_logic_vector(31 downto 0);                    --                          pio_system_info_writedata.export
-            pio_wdi_external_connection_export                        : out std_logic;                                        --                        pio_wdi_external_connection.export
-            ram_diag_bg_10gbe_address_export                          : out std_logic_vector(16 downto 0);                    --                          ram_diag_bg_10gbe_address.export
-            ram_diag_bg_10gbe_clk_export                              : out std_logic;                                        --                              ram_diag_bg_10gbe_clk.export
-            ram_diag_bg_10gbe_read_export                             : out std_logic;                                        --                             ram_diag_bg_10gbe_read.export
-            ram_diag_bg_10gbe_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => '0'); --                         ram_diag_bg_10gbe_readdata.export
-            ram_diag_bg_10gbe_reset_export                            : out std_logic;                                        --                            ram_diag_bg_10gbe_reset.export
-            ram_diag_bg_10gbe_write_export                            : out std_logic;                                        --                            ram_diag_bg_10gbe_write.export
-            ram_diag_bg_10gbe_writedata_export                        : out std_logic_vector(31 downto 0);                    --                        ram_diag_bg_10gbe_writedata.export
-            ram_diag_bg_1gbe_address_export                           : out std_logic_vector(10 downto 0);                    --                           ram_diag_bg_1gbe_address.export
-            ram_diag_bg_1gbe_clk_export                               : out std_logic;                                        --                               ram_diag_bg_1gbe_clk.export
-            ram_diag_bg_1gbe_read_export                              : out std_logic;                                        --                              ram_diag_bg_1gbe_read.export
-            ram_diag_bg_1gbe_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => '0'); --                          ram_diag_bg_1gbe_readdata.export
-            ram_diag_bg_1gbe_reset_export                             : out std_logic;                                        --                             ram_diag_bg_1gbe_reset.export
-            ram_diag_bg_1gbe_write_export                             : out std_logic;                                        --                             ram_diag_bg_1gbe_write.export
-            ram_diag_bg_1gbe_writedata_export                         : out std_logic_vector(31 downto 0);                    --                         ram_diag_bg_1gbe_writedata.export
-            ram_diag_data_buffer_10gbe_address_export                 : out std_logic_vector(16 downto 0);                    --                 ram_diag_data_buffer_10gbe_address.export
-            ram_diag_data_buffer_10gbe_clk_export                     : out std_logic;                                        --                     ram_diag_data_buffer_10gbe_clk.export
-            ram_diag_data_buffer_10gbe_read_export                    : out std_logic;                                        --                    ram_diag_data_buffer_10gbe_read.export
-            ram_diag_data_buffer_10gbe_readdata_export                : in  std_logic_vector(31 downto 0) := (others => '0'); --                ram_diag_data_buffer_10gbe_readdata.export
-            ram_diag_data_buffer_10gbe_reset_export                   : out std_logic;                                        --                   ram_diag_data_buffer_10gbe_reset.export
-            ram_diag_data_buffer_10gbe_write_export                   : out std_logic;                                        --                   ram_diag_data_buffer_10gbe_write.export
-            ram_diag_data_buffer_10gbe_writedata_export               : out std_logic_vector(31 downto 0);                    --               ram_diag_data_buffer_10gbe_writedata.export
-            ram_diag_data_buffer_1gbe_address_export                  : out std_logic_vector(10 downto 0);                    --                  ram_diag_data_buffer_1gbe_address.export
-            ram_diag_data_buffer_1gbe_clk_export                      : out std_logic;                                        --                      ram_diag_data_buffer_1gbe_clk.export
-            ram_diag_data_buffer_1gbe_read_export                     : out std_logic;                                        --                     ram_diag_data_buffer_1gbe_read.export
-            ram_diag_data_buffer_1gbe_readdata_export                 : in  std_logic_vector(31 downto 0) := (others => '0'); --                 ram_diag_data_buffer_1gbe_readdata.export
-            ram_diag_data_buffer_1gbe_reset_export                    : out std_logic;                                        --                    ram_diag_data_buffer_1gbe_reset.export
-            ram_diag_data_buffer_1gbe_write_export                    : out std_logic;                                        --                    ram_diag_data_buffer_1gbe_write.export
-            ram_diag_data_buffer_1gbe_writedata_export                : out std_logic_vector(31 downto 0);                    --                ram_diag_data_buffer_1gbe_writedata.export
-            ram_diag_data_buffer_ddr_mb_i_address_export              : out std_logic_vector(10 downto 0);                    --              ram_diag_data_buffer_ddr_mb_i_address.export
-            ram_diag_data_buffer_ddr_mb_i_clk_export                  : out std_logic;                                        --                  ram_diag_data_buffer_ddr_mb_i_clk.export
-            ram_diag_data_buffer_ddr_mb_i_read_export                 : out std_logic;                                        --                 ram_diag_data_buffer_ddr_mb_i_read.export
-            ram_diag_data_buffer_ddr_mb_i_readdata_export             : in  std_logic_vector(31 downto 0) := (others => '0'); --             ram_diag_data_buffer_ddr_mb_i_readdata.export
-            ram_diag_data_buffer_ddr_mb_i_reset_export                : out std_logic;                                        --                ram_diag_data_buffer_ddr_mb_i_reset.export
-            ram_diag_data_buffer_ddr_mb_i_write_export                : out std_logic;                                        --                ram_diag_data_buffer_ddr_mb_i_write.export
-            ram_diag_data_buffer_ddr_mb_i_writedata_export            : out std_logic_vector(31 downto 0);                    --            ram_diag_data_buffer_ddr_mb_i_writedata.export
-            ram_diag_data_buffer_ddr_mb_ii_address_export             : out std_logic_vector(10 downto 0);                    --             ram_diag_data_buffer_ddr_mb_ii_address.export
-            ram_diag_data_buffer_ddr_mb_ii_clk_export                 : out std_logic;                                        --                 ram_diag_data_buffer_ddr_mb_ii_clk.export
-            ram_diag_data_buffer_ddr_mb_ii_read_export                : out std_logic;                                        --                ram_diag_data_buffer_ddr_mb_ii_read.export
-            ram_diag_data_buffer_ddr_mb_ii_readdata_export            : in  std_logic_vector(31 downto 0) := (others => '0'); --            ram_diag_data_buffer_ddr_mb_ii_readdata.export
-            ram_diag_data_buffer_ddr_mb_ii_reset_export               : out std_logic;                                        --               ram_diag_data_buffer_ddr_mb_ii_reset.export
-            ram_diag_data_buffer_ddr_mb_ii_write_export               : out std_logic;                                        --               ram_diag_data_buffer_ddr_mb_ii_write.export
-            ram_diag_data_buffer_ddr_mb_ii_writedata_export           : out std_logic_vector(31 downto 0);                    --           ram_diag_data_buffer_ddr_mb_ii_writedata.export
-            reg_bsn_monitor_10gbe_address_export                      : out std_logic_vector(10 downto 0);                    --                      reg_bsn_monitor_10gbe_address.export
-            reg_bsn_monitor_10gbe_clk_export                          : out std_logic;                                        --                          reg_bsn_monitor_10gbe_clk.export
-            reg_bsn_monitor_10gbe_read_export                         : out std_logic;                                        --                         reg_bsn_monitor_10gbe_read.export
-            reg_bsn_monitor_10gbe_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => '0'); --                     reg_bsn_monitor_10gbe_readdata.export
-            reg_bsn_monitor_10gbe_reset_export                        : out std_logic;                                        --                        reg_bsn_monitor_10gbe_reset.export
-            reg_bsn_monitor_10gbe_write_export                        : out std_logic;                                        --                        reg_bsn_monitor_10gbe_write.export
-            reg_bsn_monitor_10gbe_writedata_export                    : out std_logic_vector(31 downto 0);                    --                    reg_bsn_monitor_10gbe_writedata.export
-            reg_bsn_monitor_1gbe_address_export                       : out std_logic_vector(4 downto 0);                     --                       reg_bsn_monitor_1gbe_address.export
-            reg_bsn_monitor_1gbe_clk_export                           : out std_logic;                                        --                           reg_bsn_monitor_1gbe_clk.export
-            reg_bsn_monitor_1gbe_read_export                          : out std_logic;                                        --                          reg_bsn_monitor_1gbe_read.export
-            reg_bsn_monitor_1gbe_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => '0'); --                      reg_bsn_monitor_1gbe_readdata.export
-            reg_bsn_monitor_1gbe_reset_export                         : out std_logic;                                        --                         reg_bsn_monitor_1gbe_reset.export
-            reg_bsn_monitor_1gbe_write_export                         : out std_logic;                                        --                         reg_bsn_monitor_1gbe_write.export
-            reg_bsn_monitor_1gbe_writedata_export                     : out std_logic_vector(31 downto 0);                    --                     reg_bsn_monitor_1gbe_writedata.export
-            reg_diag_bg_10gbe_address_export                          : out std_logic_vector(2 downto 0);                     --                          reg_diag_bg_10gbe_address.export
-            reg_diag_bg_10gbe_clk_export                              : out std_logic;                                        --                              reg_diag_bg_10gbe_clk.export
-            reg_diag_bg_10gbe_read_export                             : out std_logic;                                        --                             reg_diag_bg_10gbe_read.export
-            reg_diag_bg_10gbe_readdata_export                         : in  std_logic_vector(31 downto 0) := (others => '0'); --                         reg_diag_bg_10gbe_readdata.export
-            reg_diag_bg_10gbe_reset_export                            : out std_logic;                                        --                            reg_diag_bg_10gbe_reset.export
-            reg_diag_bg_10gbe_write_export                            : out std_logic;                                        --                            reg_diag_bg_10gbe_write.export
-            reg_diag_bg_10gbe_writedata_export                        : out std_logic_vector(31 downto 0);                    --                        reg_diag_bg_10gbe_writedata.export
-            reg_diag_bg_1gbe_address_export                           : out std_logic_vector(2 downto 0);                     --                           reg_diag_bg_1gbe_address.export
-            reg_diag_bg_1gbe_clk_export                               : out std_logic;                                        --                               reg_diag_bg_1gbe_clk.export
-            reg_diag_bg_1gbe_read_export                              : out std_logic;                                        --                              reg_diag_bg_1gbe_read.export
-            reg_diag_bg_1gbe_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => '0'); --                          reg_diag_bg_1gbe_readdata.export
-            reg_diag_bg_1gbe_reset_export                             : out std_logic;                                        --                             reg_diag_bg_1gbe_reset.export
-            reg_diag_bg_1gbe_write_export                             : out std_logic;                                        --                             reg_diag_bg_1gbe_write.export
-            reg_diag_bg_1gbe_writedata_export                         : out std_logic_vector(31 downto 0);                    --                         reg_diag_bg_1gbe_writedata.export
-            reg_diag_data_buffer_10gbe_address_export                 : out std_logic_vector(5 downto 0);                     --                 reg_diag_data_buffer_10gbe_address.export
-            reg_diag_data_buffer_10gbe_clk_export                     : out std_logic;                                        --                     reg_diag_data_buffer_10gbe_clk.export
-            reg_diag_data_buffer_10gbe_read_export                    : out std_logic;                                        --                    reg_diag_data_buffer_10gbe_read.export
-            reg_diag_data_buffer_10gbe_readdata_export                : in  std_logic_vector(31 downto 0) := (others => '0'); --                reg_diag_data_buffer_10gbe_readdata.export
-            reg_diag_data_buffer_10gbe_reset_export                   : out std_logic;                                        --                   reg_diag_data_buffer_10gbe_reset.export
-            reg_diag_data_buffer_10gbe_write_export                   : out std_logic;                                        --                   reg_diag_data_buffer_10gbe_write.export
-            reg_diag_data_buffer_10gbe_writedata_export               : out std_logic_vector(31 downto 0);                    --               reg_diag_data_buffer_10gbe_writedata.export
-            reg_diag_data_buffer_1gbe_address_export                  : out std_logic_vector(4 downto 0);                     --                  reg_diag_data_buffer_1gbe_address.export
-            reg_diag_data_buffer_1gbe_clk_export                      : out std_logic;                                        --                      reg_diag_data_buffer_1gbe_clk.export
-            reg_diag_data_buffer_1gbe_read_export                     : out std_logic;                                        --                     reg_diag_data_buffer_1gbe_read.export
-            reg_diag_data_buffer_1gbe_readdata_export                 : in  std_logic_vector(31 downto 0) := (others => '0'); --                 reg_diag_data_buffer_1gbe_readdata.export
-            reg_diag_data_buffer_1gbe_reset_export                    : out std_logic;                                        --                    reg_diag_data_buffer_1gbe_reset.export
-            reg_diag_data_buffer_1gbe_write_export                    : out std_logic;                                        --                    reg_diag_data_buffer_1gbe_write.export
-            reg_diag_data_buffer_1gbe_writedata_export                : out std_logic_vector(31 downto 0);                    --                reg_diag_data_buffer_1gbe_writedata.export
-            reg_diag_data_buffer_ddr_mb_i_address_export              : out std_logic_vector(4 downto 0);                     --              reg_diag_data_buffer_ddr_mb_i_address.export
-            reg_diag_data_buffer_ddr_mb_i_clk_export                  : out std_logic;                                        --                  reg_diag_data_buffer_ddr_mb_i_clk.export
-            reg_diag_data_buffer_ddr_mb_i_read_export                 : out std_logic;                                        --                 reg_diag_data_buffer_ddr_mb_i_read.export
-            reg_diag_data_buffer_ddr_mb_i_readdata_export             : in  std_logic_vector(31 downto 0) := (others => '0'); --             reg_diag_data_buffer_ddr_mb_i_readdata.export
-            reg_diag_data_buffer_ddr_mb_i_reset_export                : out std_logic;                                        --                reg_diag_data_buffer_ddr_mb_i_reset.export
-            reg_diag_data_buffer_ddr_mb_i_write_export                : out std_logic;                                        --                reg_diag_data_buffer_ddr_mb_i_write.export
-            reg_diag_data_buffer_ddr_mb_i_writedata_export            : out std_logic_vector(31 downto 0);                    --            reg_diag_data_buffer_ddr_mb_i_writedata.export
-            reg_diag_data_buffer_ddr_mb_ii_address_export             : out std_logic_vector(4 downto 0);                     --             reg_diag_data_buffer_ddr_mb_ii_address.export
-            reg_diag_data_buffer_ddr_mb_ii_clk_export                 : out std_logic;                                        --                 reg_diag_data_buffer_ddr_mb_ii_clk.export
-            reg_diag_data_buffer_ddr_mb_ii_read_export                : out std_logic;                                        --                reg_diag_data_buffer_ddr_mb_ii_read.export
-            reg_diag_data_buffer_ddr_mb_ii_readdata_export            : in  std_logic_vector(31 downto 0) := (others => '0'); --            reg_diag_data_buffer_ddr_mb_ii_readdata.export
-            reg_diag_data_buffer_ddr_mb_ii_reset_export               : out std_logic;                                        --               reg_diag_data_buffer_ddr_mb_ii_reset.export
-            reg_diag_data_buffer_ddr_mb_ii_write_export               : out std_logic;                                        --               reg_diag_data_buffer_ddr_mb_ii_write.export
-            reg_diag_data_buffer_ddr_mb_ii_writedata_export           : out std_logic_vector(31 downto 0);                    --           reg_diag_data_buffer_ddr_mb_ii_writedata.export
-            reg_diag_rx_seq_10gbe_address_export                      : out std_logic_vector(4 downto 0);                     --                      reg_diag_rx_seq_10gbe_address.export
-            reg_diag_rx_seq_10gbe_clk_export                          : out std_logic;                                        --                          reg_diag_rx_seq_10gbe_clk.export
-            reg_diag_rx_seq_10gbe_read_export                         : out std_logic;                                        --                         reg_diag_rx_seq_10gbe_read.export
-            reg_diag_rx_seq_10gbe_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => '0'); --                     reg_diag_rx_seq_10gbe_readdata.export
-            reg_diag_rx_seq_10gbe_reset_export                        : out std_logic;                                        --                        reg_diag_rx_seq_10gbe_reset.export
-            reg_diag_rx_seq_10gbe_write_export                        : out std_logic;                                        --                        reg_diag_rx_seq_10gbe_write.export
-            reg_diag_rx_seq_10gbe_writedata_export                    : out std_logic_vector(31 downto 0);                    --                    reg_diag_rx_seq_10gbe_writedata.export
-            reg_diag_rx_seq_1gbe_address_export                       : out std_logic_vector(2 downto 0);                     --                       reg_diag_rx_seq_1gbe_address.export
-            reg_diag_rx_seq_1gbe_clk_export                           : out std_logic;                                        --                           reg_diag_rx_seq_1gbe_clk.export
-            reg_diag_rx_seq_1gbe_read_export                          : out std_logic;                                        --                          reg_diag_rx_seq_1gbe_read.export
-            reg_diag_rx_seq_1gbe_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => '0'); --                      reg_diag_rx_seq_1gbe_readdata.export
-            reg_diag_rx_seq_1gbe_reset_export                         : out std_logic;                                        --                         reg_diag_rx_seq_1gbe_reset.export
-            reg_diag_rx_seq_1gbe_write_export                         : out std_logic;                                        --                         reg_diag_rx_seq_1gbe_write.export
-            reg_diag_rx_seq_1gbe_writedata_export                     : out std_logic_vector(31 downto 0);                    --                     reg_diag_rx_seq_1gbe_writedata.export
-            reg_diag_rx_seq_ddr_mb_i_address_export                   : out std_logic_vector(2 downto 0);                     --                   reg_diag_rx_seq_ddr_mb_i_address.export
-            reg_diag_rx_seq_ddr_mb_i_clk_export                       : out std_logic;                                        --                       reg_diag_rx_seq_ddr_mb_i_clk.export
-            reg_diag_rx_seq_ddr_mb_i_read_export                      : out std_logic;                                        --                      reg_diag_rx_seq_ddr_mb_i_read.export
-            reg_diag_rx_seq_ddr_mb_i_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => '0'); --                  reg_diag_rx_seq_ddr_mb_i_readdata.export
-            reg_diag_rx_seq_ddr_mb_i_reset_export                     : out std_logic;                                        --                     reg_diag_rx_seq_ddr_mb_i_reset.export
-            reg_diag_rx_seq_ddr_mb_i_write_export                     : out std_logic;                                        --                     reg_diag_rx_seq_ddr_mb_i_write.export
-            reg_diag_rx_seq_ddr_mb_i_writedata_export                 : out std_logic_vector(31 downto 0);                    --                 reg_diag_rx_seq_ddr_mb_i_writedata.export
-            reg_diag_rx_seq_ddr_mb_ii_address_export                  : out std_logic_vector(2 downto 0);                     --                  reg_diag_rx_seq_ddr_mb_ii_address.export
-            reg_diag_rx_seq_ddr_mb_ii_clk_export                      : out std_logic;                                        --                      reg_diag_rx_seq_ddr_mb_ii_clk.export
-            reg_diag_rx_seq_ddr_mb_ii_read_export                     : out std_logic;                                        --                     reg_diag_rx_seq_ddr_mb_ii_read.export
-            reg_diag_rx_seq_ddr_mb_ii_readdata_export                 : in  std_logic_vector(31 downto 0) := (others => '0'); --                 reg_diag_rx_seq_ddr_mb_ii_readdata.export
-            reg_diag_rx_seq_ddr_mb_ii_reset_export                    : out std_logic;                                        --                    reg_diag_rx_seq_ddr_mb_ii_reset.export
-            reg_diag_rx_seq_ddr_mb_ii_write_export                    : out std_logic;                                        --                    reg_diag_rx_seq_ddr_mb_ii_write.export
-            reg_diag_rx_seq_ddr_mb_ii_writedata_export                : out std_logic_vector(31 downto 0);                    --                reg_diag_rx_seq_ddr_mb_ii_writedata.export
-            reg_diag_tx_seq_10gbe_address_export                      : out std_logic_vector(3 downto 0);                     --                      reg_diag_tx_seq_10gbe_address.export
-            reg_diag_tx_seq_10gbe_clk_export                          : out std_logic;                                        --                          reg_diag_tx_seq_10gbe_clk.export
-            reg_diag_tx_seq_10gbe_read_export                         : out std_logic;                                        --                         reg_diag_tx_seq_10gbe_read.export
-            reg_diag_tx_seq_10gbe_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => '0'); --                     reg_diag_tx_seq_10gbe_readdata.export
-            reg_diag_tx_seq_10gbe_reset_export                        : out std_logic;                                        --                        reg_diag_tx_seq_10gbe_reset.export
-            reg_diag_tx_seq_10gbe_write_export                        : out std_logic;                                        --                        reg_diag_tx_seq_10gbe_write.export
-            reg_diag_tx_seq_10gbe_writedata_export                    : out std_logic_vector(31 downto 0);                    --                    reg_diag_tx_seq_10gbe_writedata.export
-            reg_diag_tx_seq_1gbe_address_export                       : out std_logic_vector(1 downto 0);                     --                       reg_diag_tx_seq_1gbe_address.export
-            reg_diag_tx_seq_1gbe_clk_export                           : out std_logic;                                        --                           reg_diag_tx_seq_1gbe_clk.export
-            reg_diag_tx_seq_1gbe_read_export                          : out std_logic;                                        --                          reg_diag_tx_seq_1gbe_read.export
-            reg_diag_tx_seq_1gbe_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => '0'); --                      reg_diag_tx_seq_1gbe_readdata.export
-            reg_diag_tx_seq_1gbe_reset_export                         : out std_logic;                                        --                         reg_diag_tx_seq_1gbe_reset.export
-            reg_diag_tx_seq_1gbe_write_export                         : out std_logic;                                        --                         reg_diag_tx_seq_1gbe_write.export
-            reg_diag_tx_seq_1gbe_writedata_export                     : out std_logic_vector(31 downto 0);                    --                     reg_diag_tx_seq_1gbe_writedata.export
-            reg_diag_tx_seq_ddr_mb_i_address_export                   : out std_logic_vector(1 downto 0);                     --                   reg_diag_tx_seq_ddr_mb_i_address.export
-            reg_diag_tx_seq_ddr_mb_i_clk_export                       : out std_logic;                                        --                       reg_diag_tx_seq_ddr_mb_i_clk.export
-            reg_diag_tx_seq_ddr_mb_i_read_export                      : out std_logic;                                        --                      reg_diag_tx_seq_ddr_mb_i_read.export
-            reg_diag_tx_seq_ddr_mb_i_readdata_export                  : in  std_logic_vector(31 downto 0) := (others => '0'); --                  reg_diag_tx_seq_ddr_mb_i_readdata.export
-            reg_diag_tx_seq_ddr_mb_i_reset_export                     : out std_logic;                                        --                     reg_diag_tx_seq_ddr_mb_i_reset.export
-            reg_diag_tx_seq_ddr_mb_i_write_export                     : out std_logic;                                        --                     reg_diag_tx_seq_ddr_mb_i_write.export
-            reg_diag_tx_seq_ddr_mb_i_writedata_export                 : out std_logic_vector(31 downto 0);                    --                 reg_diag_tx_seq_ddr_mb_i_writedata.export
-            reg_diag_tx_seq_ddr_mb_ii_address_export                  : out std_logic_vector(1 downto 0);                     --                  reg_diag_tx_seq_ddr_mb_ii_address.export
-            reg_diag_tx_seq_ddr_mb_ii_clk_export                      : out std_logic;                                        --                      reg_diag_tx_seq_ddr_mb_ii_clk.export
-            reg_diag_tx_seq_ddr_mb_ii_read_export                     : out std_logic;                                        --                     reg_diag_tx_seq_ddr_mb_ii_read.export
-            reg_diag_tx_seq_ddr_mb_ii_readdata_export                 : in  std_logic_vector(31 downto 0) := (others => '0'); --                 reg_diag_tx_seq_ddr_mb_ii_readdata.export
-            reg_diag_tx_seq_ddr_mb_ii_reset_export                    : out std_logic;                                        --                    reg_diag_tx_seq_ddr_mb_ii_reset.export
-            reg_diag_tx_seq_ddr_mb_ii_write_export                    : out std_logic;                                        --                    reg_diag_tx_seq_ddr_mb_ii_write.export
-            reg_diag_tx_seq_ddr_mb_ii_writedata_export                : out std_logic_vector(31 downto 0);                    --                reg_diag_tx_seq_ddr_mb_ii_writedata.export
-            reg_dpmm_ctrl_address_export                              : out std_logic_vector(0 downto 0);                     --                              reg_dpmm_ctrl_address.export
-            reg_dpmm_ctrl_clk_export                                  : out std_logic;                                        --                                  reg_dpmm_ctrl_clk.export
-            reg_dpmm_ctrl_read_export                                 : out std_logic;                                        --                                 reg_dpmm_ctrl_read.export
-            reg_dpmm_ctrl_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             reg_dpmm_ctrl_readdata.export
-            reg_dpmm_ctrl_reset_export                                : out std_logic;                                        --                                reg_dpmm_ctrl_reset.export
-            reg_dpmm_ctrl_write_export                                : out std_logic;                                        --                                reg_dpmm_ctrl_write.export
-            reg_dpmm_ctrl_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            reg_dpmm_ctrl_writedata.export
-            reg_dpmm_data_address_export                              : out std_logic_vector(0 downto 0);                     --                              reg_dpmm_data_address.export
-            reg_dpmm_data_clk_export                                  : out std_logic;                                        --                                  reg_dpmm_data_clk.export
-            reg_dpmm_data_read_export                                 : out std_logic;                                        --                                 reg_dpmm_data_read.export
-            reg_dpmm_data_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             reg_dpmm_data_readdata.export
-            reg_dpmm_data_reset_export                                : out std_logic;                                        --                                reg_dpmm_data_reset.export
-            reg_dpmm_data_write_export                                : out std_logic;                                        --                                reg_dpmm_data_write.export
-            reg_dpmm_data_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            reg_dpmm_data_writedata.export
-            reg_epcs_address_export                                   : out std_logic_vector(2 downto 0);                     --                                   reg_epcs_address.export
-            reg_epcs_clk_export                                       : out std_logic;                                        --                                       reg_epcs_clk.export
-            reg_epcs_read_export                                      : out std_logic;                                        --                                      reg_epcs_read.export
-            reg_epcs_readdata_export                                  : in  std_logic_vector(31 downto 0) := (others => '0'); --                                  reg_epcs_readdata.export
-            reg_epcs_reset_export                                     : out std_logic;                                        --                                     reg_epcs_reset.export
-            reg_epcs_write_export                                     : out std_logic;                                        --                                     reg_epcs_write.export
-            reg_epcs_writedata_export                                 : out std_logic_vector(31 downto 0);                    --                                 reg_epcs_writedata.export
-            reg_eth10g_back0_address_export                           : out std_logic_vector(5 downto 0);                     --                           reg_eth10g_back0_address.export
-            reg_eth10g_back0_clk_export                               : out std_logic;                                        --                               reg_eth10g_back0_clk.export
-            reg_eth10g_back0_read_export                              : out std_logic;                                        --                              reg_eth10g_back0_read.export
-            reg_eth10g_back0_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => '0'); --                          reg_eth10g_back0_readdata.export
-            reg_eth10g_back0_reset_export                             : out std_logic;                                        --                             reg_eth10g_back0_reset.export
-            reg_eth10g_back0_write_export                             : out std_logic;                                        --                             reg_eth10g_back0_write.export
-            reg_eth10g_back0_writedata_export                         : out std_logic_vector(31 downto 0);                    --                         reg_eth10g_back0_writedata.export
-            reg_eth10g_back1_address_export                           : out std_logic_vector(5 downto 0);                     --                           reg_eth10g_back1_address.export
-            reg_eth10g_back1_clk_export                               : out std_logic;                                        --                               reg_eth10g_back1_clk.export
-            reg_eth10g_back1_read_export                              : out std_logic;                                        --                              reg_eth10g_back1_read.export
-            reg_eth10g_back1_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => '0'); --                          reg_eth10g_back1_readdata.export
-            reg_eth10g_back1_reset_export                             : out std_logic;                                        --                             reg_eth10g_back1_reset.export
-            reg_eth10g_back1_write_export                             : out std_logic;                                        --                             reg_eth10g_back1_write.export
-            reg_eth10g_back1_writedata_export                         : out std_logic_vector(31 downto 0);                    --                         reg_eth10g_back1_writedata.export
-            reg_eth10g_qsfp_ring_address_export                       : out std_logic_vector(6 downto 0);                     --                       reg_eth10g_qsfp_ring_address.export
-            reg_eth10g_qsfp_ring_clk_export                           : out std_logic;                                        --                           reg_eth10g_qsfp_ring_clk.export
-            reg_eth10g_qsfp_ring_read_export                          : out std_logic;                                        --                          reg_eth10g_qsfp_ring_read.export
-            reg_eth10g_qsfp_ring_readdata_export                      : in  std_logic_vector(31 downto 0) := (others => '0'); --                      reg_eth10g_qsfp_ring_readdata.export
-            reg_eth10g_qsfp_ring_reset_export                         : out std_logic;                                        --                         reg_eth10g_qsfp_ring_reset.export
-            reg_eth10g_qsfp_ring_write_export                         : out std_logic;                                        --                         reg_eth10g_qsfp_ring_write.export
-            reg_eth10g_qsfp_ring_writedata_export                     : out std_logic_vector(31 downto 0);                    --                     reg_eth10g_qsfp_ring_writedata.export
-            reg_fpga_temp_sens_address_export                         : out std_logic_vector(2 downto 0);                     --                         reg_fpga_temp_sens_address.export
-            reg_fpga_temp_sens_clk_export                             : out std_logic;                                        --                             reg_fpga_temp_sens_clk.export
-            reg_fpga_temp_sens_read_export                            : out std_logic;                                        --                            reg_fpga_temp_sens_read.export
-            reg_fpga_temp_sens_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => '0'); --                        reg_fpga_temp_sens_readdata.export
-            reg_fpga_temp_sens_reset_export                           : out std_logic;                                        --                           reg_fpga_temp_sens_reset.export
-            reg_fpga_temp_sens_write_export                           : out std_logic;                                        --                           reg_fpga_temp_sens_write.export
-            reg_fpga_temp_sens_writedata_export                       : out std_logic_vector(31 downto 0);                    --                       reg_fpga_temp_sens_writedata.export
-            reg_fpga_voltage_sens_address_export                      : out std_logic_vector(3 downto 0);                     --                      reg_fpga_voltage_sens_address.export
-            reg_fpga_voltage_sens_clk_export                          : out std_logic;                                        --                          reg_fpga_voltage_sens_clk.export
-            reg_fpga_voltage_sens_read_export                         : out std_logic;                                        --                         reg_fpga_voltage_sens_read.export
-            reg_fpga_voltage_sens_readdata_export                     : in  std_logic_vector(31 downto 0) := (others => '0'); --                     reg_fpga_voltage_sens_readdata.export
-            reg_fpga_voltage_sens_reset_export                        : out std_logic;                                        --                        reg_fpga_voltage_sens_reset.export
-            reg_fpga_voltage_sens_write_export                        : out std_logic;                                        --                        reg_fpga_voltage_sens_write.export
-            reg_fpga_voltage_sens_writedata_export                    : out std_logic_vector(31 downto 0);                    --                    reg_fpga_voltage_sens_writedata.export
-            reg_io_ddr_mb_i_address_export                            : out std_logic_vector(15 downto 0);                    --                            reg_io_ddr_mb_i_address.export
-            reg_io_ddr_mb_i_clk_export                                : out std_logic;                                        --                                reg_io_ddr_mb_i_clk.export
-            reg_io_ddr_mb_i_read_export                               : out std_logic;                                        --                               reg_io_ddr_mb_i_read.export
-            reg_io_ddr_mb_i_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => '0'); --                           reg_io_ddr_mb_i_readdata.export
-            reg_io_ddr_mb_i_reset_export                              : out std_logic;                                        --                              reg_io_ddr_mb_i_reset.export
-            reg_io_ddr_mb_i_write_export                              : out std_logic;                                        --                              reg_io_ddr_mb_i_write.export
-            reg_io_ddr_mb_i_writedata_export                          : out std_logic_vector(31 downto 0);                    --                          reg_io_ddr_mb_i_writedata.export
-            reg_io_ddr_mb_ii_address_export                           : out std_logic_vector(15 downto 0);                    --                           reg_io_ddr_mb_ii_address.export
-            reg_io_ddr_mb_ii_clk_export                               : out std_logic;                                        --                               reg_io_ddr_mb_ii_clk.export
-            reg_io_ddr_mb_ii_read_export                              : out std_logic;                                        --                              reg_io_ddr_mb_ii_read.export
-            reg_io_ddr_mb_ii_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => '0'); --                          reg_io_ddr_mb_ii_readdata.export
-            reg_io_ddr_mb_ii_reset_export                             : out std_logic;                                        --                             reg_io_ddr_mb_ii_reset.export
-            reg_io_ddr_mb_ii_write_export                             : out std_logic;                                        --                             reg_io_ddr_mb_ii_write.export
-            reg_io_ddr_mb_ii_writedata_export                         : out std_logic_vector(31 downto 0);                    --                         reg_io_ddr_mb_ii_writedata.export
-            reg_10gbase_r_24_address_export                           : out std_logic_vector(14 downto 0);                    --     reg_10gbase_r_24_address.export
-            reg_10gbase_r_24_clk_export                               : out std_logic;                                        --         reg_10gbase_r_24_clk.export
-            reg_10gbase_r_24_read_export                              : out std_logic;                                        --        reg_10gbase_r_24_read.export
-            reg_10gbase_r_24_readdata_export                          : in  std_logic_vector(31 downto 0) := (others => '0'); --    reg_10gbase_r_24_readdata.export
-            reg_10gbase_r_24_reset_export                             : out std_logic;                                        --       reg_10gbase_r_24_reset.export
-            reg_10gbase_r_24_waitrequest_export                       : in  std_logic                     := '0';             -- reg_10gbase_r_24_waitrequest.export
-            reg_10gbase_r_24_write_export                             : out std_logic;                                        --       reg_10gbase_r_24_write.export
-            reg_10gbase_r_24_writedata_export                         : out std_logic_vector(31 downto 0);                    --   reg_10gbase_r_24_writedata.export
-            reg_mmdp_ctrl_address_export                              : out std_logic_vector(0 downto 0);                     --                              reg_mmdp_ctrl_address.export
-            reg_mmdp_ctrl_clk_export                                  : out std_logic;                                        --                                  reg_mmdp_ctrl_clk.export
-            reg_mmdp_ctrl_read_export                                 : out std_logic;                                        --                                 reg_mmdp_ctrl_read.export
-            reg_mmdp_ctrl_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             reg_mmdp_ctrl_readdata.export
-            reg_mmdp_ctrl_reset_export                                : out std_logic;                                        --                                reg_mmdp_ctrl_reset.export
-            reg_mmdp_ctrl_write_export                                : out std_logic;                                        --                                reg_mmdp_ctrl_write.export
-            reg_mmdp_ctrl_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            reg_mmdp_ctrl_writedata.export
-            reg_mmdp_data_address_export                              : out std_logic_vector(0 downto 0);                     --                              reg_mmdp_data_address.export
-            reg_mmdp_data_clk_export                                  : out std_logic;                                        --                                  reg_mmdp_data_clk.export
-            reg_mmdp_data_read_export                                 : out std_logic;                                        --                                 reg_mmdp_data_read.export
-            reg_mmdp_data_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             reg_mmdp_data_readdata.export
-            reg_mmdp_data_reset_export                                : out std_logic;                                        --                                reg_mmdp_data_reset.export
-            reg_mmdp_data_write_export                                : out std_logic;                                        --                                reg_mmdp_data_write.export
-            reg_mmdp_data_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            reg_mmdp_data_writedata.export
-            reg_remu_address_export                                   : out std_logic_vector(2 downto 0);                     --                                   reg_remu_address.export
-            reg_remu_clk_export                                       : out std_logic;                                        --                                       reg_remu_clk.export
-            reg_remu_read_export                                      : out std_logic;                                        --                                      reg_remu_read.export
-            reg_remu_readdata_export                                  : in  std_logic_vector(31 downto 0) := (others => '0'); --                                  reg_remu_readdata.export
-            reg_remu_reset_export                                     : out std_logic;                                        --                                     reg_remu_reset.export
-            reg_remu_write_export                                     : out std_logic;                                        --                                     reg_remu_write.export
-            reg_remu_writedata_export                                 : out std_logic_vector(31 downto 0);                    --                                 reg_remu_writedata.export
-            reg_tr_10gbe_back0_address_export                         : out std_logic_vector(17 downto 0);                    --                         reg_tr_10gbe_back0_address.export
-            reg_tr_10gbe_back0_clk_export                             : out std_logic;                                        --                             reg_tr_10gbe_back0_clk.export
-            reg_tr_10gbe_back0_read_export                            : out std_logic;                                        --                            reg_tr_10gbe_back0_read.export
-            reg_tr_10gbe_back0_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => '0'); --                        reg_tr_10gbe_back0_readdata.export
-            reg_tr_10gbe_back0_reset_export                           : out std_logic;                                        --                           reg_tr_10gbe_back0_reset.export
-            reg_tr_10gbe_back0_waitrequest_export                     : in  std_logic                     := '0';             --                     reg_tr_10gbe_back0_waitrequest.export
-            reg_tr_10gbe_back0_write_export                           : out std_logic;                                        --                           reg_tr_10gbe_back0_write.export
-            reg_tr_10gbe_back0_writedata_export                       : out std_logic_vector(31 downto 0);                    --                       reg_tr_10gbe_back0_writedata.export
-            reg_tr_10gbe_back1_address_export                         : out std_logic_vector(17 downto 0);                    --                         reg_tr_10gbe_back1_address.export
-            reg_tr_10gbe_back1_clk_export                             : out std_logic;                                        --                             reg_tr_10gbe_back1_clk.export
-            reg_tr_10gbe_back1_read_export                            : out std_logic;                                        --                            reg_tr_10gbe_back1_read.export
-            reg_tr_10gbe_back1_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => '0'); --                        reg_tr_10gbe_back1_readdata.export
-            reg_tr_10gbe_back1_reset_export                           : out std_logic;                                        --                           reg_tr_10gbe_back1_reset.export
-            reg_tr_10gbe_back1_waitrequest_export                     : in  std_logic                     := '0';             --                     reg_tr_10gbe_back1_waitrequest.export
-            reg_tr_10gbe_back1_write_export                           : out std_logic;                                        --                           reg_tr_10gbe_back1_write.export
-            reg_tr_10gbe_back1_writedata_export                       : out std_logic_vector(31 downto 0);                    --                       reg_tr_10gbe_back1_writedata.export
-            reg_tr_10gbe_qsfp_ring_address_export                     : out std_logic_vector(18 downto 0);                    --                     reg_tr_10gbe_qsfp_ring_address.export
-            reg_tr_10gbe_qsfp_ring_clk_export                         : out std_logic;                                        --                         reg_tr_10gbe_qsfp_ring_clk.export
-            reg_tr_10gbe_qsfp_ring_read_export                        : out std_logic;                                        --                        reg_tr_10gbe_qsfp_ring_read.export
-            reg_tr_10gbe_qsfp_ring_readdata_export                    : in  std_logic_vector(31 downto 0) := (others => '0'); --                    reg_tr_10gbe_qsfp_ring_readdata.export
-            reg_tr_10gbe_qsfp_ring_reset_export                       : out std_logic;                                        --                       reg_tr_10gbe_qsfp_ring_reset.export
-            reg_tr_10gbe_qsfp_ring_waitrequest_export                 : in  std_logic                     := '0';             --                 reg_tr_10gbe_qsfp_ring_waitrequest.export
-            reg_tr_10gbe_qsfp_ring_write_export                       : out std_logic;                                        --                       reg_tr_10gbe_qsfp_ring_write.export
-            reg_tr_10gbe_qsfp_ring_writedata_export                   : out std_logic_vector(31 downto 0);                    --                   reg_tr_10gbe_qsfp_ring_writedata.export
-            reg_unb_pmbus_address_export                              : out std_logic_vector(5 downto 0);                     --                              reg_unb_pmbus_address.export
-            reg_unb_pmbus_clk_export                                  : out std_logic;                                        --                                  reg_unb_pmbus_clk.export
-            reg_unb_pmbus_read_export                                 : out std_logic;                                        --                                 reg_unb_pmbus_read.export
-            reg_unb_pmbus_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => '0'); --                             reg_unb_pmbus_readdata.export
-            reg_unb_pmbus_reset_export                                : out std_logic;                                        --                                reg_unb_pmbus_reset.export
-            reg_unb_pmbus_write_export                                : out std_logic;                                        --                                reg_unb_pmbus_write.export
-            reg_unb_pmbus_writedata_export                            : out std_logic_vector(31 downto 0);                    --                            reg_unb_pmbus_writedata.export
-            reg_unb_sens_address_export                               : out std_logic_vector(5 downto 0);                     --                               reg_unb_sens_address.export
-            reg_unb_sens_clk_export                                   : out std_logic;                                        --                                   reg_unb_sens_clk.export
-            reg_unb_sens_read_export                                  : out std_logic;                                        --                                  reg_unb_sens_read.export
-            reg_unb_sens_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => '0'); --                              reg_unb_sens_readdata.export
-            reg_unb_sens_reset_export                                 : out std_logic;                                        --                                 reg_unb_sens_reset.export
-            reg_unb_sens_write_export                                 : out std_logic;                                        --                                 reg_unb_sens_write.export
-            reg_unb_sens_writedata_export                             : out std_logic_vector(31 downto 0);                    --                             reg_unb_sens_writedata.export
-            reg_wdi_address_export                                    : out std_logic_vector(0 downto 0);                     --                                    reg_wdi_address.export
-            reg_wdi_clk_export                                        : out std_logic;                                        --                                        reg_wdi_clk.export
-            reg_wdi_read_export                                       : out std_logic;                                        --                                       reg_wdi_read.export
-            reg_wdi_readdata_export                                   : in  std_logic_vector(31 downto 0) := (others => '0'); --                                   reg_wdi_readdata.export
-            reg_wdi_reset_export                                      : out std_logic;                                        --                                      reg_wdi_reset.export
-            reg_wdi_write_export                                      : out std_logic;                                        --                                      reg_wdi_write.export
-            reg_wdi_writedata_export                                  : out std_logic_vector(31 downto 0);                    --                                  reg_wdi_writedata.export
-            reset_reset_n                                             : in  std_logic                     := '0';             --                                              reset.reset_n
-            rom_system_info_address_export                            : out std_logic_vector(9 downto 0);                     --                            rom_system_info_address.export
-            rom_system_info_clk_export                                : out std_logic;                                        --                                rom_system_info_clk.export
-            rom_system_info_read_export                               : out std_logic;                                        --                               rom_system_info_read.export
-            rom_system_info_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => '0'); --                           rom_system_info_readdata.export
-            rom_system_info_reset_export                              : out std_logic;                                        --                              rom_system_info_reset.export
-            rom_system_info_write_export                              : out std_logic;                                        --                              rom_system_info_write.export
-            rom_system_info_writedata_export                          : out std_logic_vector(31 downto 0)                     --                          rom_system_info_writedata.export
+        port (
+            avs_eth_0_clk_export                                         : out std_logic;                                        -- export
+            avs_eth_0_irq_export                                         : in  std_logic                     := 'X';             -- export
+            avs_eth_0_ram_address_export                                 : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_ram_read_export                                    : out std_logic;                                        -- export
+            avs_eth_0_ram_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_ram_write_export                                   : out std_logic;                                        -- export
+            avs_eth_0_ram_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reg_address_export                                 : out std_logic_vector(3 downto 0);                     -- export
+            avs_eth_0_reg_read_export                                    : out std_logic;                                        -- export
+            avs_eth_0_reg_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_reg_write_export                                   : out std_logic;                                        -- export
+            avs_eth_0_reg_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            avs_eth_0_reset_export                                       : out std_logic;                                        -- export
+            avs_eth_0_tse_address_export                                 : out std_logic_vector(9 downto 0);                     -- export
+            avs_eth_0_tse_read_export                                    : out std_logic;                                        -- export
+            avs_eth_0_tse_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            avs_eth_0_tse_waitrequest_export                             : in  std_logic                     := 'X';             -- export
+            avs_eth_0_tse_write_export                                   : out std_logic;                                        -- export
+            avs_eth_0_tse_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            clk_clk                                                      : in  std_logic                     := 'X';             -- clk
+            jesd204b_address_export                                       : out std_logic_vector(11 downto 0);                     -- export
+            jesd204b_clk_export                                           : out std_logic;                                        -- export
+            jesd204b_read_export                                          : out std_logic;                                        -- export
+            jesd204b_readdata_export                                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            jesd204b_reset_export                                         : out std_logic;                                        -- export
+            jesd204b_write_export                                         : out std_logic;                                        -- export
+            jesd204b_writedata_export                                     : out std_logic_vector(31 downto 0);                    -- export
+            pio_pps_address_export                                       : out std_logic_vector(0 downto 0);                     -- export
+            pio_pps_clk_export                                           : out std_logic;                                        -- export
+            pio_pps_read_export                                          : out std_logic;                                        -- export
+            pio_pps_readdata_export                                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_pps_reset_export                                         : out std_logic;                                        -- export
+            pio_pps_write_export                                         : out std_logic;                                        -- export
+            pio_pps_writedata_export                                     : out std_logic_vector(31 downto 0);                    -- export
+            pio_system_info_address_export                               : out std_logic_vector(4 downto 0);                     -- export
+            pio_system_info_clk_export                                   : out std_logic;                                        -- export
+            pio_system_info_read_export                                  : out std_logic;                                        -- export
+            pio_system_info_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            pio_system_info_reset_export                                 : out std_logic;                                        -- export
+            pio_system_info_write_export                                 : out std_logic;                                        -- export
+            pio_system_info_writedata_export                             : out std_logic_vector(31 downto 0);                    -- export
+            pio_wdi_external_connection_export                           : out std_logic;                                        -- export
+            reg_dpmm_ctrl_address_export                                 : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_ctrl_clk_export                                     : out std_logic;                                        -- export
+            reg_dpmm_ctrl_read_export                                    : out std_logic;                                        -- export
+            reg_dpmm_ctrl_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_ctrl_reset_export                                   : out std_logic;                                        -- export
+            reg_dpmm_ctrl_write_export                                   : out std_logic;                                        -- export
+            reg_dpmm_ctrl_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            reg_dpmm_data_address_export                                 : out std_logic_vector(0 downto 0);                     -- export
+            reg_dpmm_data_clk_export                                     : out std_logic;                                        -- export
+            reg_dpmm_data_read_export                                    : out std_logic;                                        -- export
+            reg_dpmm_data_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_dpmm_data_reset_export                                   : out std_logic;                                        -- export
+            reg_dpmm_data_write_export                                   : out std_logic;                                        -- export
+            reg_dpmm_data_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            reg_epcs_address_export                                      : out std_logic_vector(2 downto 0);                     -- export
+            reg_epcs_clk_export                                          : out std_logic;                                        -- export
+            reg_epcs_read_export                                         : out std_logic;                                        -- export
+            reg_epcs_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_epcs_reset_export                                        : out std_logic;                                        -- export
+            reg_epcs_write_export                                        : out std_logic;                                        -- export
+            reg_epcs_writedata_export                                    : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_temp_sens_address_export                            : out std_logic_vector(2 downto 0);                     -- export
+            reg_fpga_temp_sens_clk_export                                : out std_logic;                                        -- export
+            reg_fpga_temp_sens_read_export                               : out std_logic;                                        -- export
+            reg_fpga_temp_sens_readdata_export                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_temp_sens_reset_export                              : out std_logic;                                        -- export
+            reg_fpga_temp_sens_write_export                              : out std_logic;                                        -- export
+            reg_fpga_temp_sens_writedata_export                          : out std_logic_vector(31 downto 0);                    -- export
+            reg_fpga_voltage_sens_address_export                         : out std_logic_vector(3 downto 0);                     -- export
+            reg_fpga_voltage_sens_clk_export                             : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_read_export                            : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_fpga_voltage_sens_reset_export                           : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_write_export                           : out std_logic;                                        -- export
+            reg_fpga_voltage_sens_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_ctrl_address_export                                 : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_ctrl_clk_export                                     : out std_logic;                                        -- export
+            reg_mmdp_ctrl_read_export                                    : out std_logic;                                        -- export
+            reg_mmdp_ctrl_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_ctrl_reset_export                                   : out std_logic;                                        -- export
+            reg_mmdp_ctrl_write_export                                   : out std_logic;                                        -- export
+            reg_mmdp_ctrl_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            reg_mmdp_data_address_export                                 : out std_logic_vector(0 downto 0);                     -- export
+            reg_mmdp_data_clk_export                                     : out std_logic;                                        -- export
+            reg_mmdp_data_read_export                                    : out std_logic;                                        -- export
+            reg_mmdp_data_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_mmdp_data_reset_export                                   : out std_logic;                                        -- export
+            reg_mmdp_data_write_export                                   : out std_logic;                                        -- export
+            reg_mmdp_data_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            reg_remu_address_export                                      : out std_logic_vector(2 downto 0);                     -- export
+            reg_remu_clk_export                                          : out std_logic;                                        -- export
+            reg_remu_read_export                                         : out std_logic;                                        -- export
+            reg_remu_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_remu_reset_export                                        : out std_logic;                                        -- export
+            reg_remu_write_export                                        : out std_logic;                                        -- export
+            reg_remu_writedata_export                                    : out std_logic_vector(31 downto 0);                    -- export
+            reg_unb_pmbus_address_export                                 : out std_logic_vector(5 downto 0);                     -- export
+            reg_unb_pmbus_clk_export                                     : out std_logic;                                        -- export
+            reg_unb_pmbus_read_export                                    : out std_logic;                                        -- export
+            reg_unb_pmbus_readdata_export                                : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_unb_pmbus_reset_export                                   : out std_logic;                                        -- export
+            reg_unb_pmbus_write_export                                   : out std_logic;                                        -- export
+            reg_unb_pmbus_writedata_export                               : out std_logic_vector(31 downto 0);                    -- export
+            reg_unb_sens_address_export                                  : out std_logic_vector(5 downto 0);                     -- export
+            reg_unb_sens_clk_export                                      : out std_logic;                                        -- export
+            reg_unb_sens_read_export                                     : out std_logic;                                        -- export
+            reg_unb_sens_readdata_export                                 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_unb_sens_reset_export                                    : out std_logic;                                        -- export
+            reg_unb_sens_write_export                                    : out std_logic;                                        -- export
+            reg_unb_sens_writedata_export                                : out std_logic_vector(31 downto 0);                    -- export
+            reg_wdi_address_export                                       : out std_logic_vector(0 downto 0);                     -- export
+            reg_wdi_clk_export                                           : out std_logic;                                        -- export
+            reg_wdi_read_export                                          : out std_logic;                                        -- export
+            reg_wdi_readdata_export                                      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_wdi_reset_export                                         : out std_logic;                                        -- export
+            reg_wdi_write_export                                         : out std_logic;                                        -- export
+            reg_wdi_writedata_export                                     : out std_logic_vector(31 downto 0);                    -- export
+            reset_reset_n                                                : in  std_logic                     := 'X';             -- reset_n
+            rom_system_info_address_export                               : out std_logic_vector(9 downto 0);                     -- export
+            rom_system_info_clk_export                                   : out std_logic;                                        -- export
+            rom_system_info_read_export                                  : out std_logic;                                        -- export
+            rom_system_info_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            rom_system_info_reset_export                                 : out std_logic;                                        -- export
+            rom_system_info_write_export                                 : out std_logic;                                        -- export
+            rom_system_info_writedata_export                             : out std_logic_vector(31 downto 0);                     -- export
+            ram_diag_data_buf_jesd_address_export                        : out std_logic_vector(16 downto 0);                    -- export
+            ram_diag_data_buf_jesd_clk_export                            : out std_logic;                                        -- export
+            ram_diag_data_buf_jesd_read_export                           : out std_logic;                                        -- export
+            ram_diag_data_buf_jesd_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_diag_data_buf_jesd_reset_export                          : out std_logic;                                        -- export
+            ram_diag_data_buf_jesd_write_export                          : out std_logic;                                        -- export
+            ram_diag_data_buf_jesd_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
+            reg_diag_data_buf_jesd_address_export                        : out std_logic_vector(11 downto 0);                     -- export
+            reg_diag_data_buf_jesd_clk_export                            : out std_logic;                                        -- export
+            reg_diag_data_buf_jesd_read_export                           : out std_logic;                                        -- export
+            reg_diag_data_buf_jesd_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_diag_data_buf_jesd_reset_export                          : out std_logic;                                        -- export
+            reg_diag_data_buf_jesd_write_export                          : out std_logic;                                        -- export
+            reg_diag_data_buf_jesd_writedata_export                      : out std_logic_vector(31 downto 0)                    -- export
         );
     end component qsys_lofar2_unb2b_adc;
 
-
- 
-END qsys_unb2b_test_pkg;
+END qsys_lofar2_unb2b_adc_pkg;
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..566beaf9a88a8c014e5a138be5d3e6e8077ec04d
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -0,0 +1,169 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2018
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Jonathan Hargreaves
+-- Purpose: Tb to show that lofar2_unb2b_adc can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_adc IS
+END tb_lofar2_unb2b_adc;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_adc IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL bck_rx              : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL bck_ref_clk         : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc : ENTITY work.lofar2_unb2b_adc
+  GENERIC MAP (
+    g_design_name => "lofar2_unb2b_adc_one_node",
+    g_design_note => "Lofar2 adc with one node",
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    BCK_RX       => bck_rx,
+    BCK_REF_CLK  => bck_ref_clk,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC   => jesd204b_sync
+  );
+
+
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;
\ No newline at end of file
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index 53069eb29e865d0d4bba87ca25619bd48301323b..99aca90528b2287445406f1267e44fc964554869 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -55,7 +55,7 @@ ENTITY unb2b_board_system_info_reg IS
     g_design_name : STRING;
     g_stamp_date  : NATURAL := 0;
     g_stamp_time  : NATURAL := 0;
-    g_stamp_svn   : NATURAL := 0;
+    g_revision_id : STRING  := "";
     g_design_note : STRING
   );
   PORT (
@@ -77,9 +77,18 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
   CONSTANT c_nof_fixed_regs       : NATURAL := 2;  -- info, use_phy
   CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
   CONSTANT c_nof_stamp_regs       : NATURAL := 3;  -- date, time, svn rev
+  CONSTANT c_nof_revision_id_regs : NATURAL := 3;  -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
   CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
 
-  CONSTANT c_nof_regs             : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
+  CONSTANT c_info_reg             : NATURAL := 0;
+  CONSTANT c_use_phy_reg          : NATURAL := 1;
+  CONSTANT c_design_name_offset   : NATURAL := c_nof_fixed_regs;
+  CONSTANT c_stamp_date_offset    : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs;
+  CONSTANT c_stamp_time_offset    : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
+  CONSTANT c_revision_id_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
+  CONSTANT c_design_note_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
+
+  CONSTANT c_nof_regs             : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
 
   CONSTANT c_mm_reg        : t_c_mem := (latency  => 1,
                                          adr_w    => ceil_log2(c_nof_regs),
@@ -90,8 +99,9 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
   CONSTANT c_use_phy_w     : NATURAL := 8;
   CONSTANT c_use_phy       : STD_LOGIC_VECTOR(c_use_phy_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Unused but keep for compatibillity
 
-  CONSTANT c_design_name    : t_slv_32_arr(0 TO c_nof_design_name_regs-1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
-  CONSTANT c_design_note    : t_slv_32_arr(0 TO c_nof_design_note_regs-1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
+  CONSTANT c_design_name : t_slv_32_arr(0 TO c_nof_design_name_regs-1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
+  CONSTANT c_revision_id : t_slv_32_arr(0 TO c_nof_revision_id_regs-1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
+  CONSTANT c_design_note : t_slv_32_arr(0 TO c_nof_design_note_regs-1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
  
 BEGIN
 
@@ -111,27 +121,29 @@ BEGIN
         sla_out.rdval <= '1';               -- c_mm_reg.latency = 1
 
         vA := TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0));
-        IF vA = 0 THEN         
+        IF vA = c_info_reg THEN         
           sla_out.rddata(c_word_w-1 DOWNTO 0) <= info;
           -- Use bit 11 to indicate that we're using the MM bus (not the info SLV).
           -- Using the MM bus enables user to also read use_phy, design_name etc.
           sla_out.rddata(11) <= '1';
-        ELSIF vA = 1 THEN  
+
+        ELSIF vA = c_use_phy_reg THEN
           sla_out.rddata(c_use_phy_w-1 DOWNTO 0) <= c_use_phy;
-        ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs THEN      
-          sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_name(vA-c_nof_fixed_regs);
 
-        ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs THEN      
+        ELSIF vA < c_design_name_offset + c_nof_design_name_regs THEN
+          sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_name(vA - c_design_name_offset);
+
+        ELSIF vA = c_stamp_date_offset THEN
           sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_date, c_word_w);
 
-        ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs+1 THEN      
+        ELSIF vA = c_stamp_time_offset THEN
           sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_time, c_word_w);
 
-        ELSIF vA = c_nof_fixed_regs + c_nof_design_name_regs+2 THEN      
-          sla_out.rddata(c_word_w-1 DOWNTO 0) <= TO_UVEC(g_stamp_svn, c_word_w);
+        ELSIF vA < c_revision_id_offset + c_nof_revision_id_regs THEN
+          sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_revision_id(vA - c_revision_id_offset);
 
-        ELSIF vA < c_nof_fixed_regs + c_nof_design_name_regs+c_nof_stamp_regs+c_nof_design_note_regs THEN      
-          sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_note(vA-c_nof_fixed_regs-c_nof_design_name_regs-c_nof_stamp_regs);
+        ELSIF vA < c_design_note_offset + c_nof_design_note_regs THEN
+          sla_out.rddata(c_word_w-1 DOWNTO 0) <= c_design_note(vA - c_design_note_offset);
 
         END IF;
 
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 34b69bb9152dd49966f73533bc684efe27e9b389..d15109d12086a6ec22c61adabc10974a00aff947 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -88,7 +88,8 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
   CONSTANT c_revision_id_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
   CONSTANT c_design_note_offset   : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
 
-  CONSTANT c_nof_regs      : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+  CONSTANT c_nof_regs             : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+
   CONSTANT c_mm_reg        : t_c_mem := (latency  => 1,
                                          adr_w    => ceil_log2(c_nof_regs),
                                          dat_w    => c_word_w,       -- Use MM bus data width = c_word_w = 32 for all MM registers
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index 970529be4267e1d121cd77c32cbca7ff8485c82c..fddc99e9c4871d33aa29a5f3d6e20bec8bca5a54 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = ddr3
 hdl_library_clause_name = ddr3_lib
 hdl_lib_uses_synth = common dp diag diagnostics ss tech_ddr 
 hdl_lib_uses_sim = 
-hdl_lib_technology =
+hdl_lib_technology = ip_stratixiv
 
 synth_files =
     src/vhdl/ddr3_pkg.vhd
diff --git a/libraries/io/tr_xaui/hdllib.cfg b/libraries/io/tr_xaui/hdllib.cfg
index a09ac0f8d4e2c4c7cb14ea4b69bd5eb2d698567d..6a48778fd9356a579d461b2659c1797fb6258076 100644
--- a/libraries/io/tr_xaui/hdllib.cfg
+++ b/libraries/io/tr_xaui/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = tr_xaui
 hdl_library_clause_name = tr_xaui_lib
 hdl_lib_uses_synth = common dp mdio diagnostics tech_xaui
 hdl_lib_uses_sim = 
-hdl_lib_technology = 
+hdl_lib_technology = ip_stratixiv
 
 synth_files =
     src/vhdl/tr_xaui_deframer.vhd
diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 9b6302cee07394995810edc824cda4cfd3f5e6b7..4efc3d6cbb312445443778922aad88cab0ec13e8 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -41,7 +41,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_transceiver_reset_controller_12  ip_arria10_e3sge3_transceiver_reset_controller_12_altera_xcvr_reset_control_151
     ip_arria10_e3sge3_transceiver_reset_controller_24  ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
     ip_arria10_e3sge3_transceiver_reset_controller_48  ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
-    ip_arria10_e1sg_phy_10gbase_r                      ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
+    ip_arria10_e1sg_phy_10gbase_r                      ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180
     ip_arria10_e1sg_phy_10gbase_r_3                    ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180
     ip_arria10_e1sg_phy_10gbase_r_4                    ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180
     ip_arria10_e1sg_phy_10gbase_r_12                   ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180
@@ -53,7 +53,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e1sg_transceiver_reset_controller_4     ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
     ip_arria10_e1sg_transceiver_reset_controller_12    ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
     ip_arria10_e2sg_transceiver_reset_controller_24    ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
-    ip_arria10_e2sg_phy_10gbase_r                      ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
+    ip_arria10_e2sg_phy_10gbase_r                      ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_194
     ip_arria10_e2sg_phy_10gbase_r_3                    ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_194
     ip_arria10_e2sg_phy_10gbase_r_4                    ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_194
     ip_arria10_e2sg_phy_10gbase_r_12                   ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_194
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
index a48d4bc6571fcd72b8f853beb2c1c5399d04c811..04ece135be96de03f6cd5855bd22dd7ce4e2b196 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
@@ -21,18 +21,18 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_180;
-LIBRARY ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180;
-LIBRARY ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194;
+LIBRARY ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_194;
 
 LIBRARY IEEE, tech_pll_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index a409789620ceb0978bc10892db447ee3db5ff0ba..efdfb2b45b5611d1f0c5f791ff867c06114cc106 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
 LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
 LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
-LIBRARY ip_arria10_esg_voltage_sense_altera_voltage_sense_180;
+LIBRARY ip_arria10_e2sg_voltage_sense_altera_voltage_sense_194;
 
 
 ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 75f4327b521ad800ab918dd52288848376c97c12..fa5d74a806b9b8cc328b7481a8d747d0c8de2ad4 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -27,7 +27,8 @@
 --   
 --  
 
-LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx, ip_arria10_e1sg_jesd204b_rx_reset_seq, ip_arria10_e1sg_jesd204b_rx_core_pll, ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
+--LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx, ip_arria10_e1sg_jesd204b_rx_reset_seq, ip_arria10_e1sg_jesd204b_rx_core_pll, ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE common_lib.common_pkg.ALL;
@@ -157,7 +158,58 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
 --    );
 --  end component ip_arria10_e1sg_jesd204b_rx;
 
-  component ip_arria10_e1sg_jesd204b_rx_core_pll_cmp is
+    component ip_arria10_e1sg_jesd204b_rx is
+    port (
+      alldev_lane_aligned        : in  std_logic                     := 'X';             -- export
+      csr_cf                     : out std_logic_vector(4 downto 0);                     -- export
+      csr_cs                     : out std_logic_vector(1 downto 0);                     -- export
+      csr_f                      : out std_logic_vector(7 downto 0);                     -- export
+      csr_hd                     : out std_logic;                                        -- export
+      csr_k                      : out std_logic_vector(4 downto 0);                     -- export
+      csr_l                      : out std_logic_vector(4 downto 0);                     -- export
+      csr_lane_powerdown         : out std_logic_vector(0 downto 0);                     -- export
+      csr_m                      : out std_logic_vector(7 downto 0);                     -- export
+      csr_n                      : out std_logic_vector(4 downto 0);                     -- export
+      csr_np                     : out std_logic_vector(4 downto 0);                     -- export
+      csr_rx_testmode            : out std_logic_vector(3 downto 0);                     -- export
+      csr_s                      : out std_logic_vector(4 downto 0);                     -- export
+      dev_lane_aligned           : out std_logic;                                        -- export
+      dev_sync_n                 : out std_logic;                                        -- export
+      jesd204_rx_avs_chipselect  : in  std_logic                     := 'X';             -- chipselect
+      jesd204_rx_avs_address     : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- address
+      jesd204_rx_avs_read        : in  std_logic                     := 'X';             -- read
+      jesd204_rx_avs_readdata    : out std_logic_vector(31 downto 0);                    -- readdata
+      jesd204_rx_avs_waitrequest : out std_logic;                                        -- waitrequest
+      jesd204_rx_avs_write       : in  std_logic                     := 'X';             -- write
+      jesd204_rx_avs_writedata   : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+      jesd204_rx_avs_clk         : in  std_logic                     := 'X';             -- clk
+      jesd204_rx_avs_rst_n       : in  std_logic                     := 'X';             -- reset_n
+      jesd204_rx_dlb_data        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+      jesd204_rx_dlb_data_valid  : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_dlb_disperr     : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_dlb_errdetect   : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_dlb_kchar_data  : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- export
+      jesd204_rx_frame_error     : in  std_logic                     := 'X';             -- export
+      jesd204_rx_int                : out std_logic;                                        -- irq
+      jesd204_rx_link_data              : out std_logic_vector(31 downto 0);                    -- data
+      jesd204_rx_link_valid             : out std_logic;                                        -- valid
+      jesd204_rx_link_ready             : in  std_logic                     := 'X';             -- ready
+      pll_ref_clk                   : in  std_logic                     := 'X';             -- clk
+      rx_analogreset             : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_analogreset
+      rx_cal_busy                : out std_logic_vector(0 downto 0);                     -- rx_cal_busy
+      rx_digitalreset            : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_digitalreset
+      rx_islockedtodata          : out std_logic_vector(0 downto 0);                     -- rx_is_lockedtodata
+      rx_serial_data             : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- rx_serial_data
+      rxlink_clk                 : in  std_logic                     := 'X';             -- clk
+      rxlink_rst_n_reset_n              : in  std_logic                     := 'X';             -- reset_n
+      rxphy_clk                  : out std_logic_vector(0 downto 0);                     -- export
+      sof                        : out std_logic_vector(3 downto 0);                     -- export
+      somf                       : out std_logic_vector(3 downto 0);                     -- export
+      sysref                     : in  std_logic                     := 'X'              -- export
+    );
+  end component ip_arria10_e1sg_jesd204b_rx;
+
+  component ip_arria10_e1sg_jesd204b_rx_core_pll is
     port (
       locked   : out std_logic;        -- export
       outclk_0 : out std_logic;        -- clk
@@ -165,9 +217,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       refclk   : in  std_logic := 'X'; -- clk
       rst      : in  std_logic := 'X'  -- reset
     );
-  end component ip_arria10_e1sg_jesd204b_rx_core_pll_cmp;
+  end component ip_arria10_e1sg_jesd204b_rx_core_pll;
 
-  component ip_arria10_e1sg_jesd204b_rx_reset_seq_cmp is
+  component ip_arria10_e1sg_jesd204b_rx_reset_seq is
     generic (
       NUM_OUTPUTS                   : integer := 3;
       ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
@@ -247,9 +299,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       reset_out6       : out std_logic;                                        -- reset
       reset_out7       : out std_logic                                         -- reset
     );
-  end component ip_arria10_e1sg_jesd204b_rx_reset_seq_cmp;
+  end component ip_arria10_e1sg_jesd204b_rx_reset_seq;
 
-  component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12_cmp is
+  component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12 is
     port (
       clock              : in  std_logic                     := 'X';             -- clk
       reset              : in  std_logic                     := 'X';             -- reset
@@ -259,7 +311,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
       rx_is_lockedtodata : in  std_logic_vector(11 downto 0) := (others => 'X'); -- rx_is_lockedtodata
       rx_ready           : out std_logic_vector(11 downto 0)                     -- rx_ready
     );
-  end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12_cmp;
+  end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
 
 
 
@@ -324,7 +376,7 @@ BEGIN
 --        sysref_export                     => jesd204b_sysref
 --      );
 
-    u_ip_arria10_e1sg_jesd204b_rx : ENTITY ip_arria10_e1sg_jesd204b_rx.ip_arria10_e1sg_jesd204b_rx
+    u_ip_arria10_e1sg_jesd204b_rx : ip_arria10_e1sg_jesd204b_rx
       PORT MAP 
       (
         alldev_lane_aligned        => dev_lane_aligned_arr(i),
@@ -378,7 +430,7 @@ BEGIN
       -----------------------------------------------------------------------------
       -- Reset sequencer for each channel
       -----------------------------------------------------------------------------
-      u_ip_arria10_e1sg_jesd204b_rx_reset_seq : ENTITY ip_arria10_e1sg_jesd204b_rx_reset_seq.ip_arria10_e1sg_jesd204b_rx_reset_seq
+      u_ip_arria10_e1sg_jesd204b_rx_reset_seq : ip_arria10_e1sg_jesd204b_rx_reset_seq
       PORT MAP (
         av_address                 => reset_seq_mosi_arr(i).address(7 downto 0), -- in  std_logic_vector(7 downto 0)  := (others => '0'); 
         av_readdata                => reset_seq_miso_arr(i).rddata(31 downto 0),
@@ -438,7 +490,7 @@ BEGIN
     END GENERATE;  
   
     -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
-    u_ip_arria10_e1sg_jesd204b_rx_corepll : ENTITY ip_arria10_e1sg_jesd204b_rx_core_pll.ip_arria10_e1sg_jesd204b_rx_core_pll
+    u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll
     PORT MAP (
       locked                      => core_pll_locked,
       outclk_0                    => rxlink_clk,
@@ -462,7 +514,7 @@ BEGIN
     -- Transceiver reset controller. Use g_nof_channels out of 12 channels. Receive only
     -- Clock set to 100MHz (use mm_clk)
 
-    u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ENTITY ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
+    u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
     PORT MAP (
       clock                        => mm_clk,
       reset                        => xcvr_rst_arr(0),        -- From Reset Sequencer output1 as per example design
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
index 132a96bf48e9042ff866aac9261f6dcfbd2cfb80..c6a1565701b05eef47338a34f10cc5f3c2372449 100644
--- a/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_clkbuf_global 
-hdl_library_clause_name = ip_arria10_e2sg_clkbuf_global_altclkctrl_180
+hdl_library_clause_name = ip_arria10_e2sg_clkbuf_global_altclkctrl_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim =  ip_arria10_e2sg_altclkctrl_180
+hdl_lib_uses_sim =  ip_arria10_e2sg_altclkctrl_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
index c3522eac8615ad4fa5f72cec6cfa111a5668f7d5..61d54b2f635210f0c61b01cca8c32de0c4ac32c7 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
@@ -30,6 +30,6 @@
 
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
-vmap altmult_complex_180 ./work/
-  vlog "$IP_DIR/../altmult_complex_180/synth/ip_arria10_e2sg_complex_mult_altmult_complex_180_nkpx3mi.v" -work altmult_complex_180
+vmap altmult_complex_194 ./work/
+  vlog "$IP_DIR/../altmult_complex_194/synth/ip_arria10_e2sg_complex_mult_altmult_complex_194_nkpx3mi.v" -work altmult_complex_194
   #vlog "$IP_DIR/ip_arria10_e2sg_complex_mult_bb.v"                                                        
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
index 5fe17d7cf2d9b78a2c21fc94f9a5f9e1e99a9b31..1e148136baef78b400ac816c5fa769b68d14df72 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
@@ -1,5 +1,5 @@
 hdl_lib_name = ip_arria10_e2sg_complex_mult
-hdl_library_clause_name = ip_arria10_e2sg_complex_mult_altmult_complex_180
+hdl_library_clause_name = ip_arria10_e2sg_complex_mult_altmult_complex_194
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim =  
 hdl_lib_technology = ip_arria10_e2sg
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
index 9dc7dea90223fbe552033843df38ead3707ef6c7..b5362e8f2e5384fa6c54946570c062d41c1494b6 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
@@ -37,24 +37,24 @@ if {$IPMODEL=="PHY"} {
     set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_in_1/sim"
         
     #vlib ./work/         ;# Assume library work already exists
-    vmap ip_arria10_ddio_in_1_altera_gpio_core_180  ./work/
-    vmap ip_arria10_ddio_in_1_altera_gpio_180       ./work/
+    vmap ip_arria10_ddio_in_1_altera_gpio_core_194  ./work/
+    vmap ip_arria10_ddio_in_1_altera_gpio_194       ./work/
     
-    vlog -sv "$IP_DIR/../altera_gpio_core_180/sim/mentor/altera_gpio.sv"                        -work ip_arria10_ddio_in_1_altera_gpio_core_180
+    vlog -sv "$IP_DIR/../altera_gpio_core_194/sim/mentor/altera_gpio.sv"                        -work ip_arria10_ddio_in_1_altera_gpio_core_194
     
-    vcom     "$IP_DIR/../altera_gpio_180/sim/ip_arria10_ddio_in_1_altera_gpio_180_umwov7y.vhd"  -work ip_arria10_ddio_in_1_altera_gpio_180     
+    vcom     "$IP_DIR/../altera_gpio_194/sim/ip_arria10_ddio_in_1_altera_gpio_194_umwov7y.vhd"  -work ip_arria10_ddio_in_1_altera_gpio_194     
     vcom     "$IP_DIR/ip_arria10_ddio_in_1.vhd"                                                                                               
 
 
     set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_out_1/sim"
 
     #vlib ./work/         ;# Assume library work already exists
-    vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
-    vmap ip_arria10_ddio_out_1_altera_gpio_180      ./work/    
+    vmap ip_arria10_ddio_out_1_altera_gpio_core_194 ./work/
+    vmap ip_arria10_ddio_out_1_altera_gpio_194      ./work/    
     
-    vlog -sv "$IP_DIR/../altera_gpio_core_180/sim/mentor/altera_gpio.sv"                        -work ip_arria10_ddio_out_1_altera_gpio_core_180
+    vlog -sv "$IP_DIR/../altera_gpio_core_194/sim/mentor/altera_gpio.sv"                        -work ip_arria10_ddio_out_1_altera_gpio_core_194
     
-    vcom     "$IP_DIR/../altera_gpio_180/sim/ip_arria10_ddio_out_1_altera_gpio_180_c3jcq7i.vhd" -work ip_arria10_ddio_out_1_altera_gpio_180     
+    vcom     "$IP_DIR/../altera_gpio_194/sim/ip_arria10_ddio_out_1_altera_gpio_194_c3jcq7i.vhd" -work ip_arria10_ddio_out_1_altera_gpio_194     
     vcom     "$IP_DIR/ip_arria10_ddio_out_1.vhd"                                                                                                    
 
 } else {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
index 27316bba4be0b2742ec1fd35669bbf8c0c09aad6..9aa77ca037fb2f2f80b0dae026b7b1e022a14aad 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_ddr4_8g_1600
-hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_1600_altera_emif_180
+hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_180 ip_arria10_e2sg_altera_emif_cal_slave_nf_180 ip_arria10_e2sg_altera_avalon_onchip_memory2_180 ip_arria10_e2sg_altera_mm_interconnect_180 ip_arria10_e2sg_altera_reset_controller_180 ip_arria10_e2sg_altera_emif_arch_nf_180 ip_arria10_e2sg_altera_emif_180 ip_arria10_e2sg_altera_avalon_mm_bridge_180 ip_arria10_e2sg_altera_merlin_slave_translator_180 ip_arria10_e2sg_altera_avalon_sc_fifo_180 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_180 ip_arria10_e2sg_altera_ip_col_if_180 ip_arria10_e2sg_altera_jtag_dc_streaming_180 ip_arria10_e2sg_alt_mem_if_jtag_master_180 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_180 ip_arria10_e2sg_altera_avalon_packets_to_master_180 ip_arria10_e2sg_channel_adapter_180 ip_arria10_e2sg_timing_adapter_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_emif_cal_slave_nf_194 ip_arria10_e2sg_altera_avalon_onchip_memory2_194 ip_arria10_e2sg_altera_mm_interconnect_194 ip_arria10_e2sg_altera_reset_controller_194 ip_arria10_e2sg_altera_emif_arch_nf_194 ip_arria10_e2sg_altera_emif_194 ip_arria10_e2sg_altera_avalon_mm_bridge_194 ip_arria10_e2sg_altera_merlin_slave_translator_194 ip_arria10_e2sg_altera_avalon_sc_fifo_194 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_194 ip_arria10_e2sg_altera_ip_col_if_194 ip_arria10_e2sg_altera_jtag_dc_streaming_194 ip_arria10_e2sg_alt_mem_if_jtag_master_194 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_194 ip_arria10_e2sg_altera_avalon_packets_to_master_194 ip_arria10_e2sg_channel_adapter_194 ip_arria10_e2sg_timing_adapter_194
 
 hdl_lib_technology = ip_arria10_e2sg
 
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg
index ad4fc49ab4fe3afa4fc606e7442320901c26a26b..95fa72f14b4db6edd75c90ffd0b756c7b5d07d2b 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_ddr4_8g_2400
-hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_2400_altera_emif_180
+hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_180 ip_arria10_e2sg_altera_emif_cal_slave_nf_180 ip_arria10_e2sg_altera_avalon_onchip_memory2_180 ip_arria10_e2sg_altera_mm_interconnect_180 ip_arria10_e2sg_altera_reset_controller_180 ip_arria10_e2sg_altera_emif_arch_nf_180 ip_arria10_e2sg_altera_emif_180 ip_arria10_e2sg_altera_avalon_mm_bridge_180 ip_arria10_e2sg_altera_merlin_slave_translator_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_194 ip_arria10_e2sg_altera_emif_cal_slave_nf_194 ip_arria10_e2sg_altera_avalon_onchip_memory2_194 ip_arria10_e2sg_altera_mm_interconnect_194 ip_arria10_e2sg_altera_reset_controller_194 ip_arria10_e2sg_altera_emif_arch_nf_194 ip_arria10_e2sg_altera_emif_194 ip_arria10_e2sg_altera_avalon_mm_bridge_194 ip_arria10_e2sg_altera_merlin_slave_translator_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
index d3d03d20d597882aff8f6a889c304868f273cc79..a1afcae4f1b46411d335824d0a57a8ec7657f7c4 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_asmi_parallel
-hdl_library_clause_name = ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_180
+hdl_library_clause_name = ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_asmi_parallel_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_asmi_parallel_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
index 348f30e1b597e086b6994fafe076e6956be9a538..b35edc92f1f250ca34122bda9654725e35a0eae0 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_remote_update
-hdl_library_clause_name = ip_arria10_e2sg_remote_update_altera_remote_update_180
+hdl_library_clause_name = ip_arria10_e2sg_remote_update_altera_remote_update_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
index 0ee470a4ce9f54d0f2a680bb1a33134f2847c259..093474e35b574fab412aee5dc22de07b4e1f73e4 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_fractional_pll_clk125
 hdl_library_clause_name = ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_180 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_194 
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
index e0b939fec744b93c49bcfc0064c622b24a781cf3..f0a5deaef33c0bc96dcdfb8126d304b3a477d181 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_fractional_pll_clk200  
-hdl_library_clause_name = ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
index 649239b180b8c5541e6fdc95ac39cea72c1ffb65..3b8a784dce20fe212396acf98edd0d99f656c522 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_mac_10g
-hdl_library_clause_name = ip_arria10_e2sg_mac_10g_alt_em10g32_180
+hdl_library_clause_name = ip_arria10_e2sg_mac_10g_alt_em10g32_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_alt_em10g32_180
+hdl_lib_uses_sim = ip_arria10_e2sg_alt_em10g32_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
index 53afb110624ab2fb326243e7a2feec2315811a09..79f44d7c2db3faf9a08b339040a789848b3f7f8a 100644
--- a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
@@ -32,8 +32,8 @@
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mult_add4/sim"
 
 vmap  ip_arria10_e2sg_mult_add4 ./work/
-vmap  altera_mult_add_180       ./work/
+vmap  altera_mult_add_194       ./work/
 
 
-  vcom  "$IP_DIR/../altera_mult_add_180/sim/ip_arria10_e2sg_mult_add4_altera_mult_add_180_o5e3uui.vhd" -work altera_mult_add_180      
+  vcom  "$IP_DIR/../altera_mult_add_194/sim/ip_arria10_e2sg_mult_add4_altera_mult_add_194_o5e3uui.vhd" -work altera_mult_add_194      
   vcom  "$IP_DIR/ip_arria10_e2sg_mult_add4.vhd"                                                        -work ip_arria10_e2sg_mult_add4
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
index 1af09e1d6aea8af29a176a0daba0b137329c05b1..1b8890d3d7ac9d1ec6df284c9e5ceb86a050593a 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
index 629ab064772bfb78ad731f0f4ae066e8545d5fa5..3567d01df643b48e8f8ab8162a1f5fcb02c8554c 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_12
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
index ddf0e85afef65e03e6fd58bf78f2a58f034dd35c..aa36a182974bf125e05ed35c10a4589ff647fbec 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_24
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
index c9cfcb42a0df532ff2a6c5a20f02f72d14cf5e12..9f3ddacb670df61ec45739c9689a0613c391ca8c 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_3
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
index f30aeb66334106332bd0bf27ac97983583c98f44..2b6b7c7beee15d8903f6c817de82c78c03579e08 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_4
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
index 8710ab291e08cf3c9158453cd707480252a5b744..4723a9d7c4592bdf870979da5a0f539181fc6cad 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_48
-hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
index fda6b8e59ccd86456ce2815814c9473978cba1a9..8fe6e7c5ba294776c89ad0a02100de15b2554bb6 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_pll_clk125 
-hdl_library_clause_name = ip_arria10_e2sg_pll_clk125_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e2sg_pll_clk125_altera_iopll_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
index a6e13a55caf25212a950ddf1ed73cabaa79e8064..fc7bb42449bc3ef1bd7d39afb16c6ef9db3834ef 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_pll_clk200  
-hdl_library_clause_name = ip_arria10_e2sg_pll_clk200_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e2sg_pll_clk200_altera_iopll_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
index 899408e3da13746db868e5d261879ab663a1a5cf..4ebb54d09a00304cd89b64303cddd5c30b36a815 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_pll_clk25 
-hdl_library_clause_name = ip_arria10_e2sg_pll_clk25_altera_iopll_180
+hdl_library_clause_name = ip_arria10_e2sg_pll_clk25_altera_iopll_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
index a92ff004f54896f99ecfc0cf7d72ee5aeb4c44a4..c5c174a33131944754d4446a5aa5342b5f719b16 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_pll_xgmii_mac_clocks  
-hdl_library_clause_name = ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
index 46289f9ec305459f1f5df9c3933c4cb12ebdec0e..a93714fcde2da9b623187e3f54ae19695e82c8a9 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
@@ -31,7 +31,7 @@
 
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_temp_sense/sim"
 
-vmap  altera_temp_sense_180      ./work/
+vmap  altera_temp_sense_194      ./work/
 
-  vlog  "$IP_DIR/../altera_temp_sense_180/sim/altera_temp_sense.v" -work altera_temp_sense_180     
+  vlog  "$IP_DIR/../altera_temp_sense_194/sim/altera_temp_sense.v" -work altera_temp_sense_194     
   vcom  "$IP_DIR/ip_arria10_e2sg_temp_sense.vhd"                   
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
index ffb3cf79622f2a691f8aa840291b6a1e4f72c209..f09c783550f73e540f02d6b49ba886ff2f82781f 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
@@ -1,5 +1,5 @@
 hdl_lib_name = ip_arria10_e2sg_temp_sense 
-hdl_library_clause_name = ip_arria10_e2sg_temp_sense_altera_temp_sense_180
+hdl_library_clause_name = ip_arria10_e2sg_temp_sense_altera_temp_sense_194
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e2sg
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
index e94957fba13f0b4249679ca54aa39867292d57ed..b4ecca03eb26663a84dde9666bb06658ff0e473f 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_transceiver_pll_10g
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
index 4a0b08c882118f346b32bddce722b1adc1d7a136..d30d7f16bee770d2c03ddd9d4c7521aeb2a2a520 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_1
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
index 2508a58c562909e113b8f8c255a4823f4da31a50..3cafe88bc5af067697dc5cdaa0615eaf22eb80c4 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_12
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
index 77dad4207dc47e21b08e454a551c644bf736da4e..ce9acb98293373d6e2be48e1e676d788246656ed 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_24
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
index c3041472761a4d2222266c00aedd56a44f48c27b..7e5151ad9d64e50dc1f93a902a9d6b68a16bbff1 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_3
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
index 1afba83300023fa1019d5288140501261b0d5b98..0e479834ad37b2e11d3aeb8ba4ef1f32e61abc80 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_4
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
index 530f4e613ef31acf0e995e14245fa7f516834a17..240d3c9f516b09f5a9886eaa8a73cf69fdc6669f 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_48
-hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_194
 hdl_lib_uses_synth = 
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_194
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
index 80ce0bd3c7c62e5e4165a0eb0742dc7228129dc7..3b6dbf3dc99e11ae99bbf5cfbc198eb7feaf28ae 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_tse_sgmii_gx
-hdl_library_clause_name = ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_180
+hdl_library_clause_name = ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_194
 hdl_lib_uses_synth = common
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_eth_tse_180 
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_eth_tse_194 
 hdl_lib_technology = ip_arria10_e2sg
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
index f38591623c5f31378b6d5141b049539451165fec..46ed52d247e938125b9f95d58904df10414fa7a6 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
@@ -1,7 +1,7 @@
 hdl_lib_name = ip_arria10_e2sg_tse_sgmii_lvds
-hdl_library_clause_name = ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_180
+hdl_library_clause_name = ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_194
 hdl_lib_uses_synth = common
-hdl_lib_uses_sim = ip_arria10_e2sg_altera_eth_tse_180
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_eth_tse_194
 
 hdl_lib_technology = ip_arria10_e2sg
 
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
index f7efd9f340be3decdca4296b302597caee3a104a..574c7ff82e22cdf84668ea0c7d8894ff820c29de 100644
--- a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
@@ -32,16 +32,16 @@
 set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_voltage_sense/sim"
 
 vmap  ip_arria10_e2sg_voltage_sense          ./work/
-vmap  altera_voltage_sensor_180              ./work/
-vmap  altera_voltage_sensor_control_180      ./work/
-vmap  altera_voltage_sensor_sample_store_180 ./work/
+vmap  altera_voltage_sensor_194              ./work/
+vmap  altera_voltage_sensor_control_194      ./work/
+vmap  altera_voltage_sensor_sample_store_194 ./work/
 
 
-  vlog -sv  "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/altera_voltage_sensor_control.sv"                     -work altera_voltage_sensor_control_180     
-  vlog -sv  "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_avalon_controlr.sv"                    -work altera_voltage_sensor_control_180     
-  vlog -sv  "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_wrapper.sv"                            -work altera_voltage_sensor_control_180     
-  vlog -sv  "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store.sv"           -work altera_voltage_sensor_sample_store_180
-  vlog -sv  "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_ram.sv"       -work altera_voltage_sensor_sample_store_180
-  vlog -sv  "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_register.sv"  -work altera_voltage_sensor_sample_store_180
-  vcom      "$IP_DIR/../altera_voltage_sensor_180/sim/ip_arria10_e2sg_voltage_sense_altera_voltage_sensor_180_bqre2vy.vhd" -work altera_voltage_sensor_180             
+  vlog -sv  "$IP_DIR/../altera_voltage_sensor_control_194/sim/mentor/altera_voltage_sensor_control.sv"                     -work altera_voltage_sensor_control_194     
+  vlog -sv  "$IP_DIR/../altera_voltage_sensor_control_194/sim/mentor/voltage_sensor_avalon_controlr.sv"                    -work altera_voltage_sensor_control_194     
+  vlog -sv  "$IP_DIR/../altera_voltage_sensor_control_194/sim/mentor/voltage_sensor_wrapper.sv"                            -work altera_voltage_sensor_control_194     
+  vlog -sv  "$IP_DIR/../altera_voltage_sensor_sample_store_194/sim/mentor/altera_voltage_sensor_sample_store.sv"           -work altera_voltage_sensor_sample_store_194
+  vlog -sv  "$IP_DIR/../altera_voltage_sensor_sample_store_194/sim/mentor/altera_voltage_sensor_sample_store_ram.sv"       -work altera_voltage_sensor_sample_store_194
+  vlog -sv  "$IP_DIR/../altera_voltage_sensor_sample_store_194/sim/mentor/altera_voltage_sensor_sample_store_register.sv"  -work altera_voltage_sensor_sample_store_194
+  vcom      "$IP_DIR/../altera_voltage_sensor_194/sim/ip_arria10_e2sg_voltage_sense_altera_voltage_sensor_194_bqre2vy.vhd" -work altera_voltage_sensor_194             
   vcom      "$IP_DIR/ip_arria10_e2sg_voltage_sense.vhd"                                                                    -work ip_arria10_e2sg_voltage_sense         
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
index 176ede47d43cc7112cfcd6a775e2d4e49c0ec5eb..fd5645bdb7cc84ad3c1a1047f015593b812697db 100644
--- a/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
@@ -1,5 +1,5 @@
 hdl_lib_name = ip_arria10_e2sg_voltage_sense 
-hdl_library_clause_name = ip_arria10_e2sg_voltage_sense_altera_voltage_sense_180
+hdl_library_clause_name = ip_arria10_e2sg_voltage_sense_altera_voltage_sense_194
 hdl_lib_uses_synth = 
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e2sg
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index af4ed49167022faaad18b97797e3d3a08e98c2a0..527eb616fd1e5bf8b5ef40d71c7dd46832af8c31 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -1,12 +1,13 @@
 hdl_lib_name = tech_jesd204b
 hdl_library_clause_name = tech_jesd204b_lib
-hdl_lib_uses_synth = technology common dp ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b
+hdl_lib_uses_synth = technology common dp
 hdl_lib_uses_ip = ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b
 hdl_lib_uses_sim = 
-hdl_lib_technology = 
+#hdl_lib_technology = ip_arria10_e1sg ip_arria10_e2sg
+hdl_lib_technology =
 hdl_lib_disclose_library_clause_names =
-    ip_arria10_e1sg_jesd204b   ip_arria10_e1sg_jesd204b_alt_em10g32_180
-    ip_arria10_e2sg_jesd204b   ip_arria10_e2sg_jesd204b_alt_em10g32_194
+    ip_arria10_e1sg_jesd204b   ip_arria10_e1sg_jesd204b_180
+    ip_arria10_e2sg_jesd204b   ip_arria10_e2sg_jesd204b_194
 
 synth_files =
    tech_jesd204b_component_pkg.vhd
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
index 91c26a3c02cb1ac7f7841271e4d2f9119326acb6..c31fcb0a37cc2a3e532bbf99602589390aed6873 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
@@ -21,7 +21,7 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_mac_10g_alt_em10g32_180;
+LIBRARY ip_arria10_e2sg_mac_10g_alt_em10g32_194;
 
 LIBRARY IEEE, technology_lib, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
index 33de3adfe220d659202f0342d301475c837610ca..81551c38d3ac57bd2fd7fb4fae64c5f464e2de28 100644
--- a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_180;
-LIBRARY ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_180;
+LIBRARY ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_194;
+LIBRARY ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_194;
 
 ENTITY tech_tse_arria10_e2sg IS
   GENERIC (