diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index 6e1afe090410a47892968d35968d380aec9b075d..eac0affdf5d8716799a2c82b06a95dce6fc8401e 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -30,17 +30,19 @@
-- . g_nof_bytes is used to indicate the number of bytes in the data field. Only
-- used for deriving the DP empty field.
-- . g_use_empty: when true, it will derive the DP empty field from the AXI4 tkeep signal.
--- tkeep is the AXI4 signal that indicates with a bit for each byte of the data wheter
--- it is considered a valid or null byte. '1' for a valid byte or '0' for a null byte.
+-- tkeep is the AXI4 signal that indicates with a bit for each byte of the data whether
+-- it is considered a valid or null byte. '1' for a valid byte or '0' for a null byte.--
-- The DP empty field is derived by counting the number of '0' bits in
-- tkeep(g_nof_bytes DOWNTO 0). This means that it is only possible to derive the empty
-- field correctly when tkeep only has bits set to '0' at the end of the vector. For example:
-- . tkeep = "11111000" is valid and will translate to empty = 0011 (3 Decimal).
--- . tkeep = "11011101" is not valid.
+-- . tkeep = "11011101" is not valid and will result in a wrong empty signal of 0010 (2 Decimal).
+-- . Note that AXI4 always uses a symbol width of 8 (= byte) and thus the only DP symbol width
+-- used by the empty signal that is supported is also 8.
-- . g_axi4_rl is the ready latency of the axi4_in/out interfaces.
-- . g_dp_rl is the ready latency of the dp_in/out interfaces.
-- . g_active_low_rst should be set to TRUE when in_rst is active low. This is useful as an
--- AXI4 interface oftem comes with an active-low reset while DP comes with an active-high
+-- AXI4 interface often comes with an active-low reset while DP comes with an active-high
-- reset.
-- Remarks:
-- . AXI4 does not have a DP Xon or sync equivalent.
@@ -60,14 +62,11 @@ ENTITY axi4_stream_dp_bridge IS
g_active_low_rst : BOOLEAN := FALSE -- When True, in_rst is interpreted as active-low.
);
PORT (
- in_clk : IN STD_LOGIC := '0';
- in_rst : IN STD_LOGIC := is_true(g_active_low_rst); -- Default state is "not in reset".
+ in_clk : IN STD_LOGIC := '0';
+ in_rst : IN STD_LOGIC := is_true(g_active_low_rst); -- Default state is "not in reset".
- aclk : OUT STD_LOGIC := '0'; -- AXI4 clk
- aresetn: OUT STD_LOGIC := '1'; -- AXI4 active-low reset
-
- dp_clk : OUT STD_LOGIC := '0'; -- DP clk
- dp_rst : OUT STD_LOGIC := '0'; -- DP active-high reset
+ aresetn : OUT STD_LOGIC := '1'; -- AXI4 active-low reset
+ dp_rst : OUT STD_LOGIC := '0'; -- DP active-high reset
axi4_in_sosi : IN t_axi4_sosi := c_axi4_sosi_rst;
axi4_in_siso : OUT t_axi4_siso := c_axi4_siso_rst;
@@ -104,9 +103,7 @@ ARCHITECTURE str OF axi4_stream_dp_bridge IS
BEGIN
i_rst <= NOT in_rst WHEN g_active_low_rst ELSE in_rst;
- aclk <= in_clk;
aresetn <= NOT i_rst;
- dp_clk <= in_clk;
dp_rst <= i_rst;
----------------------------
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index 440c9f29a2f0b2a4b7c8c1028920334e4f9a5acc..ccb98c6b67b875e5103d8ea6e883fd98baf36f77 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -1,22 +1,49 @@
---------------------------------------------------------------------------------
---
--- Copyright (C) 2017
+-- --------------------------------------------------------------------------
+-- Copyright 2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- Author:
+-- . Reinier van der Walle (edits only, see Original)
+-- Purpose: General AXI stream record defintion
+-- Original:
+-- https://git.astron.nl/desp/gemini/-/blob/master/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+-- Remarks:
+-- * Choose smallest maximum SOSI slv lengths that fit all use cases, because unconstrained record
+-- fields slv is not allowed.
+-- * The large SOSI data field width of 256b has some disadvantages:
+-- . about 10% extra simulation time and PC memory usage compared to 72b
+-- (measured using tb_unb_tse_board)
+-- . a 256b number has 64 hex digits in the Wave window which is awkward because of the leading
+-- zeros when typically
+-- only 32b are used, fortunately integer representation still works OK (except 0 which is shown
+-- as blank).
+-- However the alternatives are not attractive, because they affect the implementation of the
+-- streaming
+-- components that use the SOSI record. Alternatives are e.g.:
+-- . define an extra long SOSI data field ldata[255:0] in addition to the existing data[71:0]
+-- field
+-- . use the array of SOSI records to contain wider data, all with the same SOSI control field
+-- values
+-- . define another similar SOSI record with data[255:0].
+-- Therefore define data width as 256b, because the disadvantages are acceptable and the benefit
+-- is great, because all
+-- streaming components can remain as they are.
+-- * Added sync and bsn to SOSI to have timestamp information with the data
+-- * Added re and im to SOSI to support complex data for DSP
--------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib;
@@ -27,25 +54,6 @@ USE dp_lib.dp_stream_pkg.ALL;
PACKAGE axi4_stream_pkg Is
- ------------------------------------------------------------------------------
- -- General DP stream record defintion
- ------------------------------------------------------------------------------
-
- -- Remarks:
- -- * Choose smallest maximum SOSI slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
- -- * The large SOSI data field width of 256b has some disadvantages:
- -- . about 10% extra simulation time and PC memory usage compared to 72b (measured using tb_unb_tse_board)
- -- . a 256b number has 64 hex digits in the Wave window which is awkward because of the leading zeros when typically
- -- only 32b are used, fortunately integer representation still works OK (except 0 which is shown as blank).
- -- However the alternatives are not attractive, because they affect the implementation of the streaming
- -- components that use the SOSI record. Alternatives are e.g.:
- -- . define an extra long SOSI data field ldata[255:0] in addition to the existing data[71:0] field
- -- . use the array of SOSI records to contain wider data, all with the same SOSI control field values
- -- . define another similar SOSI record with data[255:0].
- -- Therefore define data width as 256b, because the disadvantages are acceptable and the benefit is great, because all
- -- streaming components can remain as they are.
- -- * Added sync and bsn to SOSI to have timestamp information with the data
- -- * Added re and im to SOSI to support complex data for DSP
CONSTANT c_axi4_stream_data_w : NATURAL := 512; -- Data width, upto 512bit for Xilinx IP
CONSTANT c_axi4_stream_user_w : NATURAL := 70; -- User data, upto 70bit for Xilinx IP
CONSTANT c_axi4_stream_tid_w : NATURAL := 4; -- Thread ID, upto 4bit for Xilinx IP